Processors, methods, systems, and instructions for atomically storing data wider than a natively supported data width to memory

Abstract

The processor includes the widest set of data registers corresponding to a given logical processor. Each of the data registers in the widest set has a first width in bits. A decoding unit corresponding to the given logical processor decodes instructions specifying the widest set of data registers and decodes atomic store-to-memory instructions. The atomic store-to-memory instructions indicate data to have a second width in bits, which is wider than the first width in bits. The atomic store-to-memory instructions also indicate memory address information associated with a memory location. An execution unit is coupled to the decoding unit. In response to the atomic store-to-memory instructions, the execution unit atomically stores the indicated data into the memory location.

Description

Technical Field

[0001] The embodiments described herein generally relate to processors. Specifically, the embodiments described herein generally relate to ensuring the atomicity of memory in a processor. Background Technology

[0002] Many processors employ a Single Instruction Multiple Data (SIMD) architecture. In a SIMD architecture, packed data instructions, vector instructions, or SIMD instructions can operate on multiple data elements or pairs of data elements simultaneously or in parallel. The processor may have parallel execution hardware that responds to packed data instructions to execute multiple operations simultaneously or in parallel.

[0003] Multiple data elements can be packed into a single register as packed data or vector data. Within the packed data, the bits of other storage locations or registers can be logically divided into sequences of data elements. For example, a 128-bit wide packed data register can have two 64-bit wide data elements, four 32-bit data elements, eight 16-bit data elements, or sixteen 8-bit data elements. Each data element can represent a separate, independent piece of data (e.g., pixel color, complex components, etc.) and can be operated on individually and / or independently of the other data elements. Attached Figure Description

[0004] The invention can be best understood by referring to the following description and accompanying drawings, which illustrate embodiments. In the drawings: Figure 1 This is a block diagram of an embodiment of a processor that operates to execute atomic store-to-memory instructions to atomically store data wider than the natively supported data width into memory.

[0005] Figure 2 This is a block flowchart of an embodiment of an implementation of atomic store-to-memory instructions to atomically store data wider than the natively supported data width into memory.

[0006] Figure 3 This is a block diagram of another embodiment of the processor, which operates to execute atomic store-to-memory instructions to atomically store data wider than the natively supported data width into memory.

[0007] Figure 4 This is a block flowchart of a more detailed example embodiment of a method for executing atomic store-to-memory instructions.

[0008] Figure 5 This is a block diagram of an embodiment of a logic processor having a first detailed example embodiment of an execution unit, the execution unit including a hierarchical buffer and a write combination buffer.

[0009] Figure 6 This is a block diagram of an embodiment of a logic processor having an execution unit, which includes a hierarchical buffer and a write combination buffer.

[0010] Figure 7A This is a block diagram illustrating an embodiment of an ordered pipeline and an embodiment of a register renaming out-of-order issue / execution pipeline.

[0011] Figure 7B This is a block diagram of an embodiment of a processor core that includes a front-end unit coupled to an execution engine unit and both of which are coupled to a memory unit.

[0012] Figure 8A It is a block diagram of an embodiment of a single processor core along with its connection to the on-die interconnect network and a local subset of its Level 2 (L2) cache memory.

[0013] Figure 8B yes Figure 8A A block diagram of an embodiment of an expanded view of a portion of the processor core.

[0014] Figure 9 This is a block diagram of an embodiment of a processor that may have more than one core, an integrated memory controller, and integrated graphics.

[0015] Figure 10 This is a block diagram of a first embodiment of a computer architecture.

[0016] Figure 11 This is a block diagram of a second embodiment of a computer architecture.

[0017] Figure 12 This is a block diagram of a third embodiment of a computer architecture.

[0018] Figure 13 This is a block diagram of an embodiment of a system-on-a-chip architecture.

[0019] Figure 14 This is a block diagram illustrating how a software instruction converter is used to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. Detailed Implementation

[0020] This document discloses instructions for atomically storing data wider than the natively supported data width into memory, processors for executing the instructions, methods executed by the processor when processing or executing the instructions, and systems combining one or more processors to process or execute the instructions. In some embodiments, the processor may have a decoding unit or other logic for receiving and / or decoding instructions, and an execution unit or other logic for executing or otherwise performing the instructions. Many specific details (e.g., specific instruction operations, data formats, processor configurations, microarchitectural details, operation sequences, etc.) are set forth in the following description. However, embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this description.

[0021] Figure 1 This is a block diagram of an embodiment of processor 100, which operates to execute an embodiment of atomic store-to-memory instruction 108 to atomically store data wider than the natively supported data width into memory 125. In some embodiments, the processor may be a general-purpose processor (e.g., a general-purpose microprocessor or central processing unit (CPU) of the type used in desktop computers, laptop computers, or other computers). Alternatively, the processor may be a special-purpose processor. Examples of suitable special-purpose processors include, but are not limited to, network processors, communication processors, cryptographic processors, graphics processors, coprocessors, embedded processors, digital signal processors (DSPs), and controllers (e.g., microcontrollers).

[0022] Processor 100 includes at least one logical processor 101. A logical processor may also be referred to as a processor element. Examples of suitable logical processors include, but are not limited to, cores, hardware threads, thread units, and thread slots, as well as other logical processors or processor elements having a dedicated context or architectural state, including a program counter or instruction pointer. The term core is generally used to refer to logic located on an integrated circuit capable of maintaining an independent architectural state (e.g., an execution state), where the architectural state is associated with a dedicated execution and certain other resources. Conversely, the term hardware thread is often used to refer to logic located on an integrated circuit capable of maintaining an independent architectural state, where the architectural states share access to an execution or certain other resources. The boundary between such uses of the terms core and hardware thread may tend to be less distinct when two or more architectural states share an execution and / or other resource, and other executions or other resources are dedicated to an architectural state. However, cores, hardware threads, thread units, and thread slots, as well as other logical processors or processor elements, are generally considered by software as independent logical processors or processor elements. Generally, software threads, processes, or workloads can be scheduled on and independently associated with each of the cores, hardware threads, thread units, and thread slots, as well as other logical processors or processor elements.

[0023] The logic processor 101 has an instruction set architecture (ISA). An ISA represents the programming-related architectural portion of the logic processor and typically includes the natively supported instructions, architecture registers, data types, addressing modes, memory architecture, etc. An ISA differs from a microarchitecture, which generally represents the specific design technology chosen to implement the ISA. The logic processor can have any of the following: various Complex Instruction Set Computing (CISC) architectures, Reduced Instruction Set Computing (RISC) architectures, Very Long Instruction Word (VLIW) architectures, hybrid architectures, or other types of architectures. In some cases, the processor 100 may optionally have multiple logic processors, all of which may have the same ISA, or it may have two or more logic processors (with different ISAs) (e.g., different cores may have different ISAs).

[0024] The logic processor 101 and / or its ISA include architecture registers 110 (e.g., one or more architecture register files). Architecture registers may represent architecture-visible registers visible to software and / or a programmer and / or registers specified by instructions of the instruction set to identify operands. These registers contrast with other non-architecture or non-architecture-visible registers in a given microarchitecture (e.g., temporary registers, microarchitecture buffers, reorder buffers, etc.). For simplicity, architecture registers may also be simply referred to as registers herein. Each register may represent an on-die or on-processor storage location where data is stored.

[0025] Architecture register 110 may include various types of registers. Examples of such registers include, but are not limited to, general-purpose registers, packed data registers, program status registers, control registers, memory addressing registers, and so on. Packed data registers are sometimes also referred to in the art as vector registers or Single Instruction Multiple Data (SIMD) registers. Packed data registers can be operated to store packed data, vector data, or SIMD data. As shown, in some embodiments, the logic processor and / or architecture registers may include the widest set 114 of packed data registers. The widest set 114 of packed data registers represents the widest or largest set of packed data registers of the logic processor and / or the widest or largest set of packed data registers supported by the logic processor in terms of their bit width. In some embodiments, the logic processor and / or architecture registers may also optionally include a relatively narrow set 112 of packed data registers, or potentially include multiple sets of packed data registers of varying widths (each smaller than the width of each of the widest set 114 of packed data registers), although this is not required. As a particular non-limiting example, each register in the widest set 114 of packed data registers may have a width of 128 bits, while each register in the narrower set 112 of packed data registers may have a width of only 64 bits.

[0026] The logic processor 101 and / or its ISA also include an instruction set 102. Instructions in the instruction set refer to macro instructions, machine-level instructions, instructions provided to the logic processor for execution, or instructions that the logic processor is natively capable of decoding and executing, as opposed to microinstructions or microoperations (e.g., those arising from decoding instructions in the instruction set). The instruction set can include various different types of instructions. Several representative examples of these different types of instructions are shown and described below to illustrate certain concepts.

[0027] As shown, the instruction set may include a set of arithmetic and / or logical packed data instructions 104, each of which operates on the widest set 114 of packed data registers. As an example, arithmetic and / or logical packed data instructions may include a packed multiplication instruction for multiplying corresponding data elements at the same relative data element positions in two source registers of the widest set of packed data registers and storing the resulting product in one or a third of the two source registers. As another example, arithmetic and / or logical packed data instructions may include a packed addition instruction for adding corresponding data elements at the same relative data element positions in two source registers of the widest set of packed data registers and storing the resulting sum in one or a third of the two source registers. Similarly, packed logic instructions (e.g., packed logical AND instructions, packed logical OR instructions, packed logical ANDNOT instructions, packed logical XOR instructions, etc.) may optionally be present. Typically, anywhere from several to dozens (if not more) of these different types of packed data instructions may be present, each designed to operate on the widest set of packed data registers, although the scope of the invention is not limited to any such number of these instructions. The width of the widest set of packed data registers can represent the maximum size of packed data operands that arithmetic and / or logical packed data instructions can specify and / or use for operations on.

[0028] As shown, processor 100 and / or logic processor 101 may include at least one arithmetic and / or logic packed data execution unit (ALU) 118, which operates to execute arithmetic and / or logic packed data instructions 104 to operate on packed data operands stored in the widest set 114 of packed data registers. Dashed lines are used to indicate that execution and certain other resources (as discussed above) may be dedicated to the logic processor or shared by multiple logic processors. In some cases, the bit-scale width of the arithmetic and / or logic packed data execution unit may be the same as the bit-scale width of each register in the widest set of packed data registers. The bit-scale width of the arithmetic and / or logic packed data execution unit may represent the maximum bit-scale width of packed data operations it is capable of performing on one or more packed data operands (e.g., the maximum supported ALU operations). In other cases, the bit-scale width of the arithmetic and / or logic packed data execution unit may optionally be narrower than the bit-scale width of each register in the widest set of packed data registers, and different portions of operands from the widest set of packed data registers may be sent sequentially through the narrower execution unit in an interleaved or sequential manner. As an example, the first half of a 128-bit packed data operand can be sent through a 64-bit wide execution unit, and then the second half of the 128-bit packed data operand can be sent through a 64-bit wide execution unit.

[0029] In some cases, the bit-scale width of the bus or other interconnect used to deliver data directly to and / or from the widest set of packed data registers may be narrower than the bit-scale width of each of the widest set of packed data registers. For example, the width of the bus or other interconnect used to deliver data directly to and from the widest set of packed data registers may be only half the width of each of the widest set of packed data registers. In such cases, different portions (e.g., different halves) of data in a single packed data register of the widest set may be transmitted sequentially or at different times via the bus or other interconnect. As a particular example, two 64-bit halves of data from a single 128-bit packed data register of the widest set may be transmitted sequentially one after the other via a 64-bit interconnect.

[0030] As shown, the instruction set may also typically include at least one store-to-memory instruction 106 to store data from a single register in the widest set of packed data registers 114 to memory 125. The processor and / or logic processor may include a memory execution unit 120 operated to execute the store-to-memory instruction 106 to store data from a single register in the widest set of packed data registers to memory. As shown, the store-to-memory operation 122 may be transmitted to or otherwise provided to memory via a bus or other interconnect 123 to provide data from a single register in the widest set of packed data registers. In some cases, the bit-length width of the data transmitted on the bus or otherwise provided by operation 122 may be the same as the bit-length width of each register in the widest set of packed data registers. In other cases, the width of the data provided on the bus may be less than the width of the widest data register. In the latter case, the contents of the packed data registers of the widest set may be transmitted in two or more sequential transfers on the interconnect, and may optionally be grouped by start and stop indications such that they can form a single atomic memory.

[0031] Refer again Figure 1In some embodiments, the instruction set also includes at least one atomic store-to-memory instruction 108. An atomic store-to-memory instruction, when executed, is operable to cause the processor and / or logic processor to store data with a bit width wider than the natively supported data width into memory 125. As shown, the atomic store-to-memory operation 124 can be performed via a bus or other interconnect. Atomic storage can be such that all data is stored entirely, or no data is stored, but only a portion or subset of the data is guaranteed or ensured not to be stored. That is, a storage completion atomicity guarantee may exist. Atomicity can also guarantee that data stored by atomic storage will not be interleaved with data stored by other storage. Atomicity can be relative to other accesses to data such that any such access will observe all data stored entirely, or no data stored, but not only a portion or subset of the stored data. Atomicity can also be relative to power failures, system crashes, reboots, or other such events such that even in the face of such events, all data is stored entirely, or no data is stored, but only a portion or subset of the data is guaranteed or ensured not to be stored.

[0032] In some embodiments, atomic storage may be used for data wider than the natively supported data width of logic processor 101 and / or processor 100. The natively supported data width may be indicated differently in different embodiments. In some embodiments, the natively supported data width may represent the bit-level width of the widest set 114 of packed data registers, and / or the width of one or more packed data operands to be operated on or by arithmetic and / or logical packed data instructions 104. In some embodiments, the natively supported data width may represent the width of arithmetic and / or logical packed data execution unit 118 (e.g., when it has the same width of packed data operands indicated by the instructions such that multiple portions of the packed data operands are not sequentially pumped through it). In some embodiments, the natively supported data width may represent the width of a bus (e.g., a load pipe) that is narrower than the widest set of packed data registers used to directly transfer data to and from which data is transferred. For example, a processor may potentially have wide packed data registers, but the amount of data that can be stored atomically (i.e., without the methods disclosed herein) may be limited by the width of the bus derived from these wide packed data registers. In some embodiments, the natively supported data width may represent the width of the packed data operand to be stored in memory by the store-to-memory instruction 106. In some embodiments, the natively supported data width may represent the width of the data to be stored in memory by the store-to-memory operation 122. The natively supported data width relates at least to a logical processor 101 that executes the atomic store-to-memory instruction 108 and / or has an instruction set 102 that includes the atomic store-to-memory instruction 108. In some embodiments, the processor 100 may optionally have additional cores, hardware threads, or other logical processors (not shown) that may have different natively supported data widths, but such additional logical processors may not be logical processors that execute the atomic store-to-memory instruction 108 and / or may not have an instruction set that includes the atomic store-to-memory instruction 108.

[0033] There are various possible uses for this type of atomic storage operation. One example of this use is to atomically update a piece of data in a database. Another example is to atomically update shared data in a multiprocessing environment. Yet another example is to atomically pass data to a shared device (e.g., via a memory-mapped input-output (MMIO) register). For example, as will be explained further below, this can be used to assign or provide work to accelerator devices or other types of devices shared by multiple logical processors. Yet another possible example of this use is to atomically store data into a 3DXPoint. TMNon-volatile memory. Another example of this use is to atomically store data to a location to replace locks, semaphores, update shared variables, synchronize, coordinate, etc. Other uses of such atomic storage operations are still contemplated and will be apparent to those skilled in the art and of the benefit of this disclosure.

[0034] A storage completion atomicity guarantee for wider data can be a storage completion atomicity guarantee that is not typically achievable by executing multiple different instances of the store-to-memory instruction 106, each storing a different corresponding narrower portion of data from different corresponding registers of the widest set 114 of packed data registers. For example, different instances of the store-to-memory instruction will generally execute at different times. The cumulative amount of data from such differently timed store instructions will not all appear in memory simultaneously. Instead, different narrower portions of the data will typically be stored in memory at different times. Similarly, different narrower portions of the data will be delivered or provided in different timing transactions or signals on the bus or other interconnects. Due to the different times involved, it is possible for another logic processor to perform intervening read and / or store operations on the location where the data is to be stored in memory after only some of these different store operations have been executed. It is possible that after only some of these different store operations have been executed, an intervening power failure, system crash, reboot, or other such events may occur. Because of this possibility, such use of multiple storage instructions and / or different timing storage operations transmitted via a bus or other interconnection in different sequences to memory generally cannot be used to provide storage completion atomicity guarantees over a wider range of data.

[0035] exist Figure 1 In a specific example embodiment, the widest set 114 of packed data registers represents the widest data register of processor 100. However, in other embodiments, other data registers may represent the widest data register of the processor. Similarly, arithmetic and / or logical packed data instructions 104 indicate the widest packed data operand. However, in other embodiments, other instructions in the instruction set may specify the widest operand, which may not necessarily be a packed data operand. Similarly, in other embodiments, the instruction set may include store-to-memory instructions to indicate operands to be stored in another type of widest data register (i.e., not necessarily a packed data register) of memory. Likewise, execution unit 116 may include execution units to operate on other widest data registers (i.e., not necessarily packed data registers) and operands (i.e., not necessarily packed data operands).

[0036] Figure 2This is a block flowchart of an embodiment of method 226 for executing atomic store-to-memory instructions. In various embodiments, the method may be performed by a processor, instruction processing device, digital logic device, or integrated circuit.

[0037] The method includes receiving an atomic store-to-memory instruction at a given logic processor in block 228. In various aspects, the instruction may be received at the instruction fetch unit of the given logic processor, the instruction cache of the given logic processor, the prefetch unit of the given logic processor, or the decode unit of the given logic processor. The atomic store-to-memory instruction may specify (e.g., explicitly specify by one or more fields or bit sets) or otherwise indicate (e.g., implicitly indicate) the data to be atomically stored. In some embodiments, the indicated data may be bit-wider than the widest data register (e.g., the widest packed data register corresponding to the given logic processor), and other instructions of the instruction set of the given logic processor (e.g., any packed multiplication instruction, any packed addition instruction, any packed arithmetic and / or logic instructions, etc.) may be specified or otherwise indicated.

[0038] Several illustrative examples of suitable widths can be mentioned. For example, in some embodiments, the width of the indicated data may be 128 bits, and the width of the widest data register (e.g., the packed data register) may be 256 bits. In other embodiments, the width of the indicated data may be 128 bits, and the width of the widest data register (e.g., the packed data register) may be 512 bits. In still other embodiments, the width of the indicated data may be 128 bits, and the width of the widest data register (e.g., the packed data register) may be 1024 bits. In yet another embodiment, the width of the indicated data may be 256 bits, and the width of the widest data register (e.g., the packed data register) may be 512 bits. In a further embodiment, the width of the indicated data may be 256 bits, and the width of the widest data register (e.g., the packed data register) may be 1024 bits. In yet another embodiment, the width of the indicated data may be 512 bits, and the width of the widest data register (e.g., the packed data register) may be 1024 bits.

[0039] Atomic store-to-memory instructions may also specify (e.g., explicitly specify via one or more fields or bit sets) or otherwise indicate (e.g., implicitly indicate) memory address information. Memory address information may be associated with a memory location (e.g., the destination memory location where the data is to be atomically stored). For example, memory address information may be available (potentially combined with other information (e.g., information from segment registers, etc.)) to generate the memory address of the memory location. In some embodiments, the memory location may correspond to an MMIO range (e.g., the device's MMIO control register), although the scope of the invention is not so limited.

[0040] In various embodiments, the indicated data (e.g., data to be atomically stored in response to an instruction) may be initially stored in and / or accessed from different initial storage locations. In some embodiments, this data may initially be stored in multiple data registers (e.g., multiple widest packing data or other widest registers corresponding to a given logical processor). In such embodiments, the atomic store-to-memory instruction may specify or otherwise indicate at least one of these data registers (e.g., specifying one of the widest data registers in a consecutive sequence of widest data registers, where it is implicitly understood that other sequential registers are also used). Alternatively, in other embodiments, this data to be atomically stored may initially be stored in a source memory location. In such embodiments, the atomic store-to-memory instruction may specify or otherwise indicate additional memory address information associated with the source memory location (e.g., potentially used in conjunction with other information to generate a memory address for the source memory location). Similarly, in such embodiments, the atomic store-to-memory instruction may cause the data to be atomically stored to be initially loaded from this source memory location (e.g., loaded into multiple architecture widest packing data or other widest data registers corresponding to a given logical processor or loaded into one or more non-architectural temporary registers or storage locations of the processor).

[0041] The method further includes, at block 229, atomically storing indicated data into a memory location in response to and / or as a result of an atomic store-to-memory instruction. In some embodiments, this may include transferring the indicated data (which is wider than the widest packet of data or other widest register on a bus or other interconnect toward the memory location). In some embodiments, as will be further explained below, atomically storing the indicated data into a memory location may optionally be used to assign work to another device (e.g., an accelerator device), although the scope of the invention is not so limited.

[0042] The illustrated method involves architectural operations (e.g., those visible from a software perspective). In other embodiments, the method may optionally include one or more microarchitectural operations. As an example, instructions may be fetched by a fetch unit and / or a fetch unit corresponding to a given logical processor, decoded by a decode unit and / or a decode unit corresponding to a given logical processor, data may be accessed, and an execution unit corresponding to a given logical processor may perform microarchitectural operations to implement the instructions, etc. In some embodiments, the microarchitectural operations for implementing instructions may optionally include sequentially storing multiple portions of indicated data (which collectively represent the total indicated data) into a hierarchical buffer, and then simultaneously storing the total indicated data from the hierarchical buffer and / or multiple portions of the indicated data (e.g., storing to a write combination buffer), as will be explained in further detail below.

[0043] Figure 3 This is a block diagram of an embodiment of processor 300, which operates to execute an embodiment of atomic store-to-memory instruction 308. In various embodiments, the processor may represent at least a portion of an integrated circuit, may be included on a die or semiconductor substrate, may include semiconductor material, may include transistors, etc. In some embodiments, processor 300 may optionally be and / or include Figure 1 In processor 100, although this is not required. The optional features and details of processor 100 previously described may also optionally apply to processor 300. In some embodiments, processor 300 may optionally be used to perform... Figure 2 Method 226. The components, features, and specific optional details for processor 300 described herein may also be optionally applied to method 226, which may be optionally executed by processor 300. Alternatively, method 226 may be optionally executed by similar or different processors or devices. Furthermore, processor 300 may optionally execute methods similar to or different from method 226.

[0044] The processor includes at least a logic processor 301. The logic processor includes and / or supports an architecture-packed data register set 310. Each of the packed data registers may represent an on-die (or on-integrated circuit) storage location (operating to store packed data, vector data, or SIMD data). Packed data registers may be implemented in different ways in different microarchitectures and are not limited to any particular type of design. Examples of suitable types of registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, and combinations thereof. As shown, in some embodiments, the packed data registers 310 corresponding to and / or supported by the logic processor 301 may include a widest set 314 of packed data registers. Each of the widest set of packed data registers may have a first width in bits. In some embodiments, the packed data registers may optionally include a narrower set 312 of packed data registers, although this is not required. Each of the narrower set of packed data registers may have a narrower width than each of the widest set of packed data registers. In this particular example embodiment, the widest set 314 of packed data registers represents the widest data register of the processor, although in other embodiments, the other widest data registers of the processor may optionally be unpacked data registers.

[0045] During operation, processor 300 and / or logic processor 301 may receive atomic store-to-memory instructions 308. For example, instructions may be received from memory on a bus or other interconnect. In various embodiments, instructions may be stored in the instruction cache of the logic processor and / or a cache memory corresponding to the logic processor, may be fetched by a fetch unit of the logic processor and / or a fetch unit corresponding to the logic processor, etc. The instructions may represent macro instructions, machine code instructions, or other instructions or control signals of the instruction set of logic processor 301 and / or processor 300. In some embodiments, the atomic store-to-memory instruction may explicitly specify (e.g., by one or more fields or bit sets) or otherwise indicate (e.g., implicitly) that data 334 shall have a second bit width that is wider than a first bit width of each of the widest set of packed data registers (or other widest data registers of the processor).

[0046] To further illustrate, it may be helpful to specifically mention some illustrative examples of suitable widths. As examples, in some embodiments, the second width of the indicated data 334 may be 128 bits, and the first width of each of the widest packed data register 314 (or other widest architecture register) may be 256 bits. In other embodiments, the second width may be 128 bits and the first width may be 512 bits. In yet another embodiment, the second width may be 128 bits and the first width may be 1024 bits. In yet another embodiment, the second width may be 256 bits and the first width may be 512 bits. In a further embodiment, the second width may be 256 bits and the first width may be 1024 bits. In yet another embodiment, the second width may be 512 bits and the first width may be 1024 bits. These are merely a few illustrative examples of suitable widths.

[0047] The atomic store-to-memory instruction can also specify (e.g., explicitly specify via one or more fields or bit sets) or otherwise indicate (e.g., implicitly indicate) memory address information. The memory address information can be associated with a memory location 338 in memory 325 (e.g., a destination memory location), where the indicated data 334 is to be atomically stored as data 339 having a second width wider than a first width. For example, the indicated memory address information can be usable (potentially combined with other information, such as information from segment registers, etc.) to generate the memory address of the memory location. Various types of memory address information are possible. The indicated address information can represent absolute memory address information or relative memory address information, which can indicate a memory location relative to a base memory address or other memory locations. Furthermore, various different indirect memory addressing modes can optionally be used. As a specific example, an instruction may implicitly instruct a register (e.g., a general-purpose register) to store relative memory address information, which may be combined with additional memory address information stored in another implicit register (e.g., a code, data, or extended segment register) to generate a memory location 338 for identifying the first byte or other addressable memory element (in which data 339 is to be atomically stored). This is merely one example. Other forms of address information are also possible. Similarly, some or all of the address information may potentially be provided by bits of an instruction (e.g., an immediate value) rather than by providing address information in one or more registers.

[0048] In different embodiments, the indicated data 334 may initially be stored in and / or accessed from different initial storage locations. As shown, in some embodiments, data 334 may initially be stored in the widest packed data register 314 (or in other widest data registers). Because data 334 has a second width that is wider than the first width of each of the widest set of packed data registers, data may be stored in at least two of the widest set of packed data registers. In such embodiments, an atomic store-to-memory instruction may specify or otherwise indicate at least one of these multiple packed data registers of the widest set. For example, the instruction may have a field or set of bits to specify one of the widest set of packed data registers and may implicitly indicate one or more other packed data registers of the widest set (e.g., one or more sequential registers) (e.g., the processor may understand the use of these registers from the instruction's opcode without the instruction needing additional bits to explicitly specify it). Alternatively, in other embodiments, data 334 may alternatively be initially stored in a source memory location (not shown) in memory 325. In such embodiments, an atomic store-to-memory instruction may specify or otherwise indicate additional memory address information associated with the source memory location (e.g., potentially combined with other information to generate a memory address for the source memory location). Similarly, in such embodiments, an atomic store-to-memory instruction may cause data to be atomically stored to be initially loaded from this source memory location (e.g., loaded into multiple architecture-widest packed data registers 314 or loaded into one or more non-architectural temporary registers or storage locations (not shown) of the processor).

[0049] Refer again Figure 3The logic processor 301 includes a decoding unit or decoder 330. The decoding unit is operable to receive and decode instructions of the instruction set of the logic processor 301, including instructions (e.g., arithmetic and / or logic packing data instructions 104) specifying registers (or other widest data registers) in the widest set 314 of packing data registers. The decoding unit is also operable to receive and decode atomic store-to-memory instructions 308. The decoding unit may output one or more relatively low-level instructions or control signals (e.g., one or more microinstructions, microoperations, microcode entry points, decoding instructions, or control signals, etc.) that reflect, represent, and / or are derived from relatively high-level atomic store-to-memory instructions. In some embodiments, the decoding unit may include one or more input structures (e.g., one or more ports, one or more interconnects, interfaces) to receive atomic store-to-memory instructions, instruction identification and decoding logic coupled thereto to identify and decode atomic store-to-memory instructions, and one or more output structures (e.g., one or more ports, one or more interconnects, interfaces) coupled thereto to output one or more lower-level instructions or one or more control signals. The decoding unit can be implemented using a variety of different mechanisms, including but not limited to microcode read-only memory (ROM), lookup tables, hardware implementation, programmable logic arrays (PLA), and other mechanisms suitable for implementing the decoding unit.

[0050] In some embodiments, instead of directly providing atomic store-to-memory instructions to the decoding unit 330, an instruction emulator, converter, transformer, interpreter, or other instruction conversion module may be optionally used. Various types of instruction conversion modules can be implemented using software, hardware, firmware, or a combination thereof. In some embodiments, the instruction conversion module may be located external to the processor, such as, for example, on a separate die and / or in memory (e.g., as a static, dynamic, or runtime emulation module). As an example, the instruction conversion module may receive atomic store-to-memory instructions, which may have a first instruction set, and may emulate, translate, transform, interpret, or otherwise convert the atomic store-to-memory instructions into one or more corresponding intermediate instructions or control signals, which may have a second, different instruction set. One or more intermediate instructions or control signals of the second instruction set may be provided to the decoding unit (e.g., decoding unit 330), which may decode them into one or more lower-level instructions or control signals executable by the processor's native hardware (e.g., one or more execution units).

[0051] Refer again Figure 3The logic processor 301 also includes an execution unit 332. The execution unit 332 is coupled to the decoding unit 330 and to the packed data register 310. The execution unit may receive one or more decoded or otherwise converted instructions or control signals representing atomic store-to-memory instructions and / or derived from atomic store-to-memory instructions. The execution unit may also receive indicated data 334. The execution unit may operate in response to atomic store-to-memory instructions and / or as a result of atomic store-to-memory instructions (e.g., in response to one or more instructions or control signals decoded from instructions and / or in response to decoded instructions and / or in response to instructions provided to the decoding unit) to atomically store the indicated data 334 into memory location 338 as data 339. As shown, in some embodiments, data 339 may have a second width in bits, which is wider than the first width in bits of each of the registers (or other widest architecture data registers) of the widest set of packed data registers 314. This is one way in which data 334 and / or data 339 may be wider than the data width natively supported by the logic processor 301. In other embodiments, data 334 and / or data 339 may be wider than the data width natively supported by the logic processor 301 (in various other ways), as described elsewhere herein.

[0052] Execution unit 332 and / or logic processor 301 and / or processor 300 may include specific or concrete logic (e.g., transistors, integrated circuit modules, or other hardware potentially combined with firmware (e.g., instructions stored in non-volatile memory) and / or software) that operates in response to an atomic store-to-memory instruction and / or as a result of an atomic store-to-memory instruction (e.g., in response to one or more instructions or control signals decoded from an atomic store-to-memory instruction) to execute atomic store-to-memory instruction 308 and / or atomically store data 334 into memory 325. In some embodiments, the execution unit may include one or more input structures (e.g., one or more ports, one or more interconnects, interfaces) for receiving data 334, circuit modules or logic coupled thereto for receiving and processing data 334, and one or more output structures (e.g., one or more ports, one or more interconnects, interfaces) coupled thereto for outputting data 339 toward memory 325.

[0053] In some embodiments, the execution unit may include targets for Figure 5-6Any one or more circuit modules or logic shown and described herein are illustrative examples of suitable microarchitectural arrangements, although the scope of the invention is not so limited. As will be further explained below, in some embodiments, the execution unit may include a hierarchical buffer (not shown). In some embodiments, the execution unit, in response to an atomic store-to-memory instruction, may be operable to sequentially store multiple different portions of indicated data 334, which together represent an indication of a total amount, into the hierarchical buffer, and may then be operable to simultaneously store the indicated data of the total amount from the hierarchical buffer and / or multiple different portions of the indicated data. In some embodiments, the execution unit may also have a write combination buffer (not shown), and may optionally store the indicated data of the total amount into the write combination buffer simultaneously. Alternatively, the indicated data of the total amount may optionally be simultaneously stored to another storage location (e.g., a bus queue, another queue, etc.), written directly to a bus, etc. In some embodiments, the execution unit, in response to an atomic store-to-memory instruction, may also optionally be operable to configure the write combination buffer (if used) to disallow younger store operations from being merged with the write combination buffer after multiple different portions of the indicated data have been stored into the write combination buffer. In some embodiments, the execution unit may also optionally operate to configure the write combination buffer (if used) for evicting after multiple different portions of the indicated data have been stored into the write combination buffer (e.g., typically within one or about ten clock cycles of the logic processor).

[0054] To avoid ambiguity, relatively simple processors and logic processors have been shown and described. However, the processor may optionally include other processor components. For example, various different embodiments may include those for… Figure 7B and 8A Various combinations and configurations of any of the components shown and described in / B. All components of the processor can be coupled together to allow them to operate as intended.

[0055] Figure 4 This is a block flowchart of a more detailed example embodiment of method 440, which is an example embodiment of executing atomic store-to-memory instructions. In various embodiments, the method may be executed by a processor, instruction processing device, digital logic device, or integrated circuit. In some embodiments, method 440 may be performed by… Figure 3 The processor 300 and / or via Figure 3 The processor 300 and / or using Figure 3Instruction 308 is executed. The components, features, and specific optional details described herein with respect to processor 300 and / or instruction 308 may also optionally apply to method 440. Alternatively, method 440 may be executed by similar or different processors or devices and / or within similar or different processors or devices and / or using similar or different instructions. Furthermore, processor 300 may execute methods that are the same as, similar to, or different from method 440.

[0056] The method includes receiving an atomic store-to-memory instruction at a given logic processor at block 441. In some embodiments, the instruction may indicate a source operand having data. In some embodiments, the data may be wider than the data width natively supported by the given logic processor. For example, in some embodiments, the data may be wider than the given logic processor's and / or the widest packed data or other widest data register corresponding to the given logic processor and / or supported by the given logic processor. At block 442, in response to the instruction, multiple distinct portions of data representing the total amount from the source operand may be sequentially stored into multiple distinct corresponding portions of a hierarchical buffer. At block 443, in response to the instruction, the total amount of data and / or multiple distinct portions of the data stored in the hierarchical buffer may be simultaneously stored into a write combination buffer. At block 444, the write combination buffer may be optionally configured to disallow merging in response to the instruction after multiple distinct portions of the data have been stored into the write combination buffer. This helps prevent younger store operations (e.g., those younger than and / or subsequent to the atomic store-to-memory instruction in the original program sequence) from being merged with the write combination buffer. In block 445, the write combination buffer can be optionally configured to be evicted in response to the instruction after multiple distinct portions of data have been stored in the write combination buffer. In block 446, the write combination buffer can be evicted to the destination memory operand (e.g., a memory location) of the atomic store-to-memory instruction. In some embodiments, the actual eviction can be performed in response to the atomic store-to-memory instruction. In other embodiments, the actual eviction can be performed outside of the execution of the atomic store-to-memory instruction.

[0057] It should be understood that this is merely an illustrative example. In other embodiments, instead of a write combination buffer, the total amount of data may be stored from the hierarchical buffer to another storage location (e.g., a bus queue or other queue or buffer), or provided directly to the bus. For example, other embodiments may optionally omit box 445. Typically, the processor may instead be allowed to gradually evict the write combination buffer or evict it when it is ready. As another example, other embodiments may optionally omit box 444. Typically, the eviction of the write combination buffer may optionally be caused immediately after box 443, so that there is no need to configure the write combination buffer to disallow merging. As yet another example, boxes 444 and 445 may optionally be executed in the reverse order of those shown. Other embodiments may add additional operations, replacing one of the operations shown, etc., with different operations.

[0058] Figure 5 This is a block diagram of an embodiment of a logic processor 501 having an execution unit 532, which includes a hierarchical buffer and a write combination buffer 556, to execute an embodiment of an atomic store-to-memory instruction 508. In some embodiments, the logic processor 501 may optionally be used to execute Figure 2 Method 226 and / or Figure 4 Method 440. The components, features, and specific optional details for logic processor 501 described herein may also be optionally applied to method 226 and / or method 440. Alternatively, method 226 and / or method 440 may be optionally executed by similar or different processors or devices. Furthermore, logic processor 501 may optionally execute methods similar to or different from method 226 and / or method 440.

[0059] The logic processor 501 includes: a widest set 514 of packed data registers, each having a first width; a decoding unit 530 for receiving and decoding atomically stored-to-memory instructions 508; and an execution unit 532. In the illustrated example embodiment, the widest set of packed data registers represents the processor's widest architectural data register, although in other embodiments, other unpacked data registers may represent the widest data register. Unless otherwise stated, these components may optionally have... Figure 3 This describes some or all of the characteristics of the corresponding named component. To avoid ambiguity, the description will primarily focus on the different and / or additional characteristics, without repeating all characteristics that may optionally be the same or similar.

[0060] During operation, the decoding unit may operate to receive and decode instructions of the instruction set of the logic processor 501, including instructions specifying the widest data register (e.g., registers in the widest set of packed data registers 514) (e.g., arithmetic and / or logic packed data instructions 104). The decoding unit may also operate to receive and decode atomic store-to-memory instructions 508. In some embodiments, the atomic store-to-memory instruction may indicate a second width in bits that is wider than a first width in bits of each of the processor's widest data registers (e.g., registers in the widest set of packed data registers 514). As shown, in some embodiments, data may optionally be initially stored at least as a first data portion 550-1 of a first width in the first packed data register 514-1 of the widest set, and a second data portion 550-2 of a first width in the second packed data register 514-2 of the widest set. Alternatively, in other embodiments, data may alternatively be initially stored in a source memory location, as previously described.

[0061] Execution unit 532 is coupled to decoding unit 530 and to packing data register 510. The execution unit may operate in response to and / or as a result of atomic store-to-memory instruction 508 to atomically store indicated data 550-1, 550-2 to the destination memory operand and / or memory location indicated by the atomic store-to-memory instruction. As shown, in some embodiments, the execution unit may include hierarchical buffer 552 and write combination buffer 556. The hierarchical buffer and write combination buffer may be coupled together (e.g., the write combination buffer may be coupled to the output of the hierarchical buffer). In some embodiments, the hierarchical buffer may represent a new non-architectural or microarchitectural structure or storage. In some embodiments, the hierarchical buffer may be implemented by storage and / or logic that may optionally be similar to storage and / or logic used for write combination buffers but is generally simpler to implement due to more relaxed architectural guarantees and requirements than those for write combination buffers. In some embodiments, the hierarchical buffer may optionally be implemented in a memory execution unit, a memory execution cluster, although precise location of the hierarchical buffer implementation is not required.

[0062] In some embodiments, the execution unit, in response to instruction 508, may operate to sequentially store multiple distinct portions of data (e.g., first data portion 550-1 and second data portion 550-2) that collectively represent a total amount of data into different corresponding portions of a hierarchical buffer. In some embodiments, these distinct portions of data may be provided by different storage operations and may originate from a storage buffer that loads a storage queue, although the scope of the invention is not thus limited. As shown, the hierarchical buffer may have a first hierarchical buffer segment 554-1 of a first width for receiving and storing the first data portion 550-1, and a second hierarchical buffer segment 554-2 of a first width for receiving and storing the second data portion 550-2. Each of the first and second data portions may be stored at different times by different corresponding storage operations, such as storing data from a different corresponding one of the widest packed data registers (or other widest data registers) into different corresponding segments or portions of the hierarchical buffer. In the illustrated example, only the first and second data portions are shown, although in other embodiments, more than two portions (e.g., four, eight, etc.) may exist. In some embodiments, each segment may optionally be the same width as the widest packed data register or other widest register of the logic processor, although this is not required. In other embodiments, each segment may optionally be a quarter or half of the widest packed data of the logic processor or other widest register.

[0063] In some embodiments, after all distinct portions of data that collectively represent the total amount of data to be atomically stored in memory have been stored in different corresponding portions of the hierarchical buffer, the execution unit, in response to instruction 508, may operate to simultaneously store all distinct portions of data that collectively represent the total amount of data to be atomically stored from hierarchical buffer 552 into memory (e.g., to another storage location, to a bus, etc.). In the particular example shown, the other storage location to which this data is to be stored is shown as write combination buffer 556, although the scope of the invention is not so limited. As shown, the write combination buffer may have a first write combination buffer segment or portion 558-1 of a first width for storing data from a first hierarchical buffer segment or portion 554-1 of a first width, and a second write combination buffer segment or portion 558-2 of a first width for storing data from a second hierarchical buffer segment or portion 554-2 of a first width. In some embodiments, the write combination buffer may be allocated first and then filled with data from the hierarchical buffer in a single storage operation. In some embodiments, the write combination buffer may be implemented in a data cache memory cell (e.g., in a Level 1 (L1) data cache memory controller), although the scope of the invention is not so limited.

[0064] As shown, in some embodiments, the write combination buffer 556 may have one or more bits representing the non-merging field 560. In some embodiments, after multiple distinct portions of indicated data have been stored into the write combination buffer, the execution unit, in response to instruction 508, may optionally operate to configure the non-merging field of the write combination buffer to disallow merging (e.g., no merge allowed). As an example, this can help prevent younger store operations (e.g., younger than and / or subsequent to instruction 508 in the original program sequence) from merging with the write combination buffer. This can help prevent other data that is not expected to be part of the atomic storage into memory from unintentionally overwriting some data already in the write combination buffer that is to be atomically stored into memory.

[0065] As shown, in some embodiments, the write combination buffer 556 may have one or more bits representing the evict field 562. In some embodiments, after multiple different portions of indicated data have been stored in the write combination buffer, the execution unit, in response to instruction 508, may optionally operate to configure the evict field of the write combination buffer such that the write combination buffer is marked as and / or ready for evicting. In some embodiments, it may be desirable to perform this operation immediately or at least quickly after data has been stored from the hierarchical buffer into the write combination buffer. Typically, additional data should not be merged or stored into the write combination buffer at this time, so it is best to evict the write combination buffer as soon as possible so that it can then be recycled and used for other memory operations. Moreover, when data is used to assign work to accelerator devices or other devices, as will be discussed further below, it is generally best to send this data earlier rather than later so that other devices can begin to work on it. As an example, such configuration may typically be performed within about one to about ten clock cycles of the logic processor, or about one to about five clock cycles, although this is not required. The evicting of the write combination buffer may continue to memory via the memory subsystem. In some embodiments, atomic memory operations may bypass and / or not store in one or more cache memories of the processor. For example, they may be write-combined non-cacheable memory.

[0066] Advantageously, including a hierarchical buffer 552 as a separate structure from the write combination buffer 556 can tend to help simplify implementation. In some embodiments, the write combination buffer can be designed to support the architectural capability of being dumped, flushed, or evicted from memory at any given point in time. Without a separate hierarchical buffer, if the write combination buffer is used instead to accumulate different data portions of an atomic storage operation, a dump, flush, or evicting from memory can occur at an intermediate point in time when some, but not all, of the different data portions of the atomic storage operation are stored in the write combination buffer. However, guaranteeing the atomicity of the entire storage operation generally implies that storage of such incomplete portions of the total storage should not be performed, but rather only the entire storage or no storage should be performed. However, it is not required that the hierarchical buffer support the capability of being flushed or evicted from memory at any given point in time. Accordingly, the hierarchical buffer can accumulate or collect all the different data portions of an atomic storage operation and then write all these different data portions to the write combination buffer in one operation. This can help ensure the atomicity of the storage of all data. Alternatively, if desired, the hierarchical buffer can be omitted, and a write combination buffer can be used instead, wherein when some, but not all, of the different data portions of an atomic store operation are stored in the write combination buffer, it is modified at least at an intermediate point in time when the write combination buffer is used to implement the atomic store-to-memory instruction 508 to prevent dump clearing or eviction to memory. For example, a given write combination buffer can be dedicated, reserved, or locked specifically for the implementation of the atomic store-to-memory instruction so that it is treated differently (e.g., the ability to dump clear or eviction to memory at any given point in time when implementing the atomic store-to-memory instruction is not required).

[0067] Figure 6 This is a block diagram of an embodiment of a logic processor 601 having an execution unit 632, which includes a hierarchical buffer and a write combination buffer 656 to execute an embodiment of an atomic store-to-memory instruction 608. In some embodiments, the logic processor 601 may optionally be used to execute Figure 2 Method 226 and / or Figure 4 Method 440. The components, features, and specific optional details described herein with respect to logic processor 601 may also be optionally applied to method 226 and / or method 440. Alternatively, method 226 and / or method 440 may be optionally executed by similar or different processors or devices. Furthermore, logic processor 601 may optionally execute methods similar to or different from method 226 and / or method 440.

[0068] The logic processor 601 in this particular example includes a 128-bit packed data register set 614 (which represents the widest set of data registers of the logic processor and / or the widest set of data registers supported by the logic processor), a decoding unit 630 for receiving and decoding atomically stored instructions to memory 608, and an execution unit 632. Unless otherwise stated or otherwise clearly apparent, these components may optionally have Figure 3 The corresponding named components possess some or all of their characteristics. The execution unit in this particular example includes a 512-bit hierarchical buffer 652 and a 512-bit write combination buffer 656. Unless otherwise stated or clearly apparent, the hierarchical buffer and write combination buffer may optionally have... Figure 5 This describes some or all of the characteristics of those hierarchical buffers and write combination buffers. To avoid ambiguity, the different and / or additional characteristics will be described primarily, without repeating all characteristics that may optionally be the same or similar.

[0069] exist Figure 6 In this embodiment, the 128-bit packed data register 614 is the widest data register of the logic processor 601 and / or the widest data register supported by the logic processor 601. The atomic store-to-memory instruction 608 indicates data to be atomically stored to memory, which includes a first 128-bit data portion 650-1, a second 128-bit data portion 650-2, a third 128-bit data portion 650-3, and a fourth 128-bit data portion 650-4. The first 128-bit data portion 650-1 is stored in the first 128-bit packed data register 614-1, the second 128-bit data portion 650-2 is stored in the second 128-bit packed data register 614-2, the third 128-bit data portion 650-3 is stored in the third 128-bit packed data register 614-3, and the fourth 128-bit data portion 650-4 is stored in the fourth 128-bit packed data register 614-4. In other embodiments, temporary registers may alternatively be used to hold data loaded from source memory operands, as described elsewhere herein. Furthermore, 128 bits is merely an illustrative example of a suitable size for these data portions and the widest data register. In other embodiments, they may, for example, be 64 bits, 256 bits, or 512 bits, respectively.

[0070] Decoding unit 630 is coupled to microcode read-only memory (ROM) 668. The microcode ROM can be used to store microcode, microinstructions or other lower-level instructions, control signals, or certain instructions (including atomic store-to-memory instruction 608) for a logic processor's instruction set. As an example, the decoding unit can decode the atomic store-to-memory instruction into a microcode entry point at an appropriate point in the microcode within the microcode ROM to retrieve the microcode, microinstruction, or other lower-level instructions, control signals, or operations (e.g., microcode sequences) to implement the atomic store-to-memory instruction. The identified lower-level instructions or control signals (e.g., microcode sequences) can be output from the microcode ROM to the execution unit to implement the atomic store-to-memory instruction.

[0071] As shown in the example embodiments illustrated, the microcode ROM may include a store-to-hierarchical buffer instruction, control signal, or operation 670, and a store-from-hierarchical-buffer-write instruction, control signal, or operation 671. In some embodiments, the store-to-hierarchical-buffer operation 670 may be performed to store a specified or indicated one of a plurality of hierarchical buffer segments or portions (e.g., four different 128-bit hierarchical buffer segments or portions 654 in this example) from its initial storage location (e.g., one of the 128-bit packed data registers 614 in this example) to a specified or indicated one of a plurality of different hierarchical buffer segments or portions (e.g., four different 128-bit hierarchical buffer segments or portions 654 in this example). For example, a first instance of the store-to-hierarchical-buffer operation may be performed to perform a first store operation 672-1 to store a first 128-bit data portion 650-1 to a first 128-bit hierarchical buffer portion or segment 654-1, and a second instance of the store-to-hierarchical-buffer operation may be performed to perform a second store operation 672-2 to store a second 128-bit data portion 650-2 to a second 128-bit hierarchical buffer portion or segment 654-2. Continuing, a third instance of the storage-to-hierarchical-buffer operation can be performed to execute a third storage operation 672-3 to store the third 128-bit data portion 650-3 into the third 128-bit hierarchical-buffer portion or segment 654-3, and a fourth instance of the storage-to-hierarchical-buffer operation can be performed to execute a fourth storage operation 672-4 to store the fourth 128-bit data portion 650-4 into the fourth 128-bit hierarchical-buffer portion or segment 654-4. In this particular example, the hierarchical buffer is a 512-bit hierarchical buffer, although the scope of the invention is not so limited.

[0072] In some embodiments, the storage to hierarchical buffer operation 670 may indicate the data to be copied. In this example, a 128-bit portion of the data is used, although in other examples, a wider or narrower portion of the data may be used instead. For example, the operation may have one or more bits or fields to specify one of the following: a 128-bit packed data register 614 with data 650, or a temporary register with data, etc. The operation may also have one or more bits or fields to specify or otherwise indicate one of a plurality of different segments or portions 654 of the hierarchical buffer. Typically, it is not necessary to address the hierarchical buffer with a full memory address. Instead, a simple index or selector value can be used to index, address, or select one of a plurality of different segments or portions of the hierarchical buffer. For example, a 1-bit index can be used to index or select between two sections or portions of the hierarchical buffer, or a 2-bit index can be used to index or select between four sections or portions of the hierarchical buffer, and a 3-bit index can be used to index or select between eight sections or portions of the hierarchical buffer. Accordingly, for this store operation, the base and index (e.g., those used for addressing memory in other operations) can be set to zero, the scale can be set to 1, and 1-bit, 2-bit, or 3-bit indices can be configured with appropriate values ​​to index or select one of the different segments or portions of the hierarchical buffer on which data is to be stored. Furthermore, since the hierarchical buffer does not need to be addressed with its full memory address, there is no need for this store operation to search the translation backing buffer (TLB). There is also no need to support data forwarding to younger loads. This store operation can be non-blocking because address collisions and other issues are not required. There is also no need to perform breakpoint detection or any "nukes." This store operation is also not subject to ordering restrictions.

[0073] In some embodiments, after four distinct 128-bit data portions 650 have been stored into the hierarchical buffer 652, execution unit 632, in response to instruction 608, may operate to perform a storage operation 671 from the hierarchical buffer to the write combination buffer to simultaneously store the entire contents of the hierarchical buffer 652 (a 512-bit hierarchical buffer in this specific example) into the write combination buffer 656 (a 512-bit write combination buffer in this specific example) in a single storage operation. Alternatively, instead of the write combination buffer, another storage location may be optionally used, or data may optionally be provided directly to a bus or other interconnect. In some embodiments, this storage operation may be allowed to be merged with an older write combination buffer. Alternatively, if this storage operation is not merged with an older write combination buffer, it may be remissed and a write combination fill buffer may be allocated. When remissed, this storage operation may block anything subsequent in the pipeline (e.g., younger storage operations) and older storage pipelines that may use data cache to fill ports, such as resource conflict conditions, and fill the allocated write combination buffer with the contents of the hierarchical buffer.

[0074] In some embodiments, operation 671 may use a memory address based on memory address information indicated by the atomic store-to-memory instruction 608. As a particular example, a linear address may be calculated using the offset from the segment register added to the base address as indicated by the atomic store-to-memory instruction, along with the base, scale, and index, although the scope of the invention is not limited in this respect. In some embodiments, storage, all address calculations, and rights and limits checks may be associated with a 512-bit address size and operand size used for the operation, although the scope of the invention is not limited in this respect. In some embodiments, in 64-bit mode, canonical address form violations may be checked instead of segment limit checks, although the scope of the invention is not limited in this respect. In some embodiments, when generating a linear address for storage, if the linear address is not 64-byte aligned, it may cause a general protection failure, although the scope of the invention is not limited in this respect. In some embodiments, operation 671 may force the memory type to be unbuffered randomized write (USWC), regardless of the underlying memory type. This storage operation is a weakly ordered storage operation.

[0075] In some embodiments, depending on the specific implementation, the memory corresponding to operation 671 may optionally be marked as non-forwardable. Typically, the processor may have the ability to satisfy a younger load using the result of an older memory via internal bypass, where the older memory data is routed to the younger load. However, in some implementations, preventing such forwarding may be desirable. For example, this could be the case when an atomic store-to-memory instruction is used to submit work to an accelerator device, where it may be appropriate for a younger read to obtain data from the actual destination memory location if the accelerator device modifies the data (after it has already been stored in the destination memory location). In other embodiments, such as for other uses of the atomic store-to-memory instruction, there may not be a need to mark the memory as non-forwardable.

[0076] As shown, in some embodiments, the write combination buffer 656 may have one or more bits representing a non-merge field 660 and one or more bits representing an evict field 662. In some embodiments, operation 671 may optionally operate to configure the non-merge field of the write combination buffer to disallow merging (e.g., no merging is allowed), and may optionally operate to configure the evict field of the write combination buffer such that the write combination buffer is marked as and / or ready for evict.

[0077] The atomic store-to-memory instructions disclosed herein can provide architecture-supported atomic storage for the total width of the data to be stored. Furthermore, in some embodiments, data to be atomically stored can initially be loaded from a source memory operand. In some embodiments, due to the atomicity of the store-to-memory operation, if any part of the implementation of the atomic store-to-memory instruction fails, experiences a violation or exceptional condition, or otherwise fails, a portion of the data should not be transferred on the bus to memory, and the portion of the data should not be stored in memory. In some embodiments, breakpoints, range-based checks, fault checks, etc., can be performed over the entire width of the destination operand on which the data is to be atomically stored. As an example, in response to an atomic store-to-memory instruction, the execution unit can generate memory addresses for the first and last bytes of the memory location where the data is to be atomically stored (e.g., using any of a variety of possible addressing modes), and when the atomic store-to-memory instruction is retired or committed, the processor can perform checks and signaling for segment limit violations, range-based violations, faults, breakpoints, etc., on any byte from the first byte to the last byte. As an example, regarding breakpoints, it is possible that breakpoints have been potentially configured on any byte of the destination memory location, which is used to store the data to be stored atomically. In some embodiments, if a breakpoint exists on any of these bytes, the breakpoint can be signaled when the instruction completes (e.g., retire or commit).

[0078] In some embodiments, the atomic store-to-memory instructions disclosed herein can be employed as part of an algorithm to transfer data to another device (e.g., an accelerator device, an input and / or output (I / O) device (e.g., a high-performance memory controller), etc.) via mutually accessible storage locations in memory. As an example, an atomic store-to-memory instruction can represent a work commit instruction, which is employed as part of an algorithm or instruction set that a logic processor can execute to store data associated with a work or task to be performed by the accelerator device into a memory location, and the accelerator device can retrieve the data from the memory location. In some cases, the memory location can correspond to an MMIO range (e.g., the device's MMIO control register in the device's MMIP space). A wide variety of different types of accelerators are suitable, such as, for example, graphics accelerators, connected accelerators, machine learning accelerators, computer vision accelerators, cryptographic accelerators, fixed-function accelerators, general-purpose graphics processing units (GPGPUs), field-programmable gate arrays (FPGAs), etc., to name just a few. The memory location can represent a logic register (e.g., a work commit register) or other interface (through which the processor and accelerator device communicate). In some embodiments, the memory location may also be accessible from one or more other logic processors, which may also use the memory location to transfer data to a device (e.g., assign work to an accelerator device). In such embodiments, the ability to atomically store an entire amount of data into a memory location can be advantageous, as one or more other logic processors may be unable to perform interfering storage (e.g., simultaneous or interleaved storage to the same memory location and thus data contamination), which could corrupt the entire amount of data, incorrectly assign work, etc. Atomic store-to-memory instructions can help ensure that an entire amount of data (e.g., an entire logical register in memory) is stored at once and by only a single logic processor. Furthermore, atomic store-to-memory instructions can provide an efficient way for two or more logic processors to assign work to the same accelerator device without needing to synchronize or coordinate with each other, acquire locks, etc.

[0079] In some embodiments, different types of atomic store-to-memory instructions may exist for implementing work commit instructions or other instructions for transferring data to another device. One such type may not expect a response from other devices associated with the atomic storage of data to memory. For this type, the processor's retire or commit unit can retire or commit the atomic store-to-memory instruction after the data has been atomically stored in memory, without waiting for and / or needing to receive a response from other devices.

[0080] Another type of atomic store-to-memory instruction can anticipate responses from other devices associated with the atomic storage of data to memory. For example, a response from another device could indicate that the atomic storage of data to memory has been observed, acknowledged, received, or accepted (e.g., a work submission has been accepted), etc. Typically, such a response could indicate to the logic processor performing the atomic storage operation that the atomic storage operation is fully observed in the system and is now fully consistent. This response can be provided in various ways, such as by configuring one or more bits in a register or memory location of the processor that is architecturally visible (e.g., setting one or more status bits in a status register), by providing dedicated signals, by configuring one or more bits in the destination memory location, or otherwise. For this type of atomic store-to-memory instruction, after the data has been atomically stored in memory, the processor's retirement unit can wait to retire the atomic store-to-memory instruction until such a response is received from another device. Until retirement, instructions can command younger strongly ordered instructions, such as fence instructions, strongly ordered store instructions, locking instructions, etc., until the instruction is retired (e.g., when the atomically stored data is observed globally in the system and is completely consistent).

[0081] As a specific example, such a response could instruct a logic processor that an atomic store operation results in a work submission accepted by the accelerator device. As an example, the accelerator device could have an internal work queue or buffer (e.g., a shared work queue) fed by data stored to the destination memory location of an atomic store-to-memory instruction (e.g., a shared work queue portal register mapped by MMIO). In some cases, the internal work queue or buffer may have sufficient storage space or capacity to accept data from an atomic store operation, data can be moved from the destination memory location into the internal work queue or buffer, and the accelerator device can provide a response indicating that the work submission is accepted by the accelerator device. In other cases, the internal work queue or buffer may not have sufficient storage space or capacity to accept data from an atomic store operation, and the accelerator device can provide a response indicating that the work submission is not accepted by the accelerator device.

[0082] Exemplary core architectures, processors, and computer architectures

[0083] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) CPUs comprising one or more general-purpose ordered cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors comprising one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU; 2) coprocessors on a separate die in the same package as the CPU; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) on-chip systems that may include the described CPU (sometimes referred to as one or more application cores or one or more application processors), the coprocessors described above, and additional functionalities, all on the same die. The exemplary core architecture is then described, followed by descriptions of exemplary processors and computer architectures.

[0084] Exemplary core architecture

[0085] Ordered and disordered kernel diagram

[0086] Figure 7A It is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order release / execution pipeline according to embodiments of the present invention. Figure 7B It is a block diagram illustrating exemplary embodiments of ordered architecture cores to be included in a processor according to embodiments of the present invention, and exemplary register renaming, out-of-order release / execution architecture cores. Figure 7A The solid boxes in -B represent ordered pipelines and ordered cores, while the optional dashed boxes represent register renaming, out-of-order release / execution pipelines, and cores. Given that the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0087] exist Figure 7A In this process, the processor pipeline 700 includes a fetch stage 702, a length decoding stage 704, a decoding stage 706, an allocation stage 708, a renaming stage 710, a scheduling (also known as dispatch or issue) stage 712, a register read / memory read stage 714, an execution stage 716, a write-back / memory write stage 718, an exception handling stage 722, and a commit stage 724.

[0088] Figure 7BA processor core 790 is shown, which includes a front-end unit 730 coupled to an execution engine unit 750, and both are coupled to a memory unit 770. Core 790 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. As another option, core 790 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0089] Front-end unit 730 includes a branch prediction unit 732 coupled to an instruction cache memory unit 734, which is coupled to an instruction translation lookaside buffer (TLB) 736, which is coupled to an instruction fetch unit 738, which is coupled to a decoding unit 740. Decoding unit 740 (or decoder) decodes instructions and generates outputs of one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals, which are decoded from, or otherwise reflected in, or derived from the original instruction. Decoding unit 740 can be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROMs), etc. In one embodiment, core 790 includes a microcode ROM or other medium (e.g., in decoding unit 740 or otherwise within front-end unit 730) storing microcode for certain macro instructions. The decoding unit 740 is coupled to the rename / allocator unit 752 in the execution engine unit 750.

[0090] The execution engine unit 750 includes a rename / allocator unit 752 coupled to a set of retirement units 754 and one or more scheduler units 756. The scheduler units 756 represent any number of different schedulers, including reservation stations, central instruction windows, etc. One or more scheduler units 756 are coupled to one or more physical register file units 758. Each of the physical register file units 758 represents one or more physical register files, which store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer to the address of the next instruction to be executed), etc. In one embodiment, the physical register file unit 758 includes vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. One or more physical register file units 758 are overlapped by a retirement unit 754 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future heaps, one or more history buffers, and one or more retirement register files; using register mappings and register pools; etc.). The retirement unit 754 and one or more physical register file units 758 are coupled to one or more execution clusters 760. One or more execution clusters 760 include a set of one or more execution units 762 and a set of one or more memory access units 764. Execution units 762 can perform various operations (e.g., shift, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include multiple execution units that all perform all functions or only one execution unit. One or more scheduler units 756, one or more physical register file units 758, and one or more execution clusters 760 are shown as possibly multiple, because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler unit, physical register file unit, and / or execution cluster—and in the case of separate memory access pipelines, some embodiments in which only the execution cluster of this pipeline has one or more memory access units 764 are implemented). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order deployment / execution, and the remainder may be ordered.

[0091] A set of memory access units 764 is coupled to memory unit 770, which includes a data TLB unit 772 coupled to data cache memory unit 774, which is coupled to level 2 (L2) cache memory unit 776. In one exemplary embodiment, memory access unit 764 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 772 in memory unit 770. Instruction cache memory unit 734 is further coupled to level 2 (L2) cache memory unit 776 in memory unit 770. L2 cache memory unit 776 is coupled to one or more other levels of cache memory and ultimately to main memory.

[0092] By way of example, the exemplary register renaming, out-of-order release / execution core architecture can implement the following pipeline 700: 1) Instruction fetch 738 executes fetch and length decoding stages 702 and 704; 2) Decoding unit 740 executes decoding stage 706; 3) Rename / allocator unit 752 executes allocation stage 708 and rename stage 710; 4) One or more scheduler units 756 execute scheduling stage 712; 5) One or more physical register file units 758 and memory units 770 execute register read / memory read stage 714; execution cluster 760 executes execution stage 716; 6) Memory unit 770 and one or more physical register file units 758 execute write-back / memory write stage 718; 7) Various units may be involved in exception handling stage 722; and 8) Retirement unit 754 and one or more physical register file units 758 execute commit stage 724.

[0093] Core 790 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set of ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including one or more instructions described herein. In one embodiment, core 790 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thus allowing operations used by many multimedia applications to be performed using packaged data.

[0094] It should be understood that a core can support multithreading (the execution of two or more parallel sets of operations or threads), and can do so in a variety of ways, including time-segmented multithreading, simultaneous multithreading (in the case of a single physical core providing logical cores for each thread, that physical core is performing simultaneous multithreading), or combinations thereof (e.g., such as in...). (Time-segmented fetching and decoding in hyper-threading technology and subsequent simultaneous multithreading).

[0095] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated embodiment of the processor also includes separate instruction and data cache memory units 734 / 774 and a shared L2 cache memory unit 776, alternative embodiments may have a single internal cache memory for both instructions and data, such as, for example, a Level 1 (L1) internal cache memory, or multiple levels of internal cache memory. In some embodiments, the system may include a combination of internal cache memory and external cache memory external to the core and / or processor. Alternatively, all cache memory may be external to the core and / or processor.

[0096] Specific exemplary ordered kernel architecture

[0097] Figure 8A -B illustrates a block diagram of a more specific, exemplary, ordered core architecture where the core is one of several logic blocks in a chip (including other cores of the same type and / or different types). The logic blocks communicate with some fixed functional logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network), depending on the application.

[0098] Figure 8A This is a block diagram of a single processor core according to an embodiment of the invention, along with its connections to an on-die interconnect network 802 and its local subset of a Level 2 (L2) cache memory 804. In one embodiment, the instruction decoder 800 supports the x86 instruction set with Packed Data Instruction Set Extensions. The L1 cache memory 806 allows low-latency access to cache memory into scalar and vector units. Although in one embodiment (for design simplification), scalar unit 808 and vector unit 810 use separate register sets (correspondingly, scalar register 812 and vector register 814), and data transferred between them is written to memory and then read back from the Level 1 (L1) cache memory 806, alternative embodiments of the invention may use different means (e.g., using a single register set or including a communication path that allows data to be transferred between the two register sets without being written and read back).

[0099] The local subsets of L2 cache 804 are part of the global L2 cache, which is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of L2 cache 804. Data read by a processor core is stored in its L2 cache subset 804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 804 and is dumped from other subsets if necessary. A ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 cache, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0100] Figure 8B This is according to an embodiment of the present invention. Figure 8A An expanded view of a portion of the processor cores. Figure 8B This includes the L1 data cache 806A portion of L1 cache 804, and further details regarding vector unit 810 and vector register 814. Specifically, vector unit 810 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 828) that executes one or more integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports scrambling register inputs at memory inputs via scrambling unit 820, performing value conversions via value conversion units 822A-B, and performing copying via copy unit 824. Write mask register 826 allows vector writes of predicted results.

[0101] Processor with integrated memory controller and graphics

[0102] Figure 9 This is a block diagram of a processor 900 according to an embodiment of the present invention, which may have more than one core, an integrated memory controller, and an integrated graphics. Figure 9 The solid box in the diagram shows a processor 900 having a single core 902A, a system agent 910, and a collection of one or more bus controller units 916, while the dashed box shows an alternative processor 900 having multiple cores 902A-N, a collection of one or more integrated memory controller units 914 among the system agent units 910, and dedicated logic 908.

[0103] Therefore, different implementations of processor 900 may include: 1) a CPU having dedicated logic 908 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 902A-N that are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or combinations of said two cores); 2) a coprocessor having cores 902A-N that are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor having cores 902A-N that are a large number of general-purpose ordered cores. Thus, processor 900 may be a general-purpose processor, coprocessor, or dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput multi-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor may be implemented on one or more chips. Using any processing technology (such as, for example, BiCMOS, CMOS, or NMOS), processor 900 may be implemented on one or more substrates and / or portions thereof.

[0104] The memory hierarchy includes one or more levels of in-core cache memory, a set or one or more shared cache memory cells 906, and external memory (not shown) coupled to a set of integrated memory controller units 914. The set of shared cache memory cells 906 may include one or more intermediate-level cache memories, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache memory, Last-Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 912 interconnect integrated graphics logic 908, the set of shared cache memory cells 906, and system proxy units 910 / one or more integrated memory controller units 914, alternative embodiments may use any number of known techniques for interconnecting such units. In one embodiment, consistency between one or more cache memory cells 906 and core 902-AN is maintained.

[0105] In some embodiments, one or more cores of core 902A-N have multi-threading capabilities. System agent 910 includes those components that coordinate and operate core 902A-N. System agent unit 910 may include, for example, a power control unit (PCU) and a display unit. PCU may be or include the logic and components required for regulating the power state of integrated graphics logic 908 and core 902A-N. The display unit is used to drive one or more externally connected displays.

[0106] The 902A-N core can be homogeneous or heterogeneous in terms of its architecture instruction set; that is, two or more cores of the 902A-N core can be capable of executing the same instruction set, while other cores can be capable of executing different instruction sets or only a subset of those instruction sets.

[0107] Exemplary computer architecture

[0108] Figure 10-13 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the fields of laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, systems or electronic devices capable of incorporating a wide variety of processors and / or other execution logic as disclosed herein are generally suitable.

[0109] Now for reference Figure 10 The diagram illustrates a system 1000 according to an embodiment of the present invention. System 1000 may include one or more processors 1010, 1015 coupled to a controller hub 1020. In one embodiment, the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an input / output hub (IOH) 1050 (which may be on a separate chip); the GMCH 1090 includes a memory 1040 and a coprocessor 1045 to which the memory and graphics controller are coupled; the IOH 1050 couples an input / output (I / O) device 1060 to the GMCH 1090. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with the memory 1040 and the coprocessor 1045 directly coupled to the processor 1010 and the controller hub 1020 on a single chip having the IOH 1050.

[0110] The optional nature of the additional processor 1015 is in Figure 10 The term "disconnected line" is used to refer to the processor. Each processor 1010, 1015 may include one or more of the processing cores described herein, and may be a version of processor 900.

[0111] The memory 1040 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of the two memories. In at least one embodiment, the controller hub 1020 communicates with one or more processors 1010, 1015 via a multipoint bus such as a front side bus (FSB), a point-to-point interface such as a fast path interconnect (QPI), or a similar connection 1095.

[0112] In one embodiment, the coprocessor 1045 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 1020 may include an integrated graphics accelerator.

[0113] There are various differences in the spectrum of specifications for physical resources 1010 and 1015 regarding indicators such as architecture, microarchitecture, thermal, power consumption characteristics, etc.

[0114] In one embodiment, processor 1010 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 1010 recognizes these coprocessor instructions as the type to be executed by an attached coprocessor 1045. Therefore, processor 1010 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1045 on a coprocessor bus or other interconnect. One or more coprocessors 1045 receive and execute the received coprocessor instructions.

[0115] Now for reference Figure 11 The diagram shown is a block diagram of a first more specific exemplary system 1100 according to an embodiment of the present invention. Figure 11 The multiprocessor system 1100 shown is a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 coupled via point-to-point interconnect 1150. Each of processors 1170 and 1180 may be a version of processor 900. In one embodiment of the invention, processors 1170 and 1180 are processors 1010 and 1015, respectively, and coprocessor 1138 is coprocessor 1045. In another embodiment, processors 1170 and 1180 are processor 1010 and coprocessor 1045, respectively.

[0116] Processors 1170 and 1180 are shown, each including an integrated memory controller (IMC) unit 1172 and 1182, respectively. Processor 1170 also includes point-to-point (PP) interfaces 1176 and 1178 as part of its bus controller unit; similarly, the second processor 1180 includes PP interfaces 1186 and 1188. Using the PP interface circuits 1178 and 1188, processors 1170 and 1180 can exchange information via point-to-point (PP) interface 1150. Figure 11 As shown, IMC1172 and 1182 couple the processor to the corresponding memory (i.e., memory 1132 and memory 1134), which may be a portion of the main memory locally attached to the corresponding processor.

[0117] Using point-to-point interface circuits 1176, 1194, 1186, and 1198, processors 1170 and 1180 can each exchange information with chipset 1190 via separate PP interfaces 1152 and 1154. Chipset 1190 can optionally exchange information with coprocessor 1138 via high-performance interface 1139. In one embodiment, coprocessor 1138 is a dedicated processor, such as, for example, a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc. Shared cache memory (not shown) may be included in any processor or outside of both processors and connected to the processors via PP interconnect, such that if the processors are placed in low-power mode, the local cache memory information of any one or both processors can be stored in the shared cache memory.

[0118] Chipset 1190 may be coupled to first bus 1116 via interface 1196. In one embodiment, first bus 1116 may be a peripheral component interconnect (PCI) bus, or a bus such as PCI high-speed bus or another third-generation I / O interconnect bus, although the scope of the invention is not so limited.

[0119] like Figure 11 As shown, various I / O devices 1114 may be coupled to a first bus 1116 along with a bus bridge 1118, which in turn couples the first bus 1116 to a second bus 1120. In one embodiment, one or more additional processors 1115, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 1116. In one embodiment, the second bus 1120 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1120, including, for example, a keyboard and / or mouse 1122, a communication device 1127, and a storage unit 1128, such as a hard disk drive or other mass storage device, which may include instructions / code and data 1130 (in one embodiment). Additionally, audio I / O 1124 may be coupled to the second bus 1120. Note that other architectures are possible. For example, alternatives... Figure 11 The point-to-point architecture allows the system to implement multi-point bus or other similar architectures. (See reference below.) Figure 12 The diagram shown is a block diagram of a second more specific exemplary system 1200 according to an embodiment of the present invention. Figure 11 and 12 Similar elements in the figures have similar reference numerals, and Figure 11 Some aspects have been from Figure 12 The middle part is omitted to avoid ambiguity. Figure 12 Other aspects.

[0120] Figure 12 Processors 1170 and 1180 are shown to include integrated memory and I / O control logic (“CL”) 1172 and 1182, respectively. Therefore, CL 1172 and 1182 include an integrated memory controller unit and I / O control logic. Figure 12 It is shown that not only are memories 1132 and 1134 coupled to CLs 1172 and 1182, but I / O device 1214 is also coupled to control logic 1172 and 1182. Legacy I / O device 1215 is coupled to chipset 1190.

[0121] Now for reference Figure 13 The diagram shown is a block diagram of SoC1300 according to an embodiment of the present invention. Figure 9 Similar components in the diagram have similar reference numerals. Similarly, the dashed box is an optional feature on more advanced SoCs. Figure 13 In this embodiment, one or more interconnect units 1302 are coupled to: an application processor 1310, which includes a collection of one or more cores 202A-N and one or more shared cache memory units 906; a system agent unit 910; one or more bus controller units 916; one or more integrated memory controller units 914; a set or one or more coprocessors 1320, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1330; a direct memory access (DMA) unit 1332; and a display unit 1340 for coupling to one or more external displays. In one embodiment, the one or more coprocessors 1320 include a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, and the like.

[0122] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as program code or a computer program executable on a programmable system, said programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0123] Such as Figure 11The program code 1130 shown can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0124] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited to any specific programming language. In any case, the language can be a compiled or interpreted language.

[0125] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logics within a processor that, when read by a machine, cause the machine to make logic for performing the techniques described herein. Such representations (known as “IP cores”) may be stored on tangible, machine-readable media and supplied to various customers or manufacturing facilities for loading onto manufacturing machines that actually make the logic or processor.

[0126] Such machine-readable storage media may include, without limitation, a non-transitory, tangible arrangement of articles made or formed by a machine or apparatus, including storage media (such as hard disks, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and any other type of disk, magneto-optical disk), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions).

[0127] Therefore, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or design data, such as hardware description languages ​​(HDLs), that define the architectures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0128] Simulation (including binary translation, code transformation, etc.)

[0129] In some cases, an instruction translator can be used to translate instructions from a source instruction set into a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the core. Instruction translators are implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on the processor but not entirely off the processor.

[0130] Figure 14 This is a block diagram illustrating the use of a software instruction converter according to an embodiment of the invention to convert binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 14 The diagram illustrates that a program using a high-level language 1402, employing an x86 compiler 1404, can be compiled to generate x86 binary code 1406, which can be natively executed by a processor 1416 having at least one x86 instruction set core. A processor 1416 having at least one x86 instruction set core refers to any processor capable of performing substantially the same functionality as an Intel processor having at least one x86 instruction set core, by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software to be executed on an Intel processor having at least one x86 instruction set core, in order to achieve substantially the same results as on an Intel processor having at least one x86 instruction set core. The x86 compiler 1404 refers to a compiler operable to generate x86 binary code 1406 (e.g., object code), which can be executed on a processor 1416 having at least one x86 instruction set core, with or without additional linking processing. Similarly, Figure 14A program using a high-level language 1402 is illustrated using an alternative instruction set compiler 1408 to generate alternative instruction set binary code 1410, which can be natively executed by a processor 1414 that does not have at least one x86 instruction set core (e.g., a processor with a core executing the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 1412 is used to translate the x86 binary code 1406 into code that can be natively executed by the processor 1414 that does not have an x86 instruction set core. This translated code cannot be identical to the alternative instruction set binary code 1410, as an instruction converter capable of doing so would be difficult to make; however, the translated code will perform general operations and consist of instructions from the alternative instruction set. Therefore, the instruction converter 1412 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1406 through emulation, simulation, or any other process.

[0131] against Figure 1 , 4 Any of the components, features, and details described in 5 and 6 may also be optionally applied. Figure 2-3 Any of the components, features, and details described herein for any processor may be optionally applied to any of the methods described herein, which may optionally be performed by and / or by such processor in embodiments. Any of the processors described herein may optionally be included in any of the systems disclosed herein (e.g., Figure 10-13 In any of the embodiments, any of the instructions disclosed herein may optionally be executed by and / or by any of the processors disclosed herein, optionally have any of the microarchitectures shown herein in some embodiments, and optionally be included in any of the systems shown herein in some embodiments.

[0132] In this description and claims, the terms “coupled” and / or “connected”, along with their derivatives, have been used. These terms are not intended to be synonyms for each other. Rather, in embodiments, “connected” may be used to indicate that two or more elements are in direct physical and / or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical and / or electrical contact with each other. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. For example, an execution unit may be coupled to a register and / or decoding unit via one or more intermediate components. In the drawings, arrows are used to illustrate connections and couplings.

[0133] The term “and / or” may have been used. As used herein, the term “and / or” means one or the other or both (e.g., A and / or B means A or B or both A and B).

[0134] In the foregoing description, specific details have been set forth to provide a thorough understanding of the embodiments. However, other embodiments may be practiced without some of these specific details. The scope of the invention will not be determined by the specific examples provided above, but only by the claims below. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form and / or without detail to avoid obscuring the understanding of this description. Where appropriate, reference numerals or terminating portions of reference numerals have been repeated in the drawings to indicate corresponding or similar elements that may optionally have similar or identical characteristics, unless otherwise specified or clearly apparent.

[0135] Certain operations may be performed by hardware components or implemented in machine-executable or circuit-executable instructions that can be used to cause and / or induce a machine, circuit, or hardware component (e.g., a processor, a portion of a processor, circuitry, etc.) programmed with those instructions to perform the operation. Operations may also be performed optionally by a combination of hardware and software. The processor, machine, circuit, or hardware may include specific or concrete circuit modules or other logic (e.g., hardware potentially combined with firmware and / or software) operable to execute and / or process instructions and to store results in response to those instructions.

[0136] Some embodiments include an article of manufacture (e.g., a computer program product) that includes a machine-readable medium. The medium may include mechanisms for providing (e.g., storing) information in a machine-readable form. The machine-readable medium may provide (or have stored thereon) instructions or sequences of instructions that, if and / or when executed by a machine, are operable to cause the machine to perform and / or cause the machine to perform one or more operations, methods, or techniques disclosed herein.

[0137] In some embodiments, a machine-readable medium may include tangible and / or non-transitory machine-readable storage media. For example, a non-transitory machine-readable storage medium may include floppy disks, optical storage media, optical disks, optical data storage devices, CD-ROMs, magnetic disks, magneto-optical disks, read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), flash memory, phase-change memory, phase-change data storage materials, non-volatile memory, non-volatile data storage devices, non-transitory memory, non-transitory data storage devices, and so on. A non-transitory machine-readable storage medium is not composed of transient propagation signals. In some embodiments, the storage medium may include tangible media, which include solid substances or materials, such as, for example, semiconductor materials, phase-change materials, magnetic solid materials, solid data storage materials, etc. Alternatively, non-tangible transient computer-readable transmission media such as, for example, electrical, optical, acoustic, or other forms of propagation signals (such as carrier waves, infrared signals, and digital signals) may be optionally used.

[0138] Examples of suitable machines include, but are not limited to, general-purpose processors, special-purpose processors, digital logic circuits, integrated circuits, and so on. Other examples of suitable machines include computer systems or other electronic devices that include processors, digital logic circuits, or integrated circuits. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smartphones, cellular phones, servers, network devices (such as routers and switches), mobile internet devices (MIDs), media players, smart TVs, all-in-one desktops (nettops), set-top boxes, and video game controllers.

[0139] The use of terms such as "an embodiment," "an embodiment," "one or more embodiments," and "some embodiments" throughout this specification indicates that specific features may be included in the practice of the invention, but are not necessarily required. Similarly, in the description, various features are sometimes grouped together in a single embodiment, drawing, or description thereof for the purpose of simplifying this disclosure and aiding in understanding various aspects of the invention. However, this approach to disclosure is not to be construed as reflecting an intention to claim more features than are clearly stated in each claim. Rather, as reflected in the following claims, aspects of the invention lie in fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are thus clearly incorporated into that detailed description, wherein each claim stands independently as a separate embodiment of the invention.

[0140] Example Implementation

[0141] The following examples relate to other embodiments. Specific features in the examples may be used anywhere in one or more embodiments.

[0142] Example 1 is a processor including a widest set of data registers corresponding to a given logical processor. Each of the data registers in the widest set has a first width in bits. The processor also includes a decoding unit corresponding to the given logical processor to decode instructions specifying the data registers of the widest set, and to decode atomic store-to-memory instructions. The atomic store-to-memory instructions indicate data to have a second width in bits, wider than the first width in bits of each of the data registers in the widest set. The atomic store-to-memory instructions indicate memory address information associated with a memory location. The processor also has an execution unit coupled to the decoding unit. The execution unit, in response to the atomic store-to-memory instructions, atomically stores the indicated data into the memory location.

[0143] Example 2 includes the processor described in Example 1, wherein the execution unit includes a hierarchical buffer, and wherein the execution unit, in response to the instruction, sequentially stores multiple portions of indicated data to be collectively represented in the hierarchical buffer, and after the indicated data of the total amount has been stored in the hierarchical buffer, simultaneously stores the indicated data of the total amount from the hierarchical buffer.

[0144] Example 3 includes the processor described in Example 2, and further includes a write combination buffer, wherein the execution unit, in response to the atomic store to memory instruction, simultaneously stores the indicated amount of data from the hierarchical buffer to the write combination buffer.

[0145] Example 4 includes the processor described in Example 3, wherein the execution unit, in response to the atomic store to memory instruction, configures the write combination buffer for evicting after the plurality of portions of the indicated data have been stored in the write combination buffer.

[0146] Example 5 includes any of the processors described in Examples 3 to 4, wherein the execution unit, in response to the atomic store-to-memory instruction, configures the write combination buffer to disallow younger store operations from being merged with the write combination buffer after the plurality of portions of the indicated data have been stored into the write combination buffer.

[0147] Example 6 includes any of the processors described in Examples 1 to 5, wherein the execution unit, in response to the atomic store to memory instruction, signals one of the following when the atomic store to memory instruction terminates: a breakpoint configured on any byte from the first byte to the last byte of the memory location where the data is to be atomically stored, a segment constraint violation of any byte, a canonical address form violation of any byte, and a range-based violation of any byte.

[0148] Example 7 includes any of the processors described in Examples 1 to 6, wherein the execution unit, in response to the atomic store to memory instruction, makes the atomic storage of the data non-forwardable and forces the memory type associated with the atomically stored data to be unbuffered randomized write (USWC), regardless of the underlying memory type.

[0149] Example 8 includes any of the processors described in Examples 1 to 7, wherein the first and second widths are one of the following: (1) the first width is 128 bits and the second width is 256 bits; (2) the first width is 128 bits and the second width is 512 bits; (3) the first width is 128 bits and the second width is 1024 bits; (4) the first width is 256 bits and the second width is 512 bits; and (5) the first width is 256 bits and the second width is 1024 bits.

[0150] Example 9 includes any of the processors described in Examples 1 to 8, wherein the decoding unit is to decode the atomic store-to-memory instruction, the instruction indicating second memory address information associated with a second different memory location, in response to the atomic store-to-memory instruction to load the indicated data from the second different memory location.

[0151] Example 10 includes any of the processors described in Examples 1 to 8, wherein the decoding unit is to decode the atomic store-to-memory instruction, which instructs the initial use of the widest set of the data registers for storing the indicated data.

[0152] Example 11 includes any of the processors described in Examples 1 to 10, and also includes a decommissioning unit. Optionally, the decommissioning unit waits to decommission the atomic store-to-memory instruction until a response is received. Optionally, the response indicates whether the data to be atomically stored in the memory location has been fully observed and is now consistent.

[0153] Example 12 includes any of the processors described in Examples 1 to 11, wherein the second width is wider than the bit-scale width of the widest operation, which is one of the following: an arithmetic operation, a logical operation, and an arithmetic and logical operation that the given logic processor is capable of performing on one or more packed data operands.

[0154] Example 13 includes any of the processors described in Examples 1 to 12, wherein the second width is wider than the bit-scale width of the widest packed data operand, which is indicated by any of the following: any packed data addition instruction to be decoded by the decoding unit and any packed data multiplication instruction to be decoded by the decoding unit.

[0155] Example 14 is a method executed by a processor, comprising: receiving an atomic store-to-memory instruction at a given logical processor of the processor. The atomic store-to-memory instruction indicates data that is bit-wider than the widest data register that can be specified by an instruction set of the given logical processor, and the atomic store-to-memory instruction indicates memory address information associated with a memory location. The method further comprises, in response to the atomic store-to-memory instruction, atomically storing the indicated data into the memory location.

[0156] Example 15 includes the method of Example 14, wherein the atomic storage includes atomically storing indicated data having a width of at least 512 bits into the memory location, and wherein the width of the widest data register is no greater than 256 bits.

[0157] Example 16 includes the method described in any of Examples 14 to 15, wherein the atomic storage further includes, in response to the atomic store to memory instruction, sequentially storing multiple portions of the indicated data that collectively represent the total amount into a hierarchical buffer. Optionally, multiple portions of the indicated data and / or the total amount of the indicated data may be simultaneously stored from the hierarchical buffer to another storage location.

[0158] Example 17 includes the method of Example 16, wherein the simultaneous storage includes simultaneously storing the total indicated data from the hierarchical buffer to the write combination buffer, and wherein the atomic storage further includes, in response to the atomic store to memory instruction, configuring the write combination buffer to disallow younger storage operations from being merged with the write combination buffer after the plurality of portions of the indicated data have been stored to the write combination buffer. Optionally, the write combination buffer may be configured for eviction after the plurality of portions of the indicated data have been stored to the write combination buffer.

[0159] Example 18 includes the method described in any of Examples 14 to 17, wherein the indicated data is atomically stored in the memory location for assigning work to the accelerator device.

[0160] Example 19 includes the method described in any of Examples 14 to 18, and further includes detecting and signaling one of the following when the atomic store to memory instruction is submitted: a breakpoint, segment limit violation, and range-based violation at any byte in the memory location when the data is atomically stored.

[0161] Example 20 includes the method of any one of Examples 14 to 19, wherein the receiving includes receiving the atomic store to memory instruction indicating memory address information associated with a second memory location, and loading the indicated data from the second memory location in response to the atomic store to memory instruction.

[0162] Example 21 is a computer system comprising: an interconnect; and a processor coupled to the interconnect. The processor has a given core having a widest set of data registers. Each of the data registers in the widest set has a first width in bits. The given core receives an atomic store-to-memory instruction to indicate data having a second width in bits, the second width being wider than the first width of each of the data registers in the widest set. The atomic store-to-memory instruction indicates memory address information associated with a memory location, and the processor, in response to the atomic store-to-memory instruction, atomically stores the indicated data into the memory location. The computer system also includes dynamic random access memory (DRAM) coupled to the interconnect. A set of DRAM storage instructions is used to submit work to another device using different instances of the atomic store-to-memory instructions.

[0163] Example 22 includes the computer system described in Example 21, wherein the processor includes a hierarchical buffer and a write combination buffer, and wherein the processor, in response to the atomic store to memory instruction, sequentially stores multiple portions of indicated data into the hierarchical buffer. Optionally, the multiple portions of indicated data are also stored from the hierarchical buffer into the write combination buffer.

[0164] Example 23 includes any of the computer systems described in Examples 21 to 22, wherein the first width is no greater than 256 bits and the second width is at least 512 bits.

[0165] Example 24 is an article of manufacture including a non-transitory machine-readable storage medium. The non-transitory machine-readable storage medium stores atomic store-to-memory instructions. If executed by a processor, the atomic store-to-memory instructions cause the processor to perform an operation including receiving the atomic store-to-memory instructions at a given logical processor. The atomic store-to-memory instructions indicate data to have a bit width wider than the bit width of the widest arithmetic operation that the given logical processor can perform, and the atomic store-to-memory instructions indicate memory address information associated with a memory address. The operation also includes atomically storing the data into the memory location.

[0166] Example 25 includes the article of Example 24, wherein the width of the data is at least 512 bits, and wherein the width of the widest arithmetic operation is no greater than 256 bits.

[0167] Example 26 includes any of the processors described in Examples 1 to 13, further comprising an optional branch prediction unit for predicting branches, and an optional instruction prefetch unit coupled to the branch prediction unit for prefetching instructions (including atomic store-to-memory instructions). The processor may also optionally include an optional Level 1 (L1) instruction cache coupled to the instruction prefetch unit for storing instructions; an optional L1 data cache for storing data; and an optional Level 2 (L2) cache for storing both data and instructions. The processor may also optionally include an instruction fetch unit coupled to the decoding unit, the L1 instruction cache, and the L2 cache, for fetching the atomic store-to-memory instructions from one of the L1 instruction cache and the L2 cache in some cases, and providing the atomic store-to-memory instructions to the decoding unit. The processor may also optionally include a register renaming unit for renaming registers, an optional scheduler for scheduling one or more operations decoded from the atomic store-to-memory instruction for execution, and an optional submission unit for submitting the execution results of the atomic store-to-memory instruction.

[0168] Example 27 includes a system-on-a-chip comprising at least one interconnect, a processor of any one of Examples 1 to 13 coupled to the at least one interconnect, an optional graphics processing unit (GPU) coupled to the at least one interconnect, an optional digital signal processor (DSP) coupled to the at least one interconnect, an optional display controller coupled to the at least one interconnect, an optional memory controller coupled to the at least one interconnect, an optional wireless modem coupled to the at least one interconnect, an optional image signal processor coupled to the at least one interconnect, an optional Universal Serial Bus (USB) 3.0 compatible controller coupled to the at least one interconnect, an optional Bluetooth 4.1 compatible controller coupled to the at least one interconnect, and an optional wireless transceiver controller coupled to the at least one interconnect.

[0169] Example 28 is a processor or other device that operates to perform the method described in any of Examples 14 through 20.

[0170] Example 29 is a processor or other device that includes components for performing the methods of any one of Examples 14 to 20.

[0171] Example 30 is a processor or other device that includes modules and / or units and / or logic and / or circuit modules and / or components that operate to perform any of the methods described in Examples 14 to 20.

[0172] Example 31 is an optional non-transitory and / or tangible machine-readable medium that optionally stores or otherwise provides instructions including a first instruction that, if and / or when executed by a processor, computer system, electronic device or other machine, causes the machine to perform the method described in any of Examples 14 to 20.

[0173] Example 32 is a processor or other device that is essentially as described herein.

[0174] Example 33 is a processor or other device that operates to perform essentially any of the methods described herein.

[0175] Example 34 is a processor or other device that operates to execute any atomic store-to-memory instruction to atomically store a wider range of data than is natively supported by the processor, which is substantially as described herein.

[0176] Example 35 is a computer system or other electronic device that includes a processor having a decoding unit that operates to decode instructions of a first instruction set. The processor also has one or more execution units. The electronic device further includes a storage device coupled to the processor. The storage device operates to store a first instruction, which may be substantially any instruction as disclosed herein, and which is to have a second, different instruction set. The storage device also operates to store instructions for translating the first instruction into one or more instructions of the first instruction set. When executed by the processor, the one or more instructions of the first instruction set operate to cause the processor to atomically store a wider range of data than the processor natively supports into memory.

[0177] Example 36 is a processor including a decoding unit corresponding to a given logic processor. The decoding unit is used to decode an atomic store-to-memory instruction. The atomic store-to-memory instruction is used to indicate data, and the atomic store-to-memory instruction is used to indicate memory address information associated with a memory location. The processor also includes an execution unit coupled to the decoding unit. The execution unit, in response to the atomic store-to-memory instruction, atomically stores the indicated data into the memory location. The bit-width of the data to be atomically stored in response to the atomic store-to-memory instruction is wider than the bit-width of data atomically loaded by any instruction that the decoder can decode.

Claims

1. A processor, comprising: Multiple high-speed cache memories; A decoding circuit module for decoding instructions, the instructions being used to provide information to address a source memory location and to provide information to address a destination memory location; An execution circuit module coupled to the decoding circuit module is used to perform operations corresponding to the instructions, including atomically storing first data, which includes data loaded from the source memory location to the destination memory location; and A status register coupled to the execution circuit module, wherein status information is stored in a bit of the status register, the status information indicating whether the first data has been stored in the destination memory location. The first data bypasses the plurality of cache memories, regardless of the memory type of the destination memory location. The successful completion of the atomic storage requires that the destination memory location be 64-byte aligned, and The execution circuit module is used to prevent stored data younger than the instruction from being merged with the first data.

2. The processor of claim 1, wherein the status information indicates whether the first data has been accepted by the device.

3. The processor of claim 1, wherein the state information is stored based on the receipt of a response related to the atomic storage of the first data to the destination memory location.

4. The processor of claim 1, wherein the destination memory location corresponds to a work submission queue for the device.

5. The processor of claim 4, wherein the work submission queue is a shared work submission queue.

6. The processor of claim 4, wherein the work submission queue is a memory-mapped input / output (MMIO) shared work queue register.

7. The processor of claim 4, wherein the first data is used to assign work to the device.

8. The processor of claim 4, wherein the device is a memory controller.

9. The processor of claim 1, wherein the instruction is a job submission instruction for submitting work to the device.

10. The processor of claim 1, wherein the destination memory location is within the Memory Mapped Input / Output (MMIO) range.

11. The processor of claim 1, wherein the instruction for providing the information to address the destination memory location is used to specify a general-purpose register having address information to be combined with address information from a segment register.

12. The processor of claim 1, wherein the first data is 512 bits.

13. The processor of claim 1, wherein the first data is 256 bits.

14. A processor, comprising: Multiple high-speed cache memories; A decoding circuit module for decoding instructions that submit work to the device, the instructions being used to provide information to address a source memory location and to provide information to address a position in the memory-mapped input / output (MMIO) work submission queue for the device; and An execution circuit module coupled to the decoding circuit module, the execution circuit module being configured to perform operations corresponding to the instructions, including atomically storing first data, which includes data loaded from the source memory location to a location in the MMIO work submission queue for the device, for allocating work to the device. The first data bypasses the plurality of cache memories, regardless of the memory type at the location in the MMIO work submission queue. The successful completion of the atomic storage requires that the position in the MMIO work submission queue be 64-byte aligned, and The execution circuit module is used to prevent stored data younger than the instruction from being merged with the first data.

15. The processor of claim 14, wherein the MMIO work submission queue is a shared MMIO work submission queue.

16. The processor of claim 14, wherein the device is an accelerator device.

17. The processor of claim 14, further comprising a status register coupled to the execution circuit module, wherein status information is stored in a bit of the status register, the status information indicating whether the first data has been stored at the position in the MMIO work submission queue.

18. The processor of claim 17, wherein the status information indicates whether the first data has been accepted by the device.

19. The processor of claim 17, wherein the means is configured to store the status information in the bit of the status register.

20. The processor of claim 14, wherein the instruction for providing the information to address the location in the MMIO work submission queue is used to specify a general-purpose register having address information to be combined with address information from a segment register.

21. The processor of claim 14, wherein the first data is 512 bits.

22. The processor of claim 14, wherein the first data is 256 bits.

23. The processor of claim 14, wherein the device is a memory controller.

24. An apparatus comprising: Accelerator device; and A processor coupled to the accelerator device, the processor comprising: Multiple high-speed cache memories; A decoding circuit module for decoding instructions, which provide information to address a source memory location and to address a destination memory location; An execution circuit module coupled to the decoding circuit module, the execution circuit module being used to perform operations corresponding to the instructions, including atomically storing first data, which includes data loaded from the source memory location to the destination memory location; and A status register coupled to the execution circuit module, wherein status information is stored in a bit of the status register, the status information indicating whether the first data has been stored in the destination memory location. The first data bypasses the plurality of cache memories regardless of the memory type of the destination memory location, wherein successful completion of the atomic storage requires the destination memory location to be 64-byte aligned, and wherein the execution circuit module is used to prevent younger stored data than the instruction from being merged with the first data.

25. The device of claim 24, wherein the status information indicates whether the first data has been accepted by the accelerator device.

26. The device of claim 24, wherein the state information is stored based on the receipt of a response related to the atomic storage of the first data to the destination memory location.

27. The device of claim 24, wherein the destination memory location corresponds to a memory-mapped input / output (MMIO) shared job submission queue for the accelerator device, and wherein the first data is used to assign jobs to the accelerator device.

28. A processor, comprising: Multiple high-speed cache memories; A fetch circuit module for obtaining instructions to store atoms into memory; and A decoding circuit module coupled to the acquisition circuit module, the decoding circuit module being used to decode the atomic store-to-memory instruction, the atomic store-to-memory instruction having a field for specifying a 64-bit register, wherein the 64-bit register is the first of eight sequential 64-bit registers used to collectively store a 512-bit data; and An execution circuit module coupled to the decoding circuit module, the execution circuit module being used to perform operations corresponding to the atomic storage to memory instruction, including for... By bypassing the multiple high-speed cache memories, the 512-bit data is atomically stored in a memory location; and The state information associated with the atomic storage of the 512-bit data is stored in a memory location in the processor's register. The successful completion of the atomic storage requires that the memory location be 64-byte aligned, that the memory type of the memory location be a non-cacheable memory type, and that the execution circuit module is used to atomically store the 512-bit data into the memory location via a non-cacheable storage operation.

29. The processor of claim 28, wherein the atomic store to memory instruction is an instruction for submitting work to the device, and wherein the storage of the 512-bit data at the memory location indicated by the status information has been stored in the work queue of the device.

30. The processor of claim 28, wherein the state information is based on a received response related to the atomic storage of the 512-bit data to the memory location.

31. The processor of claim 28, wherein, in order to execute the decoded atomic store-to-memory instruction, the execution circuit module is configured to: The different 64-bit portions of the 512-bit data are sequentially stored from the eight sequential 64-bit registers to the storage location; and Simultaneously, the 512-bit data is stored from the storage location to the memory location.

32. A system comprising: System memory; and A processor coupled to the system memory, the processor comprising: Multiple high-speed cache memories; The acquisition circuit module is used to acquire instructions for storing atoms into memory; and A decoding circuit module coupled to the acquisition circuit module, the decoding circuit module being used to decode the atomic store-to-memory instruction, the atomic store-to-memory instruction having a field for specifying a 64-bit register, wherein the 64-bit register is the first of eight sequential 64-bit registers used to collectively store a 512-bit data; and An execution circuit module coupled to the decoding circuit module, the execution circuit module being used to perform operations corresponding to the atomic storage to memory instruction, including for... Bypassing the multiple cache memories, the 512 bits of data are atomically stored in the memory location; and The state information associated with the atomic storage of the 512-bit data is stored in a memory location in the processor's register. The successful completion of the atomic storage requires that the memory location be 64-byte aligned, that the memory type of the memory location be a non-cacheable memory type, and that the execution circuit module is used to atomically store the 512-bit data into the memory location via a non-cacheable storage operation.

33. The system of claim 32, wherein the atomic storage to memory instruction is an instruction for submitting work to the device, and wherein the storage of the 512-bit data at the memory location indicated by the status information has been stored in the work queue of the device.

34. A method executed by a processor having multiple cache memories, the method comprising: The decoding circuit module decodes the instructions, which are used to provide information to address the source memory location and to provide information to address the destination memory location. An execution circuit module coupled to the decoding circuit module performs an operation corresponding to the instruction, including atomically storing first data, which includes data loaded from the source memory location to the destination memory location; and Status information is stored in a bit of a status register coupled to the execution circuit module, indicating whether the first data has been stored in the destination memory location. The first data bypasses the plurality of cache memories, regardless of the memory type of the destination memory location. The successful completion of the atomic storage requires that the destination memory location be 64-byte aligned, and The execution circuit module is used to prevent stored data younger than the instruction from being merged with the first data.

35. The method of claim 34, wherein the status information indicates whether the first data has been accepted by the device.

36. The method of claim 34, wherein storing the state information is based on receiving a response related to the atomic storage of the first data to the destination memory location.

37. The method of claim 34, wherein the destination memory location corresponds to a work submission queue for the device.

38. The method of claim 37, wherein the work submission queue is a shared work submission queue.

39. The method of claim 37, wherein the work submission queue is a memory-mapped input / output (MMIO) shared work queue register.

40. The method of claim 37, further comprising using the first data to assign work to the apparatus.

41. The method of claim 37, wherein the device is a storage controller.

42. The method of claim 34, wherein the instruction is a work submission instruction for submitting work to the device.

43. The method of claim 34, wherein the destination memory location is within the Memory Mapped Input / Output (MMIO) range.

44. The method of claim 34, wherein the instruction for providing the information to address the destination memory location is used to specify a general-purpose register having address information to be combined with address information from a segment register.

45. The method of claim 34, wherein the first data is 512 bits.

46. ​​The method of claim 34, wherein the first data is 256 bits.

47. A machine-readable medium having stored thereon computer-executable instructions, which, when executed by a processor, cause the processor to perform the method according to any one of claims 34 to 46.

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