Simulation verification method and device of algorithm chip, computer device and medium

Abstract

This invention discloses a simulation verification method, apparatus, computer device, and medium for an algorithm chip. The method includes: acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of a hardware description language programming environment; inputting the interface input data into a reference model and acquiring simulation result data obtained by executing the general programming language logic code in the reference model; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. This invention solves the problem of verifying complex algorithm protocol models, improves the accuracy and development efficiency of algorithm protocol models, and further enhances the efficiency of debugging and locating errors.

Description

Technical Field

[0001] The embodiments of the present invention relate to computer data processing technology, and more particularly to a simulation verification method, apparatus, computer equipment and medium for an algorithm chip. Background Technology

[0002] Algorithm chip modules typically possess numerous and complex computing units to implement their various algorithmic functions. Verification of algorithm chip modules, particularly those involving communication, image, and audio algorithms, primarily focuses on: understanding the algorithmic logic and functions implemented by the module; implementing and constraining the correct random inputs to the algorithm module; determining the correct output results for different random inputs by constructing a reference model of the algorithm; and completing and traversing various input combinations to quickly achieve relatively complete functional coverage convergence.

[0003] Currently, existing methods for implementing reference models for algorithm chip modules face the following problems and risks: First, it is difficult to construct reference models for related algorithms using SystemVerilog, and it is also difficult to guarantee the correctness of the functions of complex algorithm chip modules, resulting in a long development cycle; Second, for complex algorithm chip modules, since the verification environment, reference model, and register conversion circuit are all implemented manually, the efficiency of locating errors is usually low and a long debugging time is required once a problem occurs. Summary of the Invention

[0004] This invention provides a simulation verification method, apparatus, computer equipment, and medium for algorithm chips, which solves the problem of verifying complex algorithm protocol models, improves the accuracy of algorithm protocol models, enhances development efficiency, and increases the efficiency of debugging and locating errors.

[0005] In a first aspect, embodiments of the present invention provide a simulation verification method for an algorithm chip, comprising:

[0006] Acquire simulated interface input data for the chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment;

[0007] The interface input data is input into the reference model, and the simulation result data obtained by the reference model through executing the general programming language logic code is obtained;

[0008] Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, the algorithm chip under test is subjected to the first type of functional verification.

[0009] Secondly, embodiments of the present invention also provide a simulation verification device for an algorithm chip, the simulation verification device for the algorithm chip comprising:

[0010] The interface input data acquisition module is used to acquire interface input data simulated for the algorithm chip under test, and the interface input data conforms to the requirements of the hardware description language programming environment.

[0011] The simulation result data acquisition module is used to input the interface input data into the reference model and acquire the simulation result data obtained by the reference model through executing the general programming language logic code;

[0012] The first type of functional verification module is used to perform first type of functional verification on the algorithm chip under test based on the actual result data calculated by the chip under test for the interface input data and the simulation result data.

[0013] Thirdly, embodiments of the present invention also provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the simulation verification method for the algorithm chip as described in any embodiment of the present invention.

[0014] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, on which a computer program is stored, wherein when the program is executed by a processor, it implements the simulation verification method of the algorithm chip as described in any embodiment of the present invention.

[0015] The technical solution provided by this invention involves acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; inputting the interface input data into the reference model and acquiring simulation result data obtained by the reference model through executing the general programming language logic code; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. This solves the problem of verifying complex algorithm protocol models, improves the accuracy and development efficiency of algorithm protocol models, and further enhances the efficiency of debugging and locating errors. Attached Figure Description

[0016] Figure 1a A flowchart illustrating a simulation verification method for an algorithm chip provided in Embodiment 1 of the present invention;

[0017] Figure 1b This is a schematic diagram of the calculation and simulation of the algorithm chip under test in the simulation verification method of the algorithm chip provided in Embodiment 1 of the present invention;

[0018] Figure 2 A flowchart illustrating a simulation verification method for an algorithm chip provided in Embodiment 2 of the present invention;

[0019] Figure 3 A flowchart illustrating a simulation verification method for an algorithm chip provided in Embodiment 3 of the present invention;

[0020] Figure 4 A flowchart illustrating a simulation verification method for an algorithm chip provided in Embodiment 4 of the present invention;

[0021] Figure 5 This is a schematic diagram of the structure of a simulation verification method for an algorithm chip provided in Embodiment 5 of the present invention;

[0022] Figure 6 This is a schematic diagram of the structure of a computer device provided in Embodiment Six of the present invention. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0024] Example 1

[0025] Figure 1a This is a flowchart illustrating a simulation verification method for an algorithm chip according to Embodiment 1 of the present invention. This embodiment is applicable to the verification of complex algorithm protocol models. The method of this embodiment can be executed by an algorithm chip simulation verification device, which can be implemented by software and / or hardware. This device can be configured to execute within a reference model in a hardware description language programming environment, and the reference model contains built-in general-purpose programming language logic code.

[0026] Accordingly, the method specifically includes the following steps:

[0027] S110. Obtain the interface input data simulated for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment.

[0028] The chip under test (DUT) can be a chip containing an integrated algorithm that needs to be measured. Integrating complex algorithms can improve the chip's computing power and processing efficiency. The interface input data can be data input through the algorithm chip's interface. This input data is processed by the algorithm chip to produce corresponding output data, i.e., the actual result data. A hardware description language (HDL) is a character-based computer language used to describe the operating specifications of hardware and represent the behavior and spatial structure of electronic circuits over time. Compared to software programming languages, HDL syntax and meaning describe time and concurrency, which are fundamental and entirely different attributes of hardware. The programming environment can be a comprehensive software tool that integrates all the functions required for the entire program design process, providing programmers with complete services.

[0029] For example, such as Figure 1b The diagram illustrates the computation and simulation of the algorithm under test (DUT) chip. The sequence generator in the input processing module generates data packets, which serve as the interface input data. The driver program drives the data packets generated by the sequence generator into the DUT chip. The monitor monitors the data packets input to the DUT chip and passes them to a reference model, which also serves as its input. The reference model simulates and generates reference output data after receiving the same input data as the DUT chip. The monitor in the output processing module monitors the output of the DUT chip and passes it to a scoring board. The scoring board compares the outputs of the DUT chip and the reference model. Specifically, the interface input data simulated for the DUT chip is acquired. The monitor monitors the data packets input to the DUT chip and passes them to the reference model, which also serves as its input. The interface input data conforms to the requirements of the hardware description language programming environment.

[0030] In this embodiment, the interface input data is input to the algorithm chip under test for operation. The interface input data is processed by acquiring the interface input data, and the interface input data conforms to the requirements of the hardware description language programming environment.

[0031] S120. Input the interface input data into the reference model and obtain the simulation result data obtained by the reference model through executing the general programming language logic code.

[0032] The reference model can be a model used to verify the functions executed in the algorithm chip using a programming language. The general-purpose programming language logic code can be different languages ​​used to implement different functions; the content of the code varies for each computer language and can include logic code composed of languages ​​such as C, C++, MATLAB, and Java. The simulation result data can be the simulation results obtained after the interface input data is run through the reference model.

[0033] For example, such as Figure 1b The diagram illustrates that the obtained interface input data is used as the input data for the reference model. Furthermore, by simulating the generation of reference output data after inputting the same data as the chip under test, simulation result data can be obtained.

[0034] In this implementation, by acquiring the interface input data of the algorithm chip under test and inputting the acquired interface input data into the reference model, simulation data results can be obtained.

[0035] S130. Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, perform the first type of functional verification on the algorithm chip under test.

[0036] The first type of functional verification can be performed by processing the interface input data through the chip under test to obtain actual result data; or by running the interface input data through the reference module to obtain simulation result data; and by comparing the actual result data and the simulation result data to perform functional verification.

[0037] For example, such as Figure 1b The diagram illustrates how, when input data is fed into the chip under test (DUT), the actual result data is obtained after processing. The monitor in the output processing module monitors the output of the DUT and transmits it to the scoring board. The scoring board compiles statistics comparing the outputs of the DUT and the reference model.

[0038] In this embodiment, actual result data can be obtained by processing the interface input data through the algorithm chip under test; further, the interface input data is run through the reference module to obtain simulation result data; accordingly, the actual result data and the simulation result data are compared to perform the first type of functional verification.

[0039] The technical solution provided by this invention involves acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; inputting the interface input data into the reference model and acquiring simulation result data obtained by the reference model through executing the general programming language logic code; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. This solves the problem of verifying complex algorithm protocol models, improves the accuracy and development efficiency of algorithm protocol models, and further enhances the efficiency of debugging and locating errors.

[0040] Optionally, after inputting the interface input data into the reference model, the method further includes: obtaining a plurality of simulation intermediate result data obtained by the reference model by executing the general programming language logic code; and performing a second type of functional verification on the algorithm chip to be tested according to a plurality of actual intermediate result data calculated by the algorithm chip to be tested for the interface input data and each of the simulation intermediate result data.

[0041] Among them, the simulation intermediate result data can be obtained by setting commands during the execution of the reference model using the programming language of the general programming language logic code. The actual intermediate result data can be the result data in the middle of the calculation process when the interface input data is input into the algorithm chip to be tested.

[0042] In this embodiment, the interface input data is input into the reference model, and the simulation intermediate result data is obtained in real time, and the interface input data is input into the algorithm chip to be tested, and the actual intermediate result data is obtained in real time. The simulation intermediate result data and the actual intermediate result data are compared and displayed on the scoreboard for comparison.

[0043] The advantage of this setting is that: by comparing the simulation intermediate result data and the actual intermediate result data in real time, it can be reflected on the scoreboard in real time. This can reduce the errors in the intermediate verification process. Once an error occurs during the verification process, the subsequent verification needs to be stopped and the previous verification process needs to be checked. This reduces the waste of time and can quickly and clearly locate the error link in the verification process of the reference model.

[0044] Embodiment 2

[0045] Figure 2 It is a flowchart of a simulation verification method for an algorithm chip provided in Embodiment 2 of the present invention. This embodiment is optimized based on the above embodiments. In this embodiment, the reference model has an interface conversion function programmed by C language or C++ language logic code and a core function encapsulated inside the interface conversion function, where the core function is adapted to the calculation logic in the chip to be tested.

[0046] Correspondingly, the method specifically includes the following steps:

[0047] S210. Obtain interface input data simulated for the algorithm chip to be tested, where the interface input data meets the requirements of the hardware description language programming environment.

[0048] S220. Input the interface input data into the interface conversion function in the reference model, and convert the interface input data into general input data through the interface conversion function, where the general input data meets the requirements of the C language or C++ language environment.

[0049] The interface conversion function transforms the obtained interface input data into general input data, which can then be further input into the reference model for data processing. This general input data can conform to the requirements of either the C or C++ language environment.

[0050] Specifically, the interface conversion function here uses the C language's `wrapper()` function. The number of interface parameters for the `wrapper()` function, the type of each parameter, and whether the direction is input or output are all determined by the functionality of the reference model and the requirements of the verification environment. Furthermore, configuration parameters and interface input data are designed as inputs to the `wrapper()` function, while general input data is used as its output.

[0051] S230. The general input data is transmitted to the core function through the interface conversion function, and the calculation result data matching the general input data is calculated by the core function.

[0052] The core function can be the `core()` function in the C programming language. The calculated result data can be the result data obtained by the `core()` function in the C programming language that matches the general input data.

[0053] Specifically, the `wrapper()` function calls the `core()` function inside the interface conversion function. The `wrapper()` function transfers the general input data to the `core()` function, which then calculates the result data that matches the general input data. The conversion of general input data from the `wrapper()` function to the `core()` function should be as simple as possible; this can be achieved by grouping the corresponding parameters and wrapping each group of data together as much as possible.

[0054] S240. The calculation result data is converted into simulation result data that meets the requirements of the hardware description language programming environment and output through the reference model, or the calculation result data is directly output as simulation result data to a file.

[0055] In this embodiment, the calculation result data can be converted into simulation result data that conforms to the requirements of the hardware description language programming environment and output through the reference model; alternatively, the calculation result data can be directly output as simulation result data to a file. For example, since the C language in the reference model typically does not occupy simulation time, the corresponding C language is executed first. Therefore, in addition to converting the calculation result data into simulation result data that conforms to the requirements of the hardware description language programming environment and outputting through the reference model for interaction, data can also be transferred using a file.

[0056] Furthermore, the io_printf() function in C can be used to display the printed information on the screen and write it to a storable file for easy debugging.

[0057] The advantage of this setup is that the calculation results are directly output to a file as simulation results. By using file transfer, large amounts of calculation results can be input and output in C language, thereby enabling data interaction with the verification environment.

[0058] S250. Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, perform the first type of functional verification on the algorithm chip under test.

[0059] Optionally, converting the calculation result data into simulation result data that conforms to the requirements of the hardware description language programming environment and outputting it through the reference model includes: transmitting the calculation result data to the interface conversion function through the core function; and converting the calculation result data into simulation result data that conforms to the requirements of the hardware description language programming environment and outputting it through the reference model through the interface conversion function.

[0060] In this implementation, the core function `core()` transmits the computational result data to the interface conversion function `wrapper()`. Furthermore, the `wrapper()` function converts the received computational result data into simulation result data that conforms to the requirements of the hardware description language programming environment. Accordingly, the data can be output using a reference model.

[0061] The technical solution provided by this invention involves acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of a hardware description language programming environment; inputting the interface input data into the interface conversion function in the reference model, and converting the interface input data into general input data through the interface conversion function, wherein the general input data conforms to the requirements of a C or C++ language environment; transmitting the general input data to the core function through the interface conversion function, and calculating the calculation result data matching the general input data through the core function; converting the calculation result data into simulation result data conforming to the requirements of a hardware description language programming environment and outputting it through the reference model, or directly outputting the calculation result data as simulation result data to a file; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. Furthermore, by having the interface conversion function, programmed using C or C++ language logic code, and the core function encapsulated within the interface conversion function in the reference model, the accuracy, development efficiency, and verification efficiency of the reference model verification can be improved, and data transfer can be further reduced.

[0062] Example 3

[0063] Figure 3 This is a flowchart of a simulation verification method for an algorithm chip provided in Embodiment 3 of the present invention. This embodiment is an optimization based on the above embodiments. In this embodiment, the reference model has a built-in Matlab calculation model obtained by programming Matlab language logic code, wherein the Matlab calculation model is adapted to the calculation logic in the chip under test.

[0064] Accordingly, the method specifically includes the following steps:

[0065] S310. Obtain the interface input data simulated for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment.

[0066] S320. The Matlab computing model is triggered to be executed through the hardware description language programming logic built into the reference model, and the interface input data is input into the Matlab computing model.

[0067] Among them, the Matlab computation model can be a model that performs calculations using the Matlab language.

[0068] For example, the hardware description language uses SystemVerilog. In SystemVerilog, the Matlab computation model is started via the system task `$system(cmd)`, and the interface input data is input into the Matlab computation model. Correspondingly, `$system(“Matlab-rfunc”)` can be used directly in the reference model to further execute the contents of the Matlab function `func.m`.

[0069] Furthermore, since the above commands will launch the Matlab graphical interface, they will consume significant verification server resources and require manual interaction. To address this, the "Matlab-nosplash-nodesktop" parameter can be added to the environment variables for background execution without a graphical interface. Alternatively, abbreviations can be used in the shell configuration file: abbreviations via the alias command, such as "alias Matlab-nosplash-nodesktop-r"; or abbreviations via setenv, such as "setenv Matlab-nosplash-nodesktop-r". When calling the program in the reference model, use `$system("$mrun func")` to execute it in the background.

[0070] S330. Simulation result data matching the interface input data is calculated using the Matlab calculation model.

[0071] S340. The simulation result data is output via the reference model through the Matlab calculation model, or the simulation result data is output to a file.

[0072] S350. Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, perform the first type of functional verification on the algorithm chip under test.

[0073] Optionally, the hardware description language programming logic includes instructions for executing without a graphical interface; triggering the execution of the Matlab calculation model includes: triggering the background execution of the Matlab calculation model so that the Matlab calculation model can obtain the simulation result data without a graphical interface.

[0074] The option to execute commands with or without a graphical interface can be used to call a Matlab computational model, allowing the display of the Matlab computational model's front-end interface during the call process.

[0075] The advantage of this setup is that by executing non-graphical interface instructions through hardware description language programming logic, the consumption of a large amount of verification server resources and the cost of manual interaction can be further reduced, making the verification process more rational and further improving the efficiency of verification.

[0076] The technical solution provided by this invention involves acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; triggering the execution of the Matlab calculation model through the hardware description language programming logic built into the reference model, and inputting the interface input data into the Matlab calculation model; calculating simulation result data matching the interface input data through the Matlab calculation model; outputting the simulation result data through the reference model via the Matlab calculation model, or outputting the simulation result data to a file; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. Furthermore, by having a Matlab calculation model built into the reference model, which is programmed using Matlab language logic code, the accuracy, development efficiency, and verification efficiency of the reference model verification can be improved, and the data transmission, the consumption of large amounts of verification server resources, and the cost of manual interaction can be further reduced.

[0077] Example 4

[0078] Figure 4 This is a flowchart of a simulation verification method for an algorithm chip provided in Embodiment 4 of the present invention. This embodiment is an optimization based on the above embodiments. In this embodiment, the reference model has one or more built-in Matlab general-purpose calculation functions, and each Matlab general-purpose calculation function is executed by calling the hardware description language programming logic in the reference model.

[0079] Accordingly, the method specifically includes the following steps:

[0080] S410. Obtain the interface input data simulated for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment.

[0081] S420. Input the interface input data into the reference model and trigger the execution of the general programming language logic code in the reference model.

[0082] S430. During the execution of the general programming language logic code, if a target Matlab general calculation function is detected, the C language runtime environment in the general programming language programming environment is triggered to start.

[0083] The target Matlab general computation function can be a general computation function that is executed using the Matlab language.

[0084] S440. In the C language runtime environment, trigger the opening of the Matlab runtime environment, and in the Matlab runtime environment, trigger the call of the target Matlab general calculation function.

[0085] For example, the MATLAB runtime environment is triggered using C language. The `include()` function in C then calls the MATLAB engine header file `engine.h`, and subsequently imports the `engOpen()` function from the engine API. This `engOpen()` function then controls the start of MATLAB. Once `engOpen()` opens MATLAB, logical operations can be performed using MATLAB functions, implementing a series of functional sets. This allows MATLAB to run in the background as a computational tool to complete complex calculations.

[0086] Furthermore, the `engEvalSting()` function in the engine API sends commands from the C runtime environment to the MATLAB environment, enabling a series of logical operations within MATLAB. By importing the interface input data obtained from the engine API function into SystemVerilog, it becomes possible to indirectly load the reference model into MATLAB from the verification environment using functions on the digital processing device. For example, this can be achieved through `open_system('<Simulink model> The data is passed to Matlab and then loaded into the Simulink module, engEvalSting(“open_system('<Simulink model> Through the above operations, communication can be established between the verification environment and Mtalab.

[0087] S450. When it is determined that the simulation result data matches the interface input data, the simulation result data is output through the reference model, or the simulation result data is output to a file.

[0088] S460, Trigger the shutdown of the Matlab runtime environment and the C language runtime environment.

[0089] In this embodiment, after verification is completed, the Matlab runtime environment needs to be shut down. The engClose() function in the engine API of the C language is used to close the Matlab engine and the C language runtime environment.

[0090] S470. Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, perform the first type of functional verification on the algorithm chip under test.

[0091] The technical solution provided in this invention involves acquiring interface input data simulated for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; inputting the interface input data into the reference model and triggering the execution of general programming language logic code in the reference model; during the execution of the general programming language logic code, if a target Matlab general calculation function is detected, triggering the opening of the C language runtime environment in the general programming language programming environment; triggering the opening of the Matlab runtime environment in the C language runtime environment, and triggering the call of the target Matlab general calculation function in the Matlab runtime environment; when it is determined that simulation result data matching the interface input data is obtained, the simulation result data is output through the reference model, or the simulation result data is output to a file; triggering the closure of the Matlab runtime environment and the C language runtime environment; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. Furthermore, by incorporating one or more general-purpose Matlab computation functions into the reference model, and having each general-purpose Matlab computation function executed through the hardware description language programming logic within the reference model, the accuracy, development efficiency, and verification efficiency of the reference model verification can be improved, and the accuracy and efficiency of data transmission can be guaranteed.

[0092] Example 5

[0093] Figure 5 This is a schematic diagram of the structure of a simulation verification device for an algorithm chip provided in Embodiment 5 of the present invention. The simulation verification device for an algorithm chip provided in this embodiment can be implemented by software and / or hardware, and can be configured to execute within a reference model in a hardware description language programming environment. The reference model contains built-in general-purpose programming language logic code to implement the simulation verification method for an algorithm chip in this embodiment of the present invention. Figure 5 As shown, the device may specifically include: an interface input data acquisition module 510, a simulation result data acquisition module 520, and a first type of function verification module 530.

[0094] The interface input data acquisition module 510 is used to acquire interface input data simulated for the algorithm chip under test, and the interface input data conforms to the requirements of the hardware description language programming environment.

[0095] The simulation result data acquisition module 520 is used to input the interface input data into the reference model and acquire the simulation result data obtained by the reference model through executing the general programming language logic code;

[0096] The first type of functional verification module 530 is used to perform first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data.

[0097] The technical solution provided by this invention involves acquiring simulated interface input data for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; inputting the interface input data into the reference model and acquiring simulation result data obtained by the reference model through executing the general programming language logic code; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data. This solves the problem of verifying complex algorithm protocol models, improves the accuracy and development efficiency of algorithm protocol models, and further enhances the efficiency of debugging and locating errors.

[0098] Based on the above embodiments, the reference model includes built-in interface conversion functions programmed using C or C++ language logic code and core functions encapsulated within the interface conversion functions. The core functions are adapted to the computational logic within the chip under test. The simulation result data acquisition module 520 may specifically include: a general input data conversion unit, used to input the interface input data into the interface conversion function in the reference model, and convert the interface input data into general input data through the interface conversion function, wherein the general input data conforms to the requirements of the C or C++ language environment; a result data calculation unit, used to transmit the general input data to the core function through the interface conversion function, and calculate the calculation result data matching the general input data through the core function; and a simulation result output unit, used to convert the calculation result data into simulation result data conforming to the requirements of the hardware description language programming environment and output it through the reference model, or to directly output the calculation result data as simulation result data to a file.

[0099] Based on the above embodiments, the simulation result output unit can be specifically used to: transmit the calculation result data to the interface conversion function through the core function; and convert the calculation result data into simulation result data that meets the requirements of the hardware description language programming environment through the interface conversion function and output it through the reference model.

[0100] Based on the above embodiments, the reference model has a built-in Matlab computation model programmed using Matlab language logic code, and the Matlab computation model is adapted to the computation logic within the chip under test; the simulation result data acquisition module 520 may specifically include: a Matlab computation model input unit, used to trigger the execution of the Matlab computation model through the hardware description language programming logic built into the reference model, and input the interface input data into the Matlab computation model; a simulation result data calculation unit, used to calculate simulation result data matching the interface input data through the Matlab computation model; and a simulation result data output unit, used to output the simulation result data through the reference model via the Matlab computation model, or to output the simulation result data to a file.

[0101] Based on the above embodiments, the hardware description language programming logic in the Matlab computation model input unit includes instructions for executing without a graphical interface; triggering the execution of the Matlab computation model includes: triggering background execution of the Matlab computation model so that the Matlab computation model can obtain the simulation result data without a graphical interface.

[0102] Based on the above embodiments, the reference model has one or more built-in Matlab general-purpose computation functions, each of which is executed by calling the hardware description language programming logic in the reference model. The simulation result data acquisition module 520 may specifically include: inputting the interface input data into the reference model and triggering the execution of the general-purpose programming language logic code in the reference model; during the execution of the general-purpose programming language logic code, if a target Matlab general-purpose computation function is detected, triggering the opening of the C language runtime environment in the general-purpose programming language programming environment; triggering the opening of the Matlab runtime environment in the C language runtime environment, and triggering the call of the target Matlab general-purpose computation function in the Matlab runtime environment; when it is determined that simulation result data matching the interface input data is obtained, outputting the simulation result data through the reference model, or outputting the simulation result data to a file; and triggering the closing of the Matlab runtime environment and the C language runtime environment.

[0103] Based on the above embodiments, a second type of functional verification module may also be included, which is used to: after inputting the interface input data into the reference model, further include: obtaining multiple simulation intermediate result data obtained by the reference model through executing the general programming language logic code; and performing a second type of functional verification on the algorithm chip under test based on multiple actual intermediate result data calculated by the algorithm chip under test for the interface input data, and each of the simulation intermediate result data.

[0104] The simulation verification device for the above-mentioned algorithm chip can execute the simulation verification method for the algorithm chip provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0105] Example 6

[0106] Figure 6 This is a schematic diagram of the structure of a computer device provided in Embodiment Six of the present invention. Figure 6 As shown, the device includes a processor 610, a memory 620, an input device 630, and an output device 640; the number of processors 610 in the device can be one or more. Figure 6 Taking a processor 610 as an example; the processor 610, memory 620, input device 630, and output device 640 in the device can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0107] The memory 620, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the simulation verification method of the algorithm chip in this embodiment of the invention (e.g., interface input data acquisition module 510, simulation result data acquisition module 520, and first-type functional verification module 530). The processor 610 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 620, thereby implementing the aforementioned simulation verification method of the algorithm chip. This method includes: acquiring interface input data simulated for the algorithm chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; inputting the interface input data into the reference model and acquiring simulation result data obtained by the reference model through executing the general programming language logic code; and performing first-type functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data.

[0108] The memory 620 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 620 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 620 may further include memory remotely located relative to the processor 610, which can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0109] Input device 660 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the device. Output device 640 may include display devices such as a display screen.

[0110] Example 7

[0111] Embodiment 7 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a simulation verification method for an algorithm chip. The method includes: acquiring interface input data simulated for the algorithm chip under test, the interface input data conforming to the requirements of a hardware description language programming environment; inputting the interface input data into a reference model and acquiring simulation result data obtained by the reference model through executing the logic code of the general programming language; and performing a first type of functional verification on the algorithm chip under test based on the actual result data calculated by the algorithm chip under test for the interface input data and the simulation result data.

[0112] Of course, the computer-executable instructions provided in the embodiments of the present invention are not limited to the method operations described above, but can also execute related operations in the simulation verification method of the algorithm chip provided in any embodiment of the present invention.

[0113] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0114] It is worth noting that in the embodiments of the search device described above, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0115] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A simulation verification method for an algorithm chip, executed by a reference model configured in a hardware description language programming environment, wherein the reference model has built-in general-purpose programming language logic code, characterized in that, include: Acquire simulated interface input data for the chip under test, wherein the interface input data conforms to the requirements of the hardware description language programming environment; The interface input data is input into the reference model, and the simulation result data obtained by the reference model through executing the general programming language logic code is obtained; Based on the actual result data calculated by the algorithm chip under test for the interface input data, and the simulation result data, the algorithm chip under test is subjected to the first type of functional verification. The reference model includes built-in interface conversion functions programmed using C or C++ language logic code and core functions encapsulated within the interface conversion functions. The core functions are adapted to the computational logic within the chip under test. The interface input data is input into the reference model, and the simulation result data obtained by the reference model through executing the general programming language logic code is acquired, including: The interface input data is input into the interface conversion function in the reference model, and the interface input data is converted into general input data through the interface conversion function. The general input data conforms to the requirements of the C language or C++ language environment. The general input data is transmitted to the core function through the interface conversion function, and the calculation result data matching the general input data is calculated by the core function. The calculation results data can be converted into simulation results data that meet the requirements of the hardware description language programming environment and output through the reference model, or the calculation results data can be directly output as simulation results data to a file; The reference model has a built-in Matlab calculation model obtained by programming Matlab language logic code, and the Matlab calculation model is adapted to the calculation logic in the chip under test; The interface input data is input into the reference model, and the simulation result data obtained by the reference model through executing the general programming language logic code is acquired, including: The hardware description language programming logic built into the reference model is used to trigger the execution of the Matlab computing model and input the interface input data into the Matlab computing model. The simulation result data that matches the interface input data is calculated using the Matlab calculation model. The simulation results data can be output via the reference model using the Matlab calculation model, or the simulation results data can be output to a file. The reference model contains one or more general-purpose Matlab computation functions, which are executed by calling the hardware description language programming logic in the reference model. The interface input data is input into the reference model, and the simulation result data obtained by the reference model through executing the general programming language logic code is acquired, including: The interface input data is input into the reference model, and the execution of the general programming language logic code in the reference model is triggered. During the execution of the general programming language logic code, if a target Matlab general computation function is detected, the C language runtime environment in the general programming language programming environment is triggered to start. In the C language runtime environment, the Matlab runtime environment is triggered to start, and in the Matlab runtime environment, the target Matlab general calculation function is triggered to be called; When it is determined that the simulation result data matches the input data of the interface, the simulation result data is output through the reference model, or the simulation result data is output to a file; Trigger the shutdown of the Matlab runtime environment and the C language runtime environment; The input processing module includes a sequence generator for generating interface input data; a driver for driving the data packets generated by the sequence generator into the chip under test (DUT); a monitor for monitoring the data packets input to the DUT and passing them to a reference model, which also serves as the reference model's input; the reference model for simulating and generating referenceable output data after inputting the same data as the DUT; and a scoring board for statistically analyzing and comparing the output data of the DUT and the reference model.

2. The method of claim 1, wherein, The calculation results are converted into simulation results that conform to the requirements of the hardware description language programming environment and output through the reference model, including: The calculation result data is transmitted to the interface conversion function through the core function. The calculation result data is converted into simulation result data that meets the requirements of the hardware description language programming environment through the interface conversion function and then output through the reference model.

3. The method of claim 1, wherein, The hardware description language programming logic includes instructions for executing commands with or without a graphical interface. Triggering the execution of the Matlab computation model includes: The background process is triggered to execute the Matlab computation model, so that the Matlab computation model can obtain the simulation result data without a graphical interface.

4. The method according to any one of claims 1-3, characterized in that, After inputting the interface input data into the reference model, the method further includes: Obtain multiple intermediate simulation result data from the reference model by executing the logic code of the general programming language; The second type of functional verification is performed on the algorithm chip under test based on multiple actual intermediate result data calculated by the chip under test for the interface input data, and each of the simulation intermediate result data.

5. A simulation verification device for an algorithm chip, executed by a reference model configured in a hardware description language programming environment, wherein the reference model has built-in general-purpose programming language logic code, characterized in that, include: The interface input data acquisition module is used to acquire interface input data simulated for the algorithm chip under test, and the interface input data conforms to the requirements of the hardware description language programming environment. The simulation result data acquisition module is used to input the interface input data into the reference model and acquire the simulation result data obtained by the reference model through executing the general programming language logic code; The first type of functional verification module is used to perform first type of functional verification on the algorithm chip under test based on the actual result data calculated by the chip under test for the interface input data and the simulation result data. The reference model includes built-in interface conversion functions programmed using C or C++ language logic code and core functions encapsulated within these interface conversion functions. The core functions are adapted to the computational logic within the chip under test. The simulation result data acquisition module includes: a general input data conversion unit, used to input the interface input data into the interface conversion function in the reference model, and convert the interface input data into general input data that conforms to the requirements of the C or C++ language environment; a result data calculation unit, used to transmit the general input data to the core function through the interface conversion function, and calculate the calculation result data matching the general input data through the core function; and a simulation result output unit, used to convert the calculation result data into simulation result data that conforms to the requirements of the hardware description language programming environment and output it through the reference model, or to directly output the calculation result data as simulation result data to a file. The reference model has a built-in Matlab computing model obtained by programming Matlab language logic code, and the Matlab computing model is adapted to the computing logic in the chip under test. The simulation result data acquisition module includes: a Matlab calculation model input unit, used to trigger the execution of the Matlab calculation model through the hardware description language programming logic built into the reference model, and input the interface input data into the Matlab calculation model; a simulation result data calculation unit, used to calculate simulation result data matching the interface input data through the Matlab calculation model; and a simulation result data output unit, used to output the simulation result data through the reference model via the Matlab calculation model, or to output the simulation result data to a file. The reference model contains one or more general-purpose Matlab computation functions, which are executed by calling the hardware description language programming logic in the reference model. The simulation result data acquisition module includes: inputting the interface input data into the reference model and triggering the execution of general programming language logic code in the reference model; during the execution of the general programming language logic code, if a target Matlab general calculation function is detected, triggering the opening of the C language runtime environment in the general programming language programming environment; triggering the opening of the Matlab runtime environment in the C language runtime environment, and triggering the call of the target Matlab general calculation function in the Matlab runtime environment; when it is determined that simulation result data matching the interface input data has been calculated, outputting the simulation result data through the reference model, or outputting the simulation result data to a file; and triggering the closing of the Matlab runtime environment and the C language runtime environment. The input processing module includes a sequence generator for generating interface input data; a driver for driving the data packets generated by the sequence generator into the chip under test (DUT); a monitor for monitoring the data packets input to the DUT and passing them to a reference model, which also serves as the reference model's input; the reference model for simulating and generating referenceable output data after inputting the same data as the DUT; and a scoring board for statistically analyzing and comparing the output data of the DUT and the reference model.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the simulation verification method of the algorithm chip as described in any one of claims 1-4.

7. A storage medium of computer executable instructions, on which a computer program is stored, characterized in that, When executed by the processor, this program implements the simulation verification method for the algorithm chip as described in any one of claims 1-4.

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