Chip storage device design and verification method and device, and electronic equipment

Abstract

This application discloses a method, apparatus, and electronic device for designing and verifying a chip memory device. The method includes: obtaining a memory device information table pre-extracted from a chip design document, the memory device information table including parameter information stored according to preset table positions; converting the parameter information of each memory device in the memory device information table according to the mapping relationship between the preset table positions and the parameter information to obtain a memory device parameter model; generating design code and a verification model corresponding to the memory device based on the memory device parameter model, and implementing the design of the chip memory device based on the design code, and verifying the chip memory device based on the verification model. This avoids repetitive manual operations and, based on a single chip design document, avoids invalid verification caused by information asymmetry between the design and verification processes.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a chip storage device design and verification method, apparatus and electronic device. Background Technology

[0002] Currently, many industries incorporate chips into their products and equipment to perform intelligent tasks. As people's demand for intelligence increases, chips are becoming increasingly important in the structure of these products and equipment.

[0003] Generally, chip design involves design and verification. During the design process, designers need to manually write Register Transfer Level (RTL) code for all memory devices in the design document to interact with the bus. Verification personnel need to manually set the corresponding register models for all memory devices in the design document.

[0004] Both processes involve a large number of storage devices, making these tasks repetitive and manual, potentially leading to numerous unpredictable errors. Furthermore, changes in design requirements necessitate modifications to the design documents. On one hand, both designers and verifiers need to modify the RTL code and register model accordingly, increasing the likelihood of errors. On the other hand, the design documents for both designers and verifiers need to be updated synchronously. However, information gaps may exist between designers and verifiers, meaning that after modifications, the referenced design documents may differ, rendering the verification process ineffective and wasting resources. Summary of the Invention

[0005] This application provides a chip storage device design and verification method, apparatus, and electronic device to reduce manual operation and error probability in the chip storage device design and verification process.

[0006] In a first aspect, embodiments of this application provide a method for designing and verifying a chip memory device, the method comprising:

[0007] Obtain a storage device information table extracted in advance from the chip design document, the storage device information table including parameter information stored according to a preset table position;

[0008] Based on the mapping relationship between the preset table position and parameter information, the parameter information of each storage device in the storage device information table is transformed to obtain the storage device parameter model;

[0009] The design code and verification model corresponding to the storage device are generated based on the storage device parameter model. The design of the chip storage device is implemented based on the design code, and the chip storage device is verified based on the verification model.

[0010] Secondly, embodiments of this application also provide a chip memory device design and verification apparatus, which includes:

[0011] The acquisition module is used to acquire a storage device information table extracted in advance from the chip design document. The storage device information table includes parameter information stored according to a preset table position.

[0012] The conversion module is used to convert the parameter information of each storage device in the storage device information table according to the preset table position and parameter information mapping relationship to obtain the storage device parameter model;

[0013] The design and verification module is used to generate design code and verification model corresponding to the storage device based on the storage device parameter model, and to implement the design of the chip storage device based on the design code and to verify the chip storage device based on the verification model.

[0014] Thirdly, embodiments of this application also provide an electronic device, the electronic device comprising:

[0015] One or more processors;

[0016] Storage device for storing one or more programs.

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement the chip storage device design and verification method provided in any embodiment of this application.

[0018] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, characterized in that, when the program is executed by a processor, it implements the chip storage device design and verification method provided in any embodiment of this application.

[0019] The technical solution of this application embodiment transforms the storage device information table pre-extracted from the chip design document to obtain a storage device parameter model. Then, based on the storage device parameter model, corresponding design code and verification model are generated, thereby realizing the design and verification of the chip storage device. This process uses the generated storage device parameter model to avoid repetitive manual operations and allows the machine to perform them automatically. Moreover, it is based on a single chip design document. No matter how the chip design document changes, the generation of design code and verification model is based on the same chip design document, avoiding the situation of invalid verification caused by information asymmetry in the design and verification process. Attached Figure Description

[0020] Figure 1 A flowchart illustrating the chip storage device design and verification method provided in Embodiment 1 of this application;

[0021] Figure 2 This is a schematic diagram of a process for converting a storage device information table, provided in Embodiment 2 of this application;

[0022] Figure 3 This is a schematic diagram of a process for generating design code provided in Embodiment 3 of this application;

[0023] Figure 4 A schematic diagram of a process for generating a verification model is provided for Embodiment 4 of this application;

[0024] Figure 5 This is a flowchart illustrating a chip storage device design and verification method provided in Embodiment 5 of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a chip storage device design and verification apparatus provided in Embodiment Six of this application;

[0026] Figure 7 This is a schematic diagram of the structure of an electronic device provided in Embodiment 7 of this application. Detailed Implementation

[0027] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0028] Example 1

[0029] Figure 1This is a flowchart illustrating the chip memory device design and verification method provided in Embodiment 1 of this application. This embodiment is applicable to scenarios involving chip memory device design and verification. The method can be executed by a chip memory device design and verification device, which can be implemented in hardware and / or software and is generally integrated into electronic devices such as computers with data processing capabilities. Specifically, it includes the following steps:

[0030] Step 101: Obtain the storage device information table extracted from the chip design document in advance. The storage device information table includes parameter information stored according to the preset table positions.

[0031] In this step, the process of extracting the storage device information table from the chip design document in advance can be done manually. Generally, the design document will design some functional modules, and there will be a large number of storage devices, namely registers and memory, in the functional modules. The design document will indicate the parameter information of each storage device. Since the document format of the design document will be different in different companies or even different projects, the way the parameter information of the storage device in the design document will also be different. Therefore, in order to improve the universality of the solution in this embodiment, the parameter information of the storage device can be extracted manually from the chip design document and stored in a certain preset table position to form a storage device information table.

[0032] In a specific example, the storage device information table can be shown in Table 1 below:

[0033] Table 1

[0034]

[0035] In this table, REGISTER serves as the start marker for each register; the name of the register is indicated in parentheses in the second column of the first row; the second row contains the address information for the register, with the data after the colon in the second column representing the offset of the register from the base address. The third row contains the corresponding bit field information, where the second column shows the bit width and address information for each field; the third column is the name of the smallest unit field of the register; the fourth column describes the read / write attributes, which must conform to the register's read / write rules; the fifth column is the corresponding reset value; and the sixth column is a description of the corresponding smallest unit.

[0036] Additionally, it should be noted that the process of converting chip design documents into storage device information tables is not limited to the manual method mentioned above. Since the parameter information of storage devices in most chip design documents is stored in a relatively regular manner, this embodiment can also use a text recognition model to identify the corresponding information from the chip design documents according to the cell definitions in the storage device information table and fill it into the corresponding cells.

[0037] In this context, cell definition refers to which parameters need to be filled in for a particular cell in the table.

[0038] Step 102: Based on the mapping relationship between the preset table position and parameter information, convert the parameter information of each storage device in the storage device information table to obtain the storage device parameter model.

[0039] In this step, the preset table position refers to the table position in the new information table of the storage device, such as the first row and first column, the first row and third column, etc. The mapping relationship between the preset table position and the parameter information refers to the correspondence between the parameter information stored in the cell. For details, please refer to Table 1 in the previous steps.

[0040] In addition, the conversion in this step mainly involves extracting the parameter information and then encapsulating it into a specific format to facilitate the automation of subsequent steps.

[0041] It should be noted that the specific conversion process will be explained in subsequent embodiments, and will not be repeated here.

[0042] Step 103: Generate the design code and verification model corresponding to the storage device based on the storage device parameter model, and implement the design of the chip storage device based on the design code, and verify the chip storage device based on the verification model.

[0043] In this step, the design code refers to the code that the storage device relies on to interact with the bus. Since the code format is fixed, in this step, it is only necessary to assign the parameter information of different storage devices to the corresponding positions in the code.

[0044] In addition, the verification model, also known as the common register model, is a software model used to simulate hardware registers. Its format is relatively fixed, and it also requires assigning the parameter information of different storage devices to the corresponding positions in the model code.

[0045] In this embodiment, a storage device parameter model is obtained by converting the storage device information table pre-extracted from the chip design document. Then, corresponding design code and verification model are generated based on the storage device parameter model, thereby realizing the design and verification of the chip storage device. This process uses the generated storage device parameter model to avoid repetitive manual operations and is automatically performed by the machine. Moreover, it is based on the same chip design document. No matter how the chip design document changes, the design code and verification model are based on the same chip design document, avoiding the situation of invalid verification caused by information asymmetry in the design and verification process.

[0046] Example 2

[0047] Please see Figure 2 , Figure 2 This is a schematic diagram of a process for converting a storage device information table, provided in Embodiment 2 of this application.

[0048] like Figure 2 As shown, in this embodiment, the process of converting the storage device information table may include:

[0049] Step 201: Traverse the preset start identifiers from the storage device information table.

[0050] In this step, the start identifier refers to the starting identifier in the storage device information table that marks the beginning of recording the parameter information of the new storage device, as shown in Table 1. The start identifier is the register in Table 1. Of course, register is just a specific example provided in this embodiment. In specific implementation, the specific form of the start identifier can be customized.

[0051] Of course, the start identifier has a certain uniqueness in the storage device information table, that is, it cannot conflict with other defined names.

[0052] Since the parameter information of each storage device in the storage device information table is recorded in a sequential order, this step can traverse the start identifier in the storage device information table. Each time a start identifier is traversed, the subsequent steps can be executed once, until all start identifiers in the storage device information table have been traversed.

[0053] Step 202: When any start identifier is encountered during traversal, based on the position of the start identifier in the storage information table and the mapping relationship between the preset table position and the parameter information, determine the target table position of each parameter information of the storage device corresponding to the start identifier in the storage device information table.

[0054] Since the storage device information table stores the parameter information of all storage devices, the parameter information of a storage device is generally stored according to the preset table position, that is, the position of each parameter information cell is fixed.

[0055] Therefore, in this step, the position of the start identifier can be used as a reference to obtain the parameter information. Taking Table 1 as an example, the second row and second column correspond to the address offset of the storage unit based on the base address. So, taking the position of the start identifier as the reference, if the start identifier is in the 30th row and 25th column of the storage device information table, then after treating it as the first row and first column, the other parameter information can be based on the mapping relationship by adding 29 to the row and 24 to the column. So, in this example, the position of the address offset in the storage device information table is the (2+29=31)th row and the (2+24=26)th column.

[0056] Based on the above method and the mapping relationship between each parameter information and the preset table position, the target table position corresponding to each parameter information can be obtained.

[0057] Step 203: Read the parameter information of the storage device corresponding to the start identifier from the target table position.

[0058] Since the previous steps have determined the specific target table location of each parameter information in the storage device information table, this step can directly extract the information from the corresponding target table location.

[0059] Step 204: When all start identifiers have been traversed, the parameter information of the storage device corresponding to each start identifier is encapsulated according to a preset format to obtain the storage device parameter model.

[0060] In this step, the preset format can be the format required by the ralf file. Since some preset tools will be used in the subsequent process, and the input of these tools has certain requirements on the file format, such as the Synopsys ralgen tool, which requires the input to be in the format required by the ralf file, the preset format of the powder in this step should be consistent with the requirements of the tools used later.

[0061] It should be noted that, in the aforementioned process, the parameter information may include name, offset address, bit field name, bit field read / write attribute, reset value, etc.

[0062] Example 3

[0063] Please see Figure 3 , Figure 3 This is a schematic diagram of a process for generating design code provided in Embodiment 3 of this application.

[0064] like Figure 3 As shown, the process of generating design code provided in this embodiment may include:

[0065] Step 301: Generate storage device read code and storage device write code according to the storage device parameter model.

[0066] It should be noted that since the code format is fixed, in this embodiment, it is only necessary to assign the parameter information of different storage devices to the corresponding positions in the code.

[0067] To generate the storage device read code, a preset read code template can be obtained first, and the read parameters of each storage device can be extracted from the storage device parameter model. For any storage device, the read parameters of the storage device are assigned to the preset read code template to obtain the storage device read code.

[0068] Specifically, taking a register as an example, the read parameters can include the register name, offset address, bit field name, bit field read / write attribute, and reset value. In a specific example, the offset address information defined for the register is assigned the corresponding FIRST_REGISSTER_ADDR offset address, and the field name is combined in the corresponding square brackets.

[0069] For generating write codes for storage devices, a preset write code template can be obtained first, and the write parameters of each storage device can be extracted from the storage device parameter model. For any storage device, the write parameters of the storage device are assigned to the preset write code template to obtain the write code for the storage device.

[0070] Specifically, taking registers as an example, the parameters to be written can include reset values, offset addresses, etc.

[0071] Step 302: Encapsulate the storage device read code and storage device write code into the design code corresponding to the storage device.

[0072] In this step, by encapsulating the storage device read code and storage device write code together, the corresponding design code can be obtained.

[0073] Example 4

[0074] Please see Figure 4 , Figure 4 This is a schematic diagram of a process for generating a verification model, provided as an embodiment of this application.

[0075] like Figure 4 As shown, the process of correcting the instrument image provided in this embodiment may include:

[0076] Step 401: Obtain the preset verification model template and extract the simulation parameters of each storage device from the storage device parameter model.

[0077] This step is the same as the process of extracting and writing parameters described above, and can be referred to accordingly. It will not be repeated here.

[0078] Specifically, taking registers as an example, simulation parameters can include the name of the corresponding block, the total length of the corresponding register being 4 bytes, the register name (first_reg) for each register, the corresponding offset address, the number of bits in each bit field, read / write attributes, reset value information, etc.

[0079] Step 402: Assign the simulation parameters to the preset verification model template to obtain the verification model corresponding to the storage device.

[0080] In this step, similar to the aforementioned design code generation process, the obtained simulation parameters are assigned to the corresponding preset verification model template.

[0081] To facilitate the implementation of the aforementioned operations, this embodiment allows the storage device parameter model to be input into a preset tool, and the verification model output by the preset tool to be obtained. The preset tool can then be used to perform the aforementioned steps. Specifically, the preset tool can be, but is not limited to, the ralgen tool or the RegWorks Spec2Reg tool.

[0082] Example 5

[0083] Please see Figure 5 , Figure 5 This is a flowchart illustrating a chip storage device design and verification method provided in Embodiment 5 of this application.

[0084] like Figure 5 As shown, the chip memory device design and verification method provided in this embodiment can be implemented using Python. Specifically, the chip memory device design and verification method provided in this embodiment may include:

[0085] Step 501: Input the design document and convert it into an Excel spreadsheet.

[0086] It should be noted that the conversion process in this step can refer to step 101 of the aforementioned embodiment one, and will not be repeated here.

[0087] For ease of understanding, this embodiment uses Table 1 from Embodiment 1 as an example to explain the subsequent steps.

[0088] Step 502: Identify the sheet number of the corresponding table. The sheet number is defined as the Ralf name corresponding to the block.

[0089] In this step, the table refers to the aforementioned storage device information table. The sheet number is the page number in the storage device information table. Generally, a storage device information table file may contain multiple pages, and each page will be assigned a sheet number.

[0090] It should be noted that since the design document contains storage devices corresponding to multiple functional modules, each functional module's storage device constitutes a block. Correspondingly, each block will output a storage device parameter model, and the name of this model can also be the assigned sheet number.

[0091] Step 503: Read the information of each row in the corresponding sheet and define the corresponding parameter access method.

[0092] This step is the traversal process mentioned in the previous embodiments. For details, please refer to step 201 in Embodiment 2, which will not be repeated here.

[0093] In addition, the parameter storage method defined in this step refers to the predefined mapping relationship between the preset table position and the parameter information.

[0094] Step 504: Use "register" as the keyword to identify the beginning of each register, and use the name in parentheses as the name of the register.

[0095] It should be noted that the "register" in keyword recognition here refers to the start identifier.

[0096] Step 505: Use the identified offset as the offset address.

[0097] Step 506: Use info as the starting point for identifying the bit field in the next line.

[0098] Step 507: Identify whether the read / write attribute of the fourth example is within the range, use the second column as the number of bits, the third column as the number of bits, and the fifth column as the reset value.

[0099] This step involves reading the corresponding parameters based on the position of the start identifier in the stored information table and the mapping relationship between the preset table position and the parameter information. For details, please refer to step 202 of Embodiment 2.

[0100] Step 508: If the information of each corresponding row is continuously identified as empty, it means that the corresponding register is complete. Start the next row of registers and continue until all registers have been collected, including their names, addresses, domain names, address ranges, and reset values.

[0101] Step 509: Generate RAL_model in the Ralf file.

[0102] In this step, the storage device parameter model in the aforementioned embodiments is generated.

[0103] Step 510: Convert RAL_model into corresponding RTL code (design code) using Python, and generate the uvm register model (verification model) from the resulting Ralf file.

[0104] Example 6

[0105] Figure 6 This is a schematic diagram of a chip memory device design and verification apparatus provided in Embodiment Six of this application. The chip memory device design and verification apparatus provided in this embodiment can execute the chip memory device design and verification methods provided in any embodiment of this application, and possesses the corresponding functional modules and beneficial effects of the method execution. This apparatus can be implemented in software and / or hardware, such as... Figure 6As shown, the chip storage device design and verification device specifically includes: an acquisition module 601, a conversion module 602, and a design and verification module 603.

[0106] The acquisition module is used to acquire a storage device information table extracted in advance from the chip design document. The storage device information table includes parameter information stored according to a preset table position.

[0107] The conversion module is used to convert the parameter information of each storage device in the storage device information table according to the preset mapping relationship between table position and parameter information, so as to obtain the storage device parameter model;

[0108] The design and verification module is used to generate design code and verification model corresponding to the storage device based on the storage device parameter model, and to implement the design of the chip storage device based on the design code and to verify the chip storage device based on the verification model.

[0109] In this embodiment, a storage device parameter model is obtained by converting the storage device information table pre-extracted from the chip design document. Then, corresponding design code and verification model are generated based on the storage device parameter model, thereby realizing the design and verification of the chip storage device. This process uses the generated storage device parameter model to avoid repetitive manual operations and is automatically performed by the machine. Moreover, it is based on the same chip design document. No matter how the chip design document changes, the design code and verification model are based on the same chip design document, avoiding the situation of invalid verification caused by information asymmetry in the design and verification process.

[0110] Furthermore, the conversion module includes:

[0111] The traversal unit is used to traverse the preset start identifier from the storage device information table;

[0112] The determining unit is used to determine the target table position of each parameter information of the storage device corresponding to the start identifier in the storage device information table, based on the position of the start identifier in the storage information table and the mapping relationship between the preset table position and the parameter information, when any start identifier is traversed;

[0113] The reading unit is used to read parameter information of the storage device corresponding to the start identifier from the target table position;

[0114] The first encapsulation unit is used to encapsulate the parameter information of the storage device corresponding to each start identifier according to a preset format when all start identifiers have been traversed, so as to obtain the storage device parameter model.

[0115] Furthermore, the design and verification module includes:

[0116] The code generation unit is used to generate storage device read code and storage device write code respectively based on the storage device parameter model;

[0117] The second encapsulation unit is used to encapsulate the storage device read code and storage device write code into the design code corresponding to the storage device.

[0118] Furthermore, the code generation unit includes:

[0119] The first acquisition subunit is used to acquire a preset read code template and extract the read parameters of each storage device from the storage device parameter model.

[0120] The first assignment subunit is used to assign the read parameters of any storage device to a preset read code template to obtain the read code of the storage device.

[0121] The second acquisition subunit is used to acquire a preset write code template and extract the write parameters of each storage device from the storage device parameter model.

[0122] The second assignment subunit is used to assign the write parameters of any storage device to a preset write code template to obtain the storage device write code.

[0123] Furthermore, the design and verification module includes:

[0124] The template acquisition unit is used to acquire a preset verification model template and extract the simulation parameters of each storage device from the storage device parameter model.

[0125] The assignment unit is used to assign simulation parameters to a preset verification model template to obtain the verification model corresponding to the storage device.

[0126] Furthermore, the design and verification module includes:

[0127] The verification model generation unit is used to input the storage device parameter model into the preset tool and obtain the verification model output by the preset tool.

[0128] Furthermore, the default tools are the ralgen tool or the RegWorks Spec2Reg tool.

[0129] Example 7

[0130] Figure 7 This is a schematic diagram of the structure of an electronic device provided in Embodiment Seven of this application, as shown below. Figure 7 As shown, the electronic device includes a processor 710, a memory 720, an input device 730, and an output device 740; the number of processors 710 in the electronic device can be one or more. Figure 7Taking a processor 710 as an example; the processor 710, memory 720, input device 730, and output device 740 in the electronic device can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0131] The memory 720, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip storage device design and verification method in the embodiments of this application (e.g., the acquisition module 601, conversion module 602, and design and verification module 603 in the chip storage device design and verification apparatus). The processor 710 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the memory 720, thereby realizing the aforementioned chip storage device design and verification method.

[0132] That is, obtain the storage device information table extracted in advance from the chip design document. The storage device information table includes parameter information stored according to the preset table position.

[0133] Based on the mapping relationship between the preset table position and parameter information, the parameter information of each storage device in the storage device information table is transformed to obtain the storage device parameter model;

[0134] The design code and verification model of the storage device are generated based on the parameter model of the storage device. The design code is used to implement the design of the chip storage device, and the verification model is used to verify the chip storage device.

[0135] The memory 720 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 720 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 720 may further include memory remotely located relative to the processor 710, which can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0136] The input device 730 can be used to receive input electrical construction drawings and generate key signal inputs related to user settings and function control of electronic equipment. The output device 740 may include display devices such as a display screen.

[0137] Example 8

[0138] Embodiment 8 of this application also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a chip storage device design and verification method, the method comprising:

[0139] Obtain a storage device information table extracted in advance from the chip design document. The storage device information table includes parameter information stored according to the preset table positions.

[0140] Based on the mapping relationship between the preset table position and parameter information, the parameter information of each storage device in the storage device information table is transformed to obtain the storage device parameter model;

[0141] The design code and verification model of the storage device are generated based on the parameter model of the storage device. The design code is used to implement the design of the chip storage device, and the verification model is used to verify the chip storage device.

[0142] Of course, the computer-executable instructions provided in the embodiments of this application are not limited to the above-described method operations, but can also perform related operations in the chip storage device design and verification method provided in any embodiment of this application.

[0143] Based on the above description of the implementation methods, those skilled in the art can clearly understand that this application can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0144] It is worth noting that in the embodiments of the search device described above, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of this application.

[0145] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A method for designing and verifying a chip memory device, comprising: The method includes: Obtain a storage device information table extracted in advance from the chip design document, the storage device information table including parameter information stored according to a preset table position; Based on the preset mapping relationship between table positions and parameter information, the parameter information of each storage device in the storage device information table is transformed to obtain a storage device parameter model. This transformation, based on the preset mapping relationship between table positions and parameter information, includes: Iterate through the preset start identifiers in the storage device information table; When any of the start identifiers is encountered, the target table position of each parameter information of the storage device corresponding to the start identifier in the storage device information table is determined based on the position of the start identifier in the storage device information table and the mapping relationship between the preset table position and the parameter information. Read the parameter information of the storage device corresponding to the start identifier from the target table position; When all start identifiers have been traversed, the parameter information of the storage device corresponding to each start identifier is encapsulated according to a preset format to obtain the storage device parameter model. Generate design code and verification model corresponding to the storage device based on the storage device parameter model, wherein generating design code corresponding to the storage device based on the storage device parameter model includes: Generate storage device read code and storage device write code based on the storage device parameter model, comprising: obtaining a preset read code template and extracting read parameters for each storage device from the storage device parameter model; for any storage device, assigning the read parameters of the storage device to the preset read code template to obtain the storage device read code; obtaining a preset write code template and extracting write parameters for each storage device from the storage device parameter model; for any storage device, assigning the write parameters of the storage device to the preset write code template to obtain the storage device write code; The storage device read code and the storage device write code are encapsulated into the design code corresponding to the storage device; The design of the chip storage device is implemented based on the design code, and the chip storage device is verified based on the verification model.

2. The method of claim 1, wherein, Generate a verification model corresponding to the storage device based on the storage device parameter model, including: Obtain a preset verification model template and extract the simulation parameters of each storage device from the storage device parameter model; The simulation parameters are assigned to the preset verification model template to obtain the verification model corresponding to the storage device.

3. The method of claim 1, wherein, Generate a verification model corresponding to the storage device based on the storage device parameter model, including: The storage device parameter model is input into a preset tool, and the verification model output by the preset tool is obtained.

4. The method of claim 3, wherein, The preset tool is either the ralgen tool or the RegWorksSpec2Reg tool.

5. A chip storage device design and verification apparatus, characterized by comprising: The device includes: The acquisition module is used to acquire a storage device information table extracted in advance from the chip design document. The storage device information table includes parameter information stored according to a preset table position. A conversion module is used to convert the parameter information of each storage device in the storage device information table according to a preset mapping relationship between table positions and parameter information to obtain a storage device parameter model. The conversion of the parameter information of each storage device in the storage device information table according to the preset mapping relationship to obtain the storage device parameter model includes: traversing preset start identifiers in the storage device information table; when any start identifier is encountered, determining the target table position of each parameter information of the storage device corresponding to the start identifier in the storage device information table based on the position of the start identifier in the storage device information table and the preset mapping relationship between table positions and parameter information; reading the parameter information of the storage device corresponding to the start identifier from the target table position; and when all start identifiers have been traversed, encapsulating the parameter information of the storage device corresponding to each start identifier according to a preset format to obtain the storage device parameter model. The design and verification module is used to generate design code and verification model corresponding to the storage device based on the storage device parameter model. The step of generating the design code corresponding to the storage device based on the storage device parameter model includes: generating storage device read code and storage device write code based on the storage device parameter model, which includes: obtaining a preset read code template and extracting read parameters for each storage device from the storage device parameter model; for any storage device, assigning the read parameters of the storage device to the preset read code template to obtain the storage device read code; obtaining a preset write code template and extracting write parameters for each storage device from the storage device parameter model; for any storage device, assigning the write parameters of the storage device to the preset write code template to obtain the storage device write code; encapsulating the storage device read code and the storage device write code into design code corresponding to the storage device; implementing the design of the chip storage device based on the design code; and verifying the chip storage device based on the verification model.

6. An electronic device, comprising: The electronic device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the chip memory device design and verification method as described in any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the chip memory device design and verification method as described in any one of claims 1-4.

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