An equivalence verification method and system based on FPGA prototype verification

Abstract

The application discloses an equivalence verification method and system based on FPGA prototype verification, and the method comprises the following steps: S1, receiving circuit models C RTL , C GATE , C FPGA corresponding to RTL, gate level net list and FPGA net list, wherein each circuit model has N corresponding comparison points, and N is a natural number; S2, establishing a search circuit, meanwhile, matching the comparison points of the circuit models C RTL , C GATE , C FPGA , and dividing the circuit models C RTL , C GATE , C FPGA into a plurality of corresponding logic cones according to the matched comparison points; and S3, simultaneously performing equivalence verification on the corresponding logic cones in the circuit models C RTL , C GATE , C FPGA . The equivalence verification method based on FPGA prototype verification can improve the accuracy of FPGA prototype verification.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit equivalence verification, and in particular to an equivalence verification method and system based on FPGA prototype verification. Background Technology

[0002] In complex ASIC chip design, various types of verification are required to ensure the functional correctness of the design. Complementing different verification methods can improve the coverage of IC verification. The main methods of functional verification include software simulation, hardware acceleration / simulation, FPGA prototyping, and formal verification.

[0003] FPGA prototyping involves directly programming the design into an FPGA chip and placing the chip in a test system or application development environment. The correctness of the chip design can be verified by inputting test vectors into the FPGA hardware or by running the software system directly on the FPGA hardware. Essentially, it aims to rapidly implement the hardware circuitry of an ASIC design, allowing the software module to run at high speed on real hardware, achieving hardware-software co-verification of the ASIC design. To program the design into the FPGA chip, the original logic design needs to be synthesized using FPGA to generate an FPGA netlist. A common method for verifying the equivalence of the RTL (Registry Transfer Level) and the gate-level netlist after logic synthesis with the FPGA netlist is to perform equivalence checks separately on the RTL and FPGA netlists, the RTL and gate-level netlists, and the FPGA netlist and gate-level netlists. If each pair of these pairs is equivalent, then the RTL, gate-level netlist, and FPGA netlist are equivalent.

[0004] However, with the increasing complexity and scale of ASIC circuits and the continuous optimization of FPGA designs, the differences between the structure of FPGA netlists and gate-level netlists are becoming increasingly significant. This results in situations where, even when RTL and FPGA netlists, and RTL and gate-level netlists are equivalent, the FPGA netlist and gate-level netlist are not equivalent. Alternatively, issues with FPGA synthesis may cause the RTL and FPGA netlist to be inequivalent. This could lead to discrepancies between the final test results after tape-out and the test results of the FPGA prototype verification. For example, the FPGA prototype verification might show correct functionality, but the actual chip after tape-out might have incorrect functionality, resulting in significant losses for the designer. Summary of the Invention

[0005] The purpose of this invention is to address the technical problem of inaccurate FPGA prototype verification results in the prior art. This invention proposes an equivalence verification method and system based on FPGA prototype verification that provides accurate verification results.

[0006] In this embodiment of the invention, an equivalence verification method based on FPGA prototype verification is provided, which includes:

[0007] Step S1: Receive the circuit model C corresponding to the RTL, gate-level netlist, and FPGA netlist. RTL C GATE C FPGA Each circuit model has N corresponding comparison points, where N is a natural number;

[0008] Step S2: Establish the search circuit, and simultaneously modify the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the circuit models C are compared based on the matched comparison points. RTL C GATE C FPGA Divide into multiple corresponding logic cones;

[0009] Step S3: Simultaneously process the circuit model C RTL C GATE C FPGA The equivalence of the corresponding logic cones is verified.

[0010] In this embodiment of the invention, step S2, establishing the search circuit, includes:

[0011] C RTL The next state is from RPO1 to RPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-master input RPI1 to RPI n C GATE The next state is from IPO1 to IPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-main input IPI1 to IPI n C FPGA The next state is HPO1 to HPO n This means that the next state depends on the basic inputs PI1 to Pi. p And pseudo-master input HPI1 to HPI n .

[0012] In this embodiment of the invention, in step S2, the circuit model C is simultaneously... RTL C GATE C FPGA The comparison points are matched, including:

[0013] Search for test vectors to make

[0014] Determine if n is less than 2. If n is greater than 2, then let... Continue searching for test vectors. If n is less than 2, end the search and form a comparison point matching pair.

[0015] In this embodiment of the invention, a random method or the ATPG method is used to search for test vectors.

[0016] In this embodiment of the invention, in step S2, the circuit model C is... RTL C GATE C FPGA After dividing the circuit into logic cones, the logic cones of each circuit model are stored in the form of linked lists.

[0017] In this embodiment of the invention, in step S3, the circuit model C is simultaneously... RTL C GATE C FPGA The corresponding logic is used to perform equivalence verification, including:

[0018] The circuit model C is respectively RTL C GATE C FPGA The outputs of the three corresponding logic cones are XORed pairwise, and the result is then ORed to output PO.

[0019] Search for a test vector. If a test vector exists such that PO = 1, then the three corresponding logical cones are not equivalent; otherwise, the three corresponding logical cones are equivalent.

[0020] If circuit model C RTL C GATE C FPGA If all corresponding logic cones are equivalent, then RTL, gate-level netlists and FPGA netlists are equivalent; otherwise, they are not equivalent.

[0021] In this embodiment of the invention, a random method or the ATPG method is used to search for test vectors.

[0022] In this embodiment of the invention, an equivalence verification system based on FPGA prototype verification is also provided, which adopts the above-mentioned equivalence verification method based on FPGA prototype verification when performing prototype verification on FPGA.

[0023] Compared with existing technologies, the equivalence verification method and system based on FPGA prototype verification of the present invention establishes a search circuit and simultaneously verifies the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the circuit models C are compared based on the matched comparison points. RTL C GATE C FPGADivide into multiple corresponding logic cones, and simultaneously apply the circuit model C RTL C GATE C FPGA The corresponding logic cones are used for equivalence verification. At the same time, equivalence verification is performed between RTL and gate-level netlist, RTL and FPGA netlist, and gate-level netlist and FPGA netlist to ensure the consistency between the FPGA verification results and the test results after the actual product is fabricated. Attached Figure Description

[0024] Figure 1 This is a flowchart of an equivalence verification method based on FPGA prototype verification according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the search circuit in an embodiment of the present invention.

[0026] Figure 3 This is a flowchart of the comparison point matching algorithm in an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of a logic circuit that performs equivalence verification on corresponding logic cones in three circuit models simultaneously, according to an embodiment of the present invention. Detailed Implementation

[0028] like Figure 1 As shown in the figure, this embodiment of the invention provides an equivalence verification method based on FPGA prototype verification, which includes steps S1-S3. These are described below.

[0029] Step S1: Receive the circuit model C corresponding to the RTL, gate-level netlist, and FPGA netlist. RTL C GATE C FPGA Each circuit model has N corresponding comparison points, where N is a natural number.

[0030] It should be noted that FPGA synthesis of the original logic design yields the RTL, gate-level netlist, and the corresponding circuit model C of the FPGA netlist. RTL C GATE C FPGA In these three circuit models, there are N corresponding comparison points, where N is a natural number.

[0031] Step S2: Establish the search circuit, and simultaneously modify the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the circuit models C are compared based on the matched comparison points. RTL C GATE C FPGA It is divided into multiple corresponding logic cones.

[0032] like Figure 2 As shown, in the established search circuit, C RTL The next state is from RPO1 to RPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-master input RPI1 to RPI n C GATE The next state is from IPO1 to IPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-main input IPI1 to IPI n C FPGA The next state is HPO1 to HPO n This means that the next state depends on the basic inputs PI1 to Pi. p And pseudo-master input HPI1 to HPI n .

[0033] like Figure 3 As shown, after establishing the search circuit, the search circuit can be used to simultaneously search the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the process includes:

[0034] Search for test vectors to make

[0035] Determine if n is less than 2.

[0036] If n is greater than 2, then let And continue searching for test vectors;

[0037] If n is less than 2: end the search, form a matching pair of comparison points, and convert the circuit model C. RTL C GATE C FPGA It is divided into logical cones.

[0038] When searching for test vectors, use a random method or the ATPG (Automatic Test Pattern Generation) method to search for test vectors.

[0039] Circuit model C RTL C GATE C FPGA After dividing the circuit model into logic cones, each logic cone is stored in a linked list. It should be noted that circuit model C... RTL Divided into logic cones A1, A2, ... AN, circuit model C RTLDivided into logic cones B1, B2, ..., BN, circuit model C RTL The circuit is divided into logic cones C1, C2, ..., CN, and the logic cones of each circuit model are stored in the form of a linked list.

[0040] Step S3: Simultaneously process the circuit model C RTL C GATE C FPGA The equivalence of the corresponding logic cones is verified.

[0041] Specifically, at the same time, circuit model C RTL C GATE C FPGA The corresponding logic is used to perform equivalence verification, including:

[0042] The circuit model C is respectively RTL C GATE C FPGA The outputs of the three corresponding logic cones are XORed pairwise, and the result is then ORed to output PO.

[0043] Use the random method or the ATPG method to search for test vectors. If there exists a test vector such that PO = 1, then the three corresponding logic cones are not equivalent; otherwise, the three corresponding logic cones are equivalent.

[0044] If circuit model C RTL C GATE C FPGA If all corresponding logic cones are equivalent, then RTL, gate netlist and FPGA netlist are equivalent; otherwise, they are not equivalent.

[0045] It should be noted that, taking the equivalence verification of logic cones A1, B1, and C1 as an example, the circuit model C is respectively... RTL C GATE C FPGA The result of performing a pairwise XOR operation on the outputs of the three corresponding logic cones, followed by a OR operation on the result, can be implemented as follows:

[0046] Connect the outputs of A1 and B1 to an XOR gate; the XOR gate outputs 0. Connect the outputs of B1 and C1 to an XOR gate; the XOR gate outputs P. Connect the outputs of A1 and C1 to an XOR gate; the XOR gate outputs Q. Connect 0, P, and Q to an OR gate; the OR gate outputs PO. The circuit diagram is shown below. Figure 4 As shown.

[0047] In this embodiment of the invention, an equivalence verification system based on FPGA prototype verification is also provided, which adopts the above-mentioned equivalence verification method based on FPGA prototype verification when performing prototype verification on FPGA.

[0048] In summary, the equivalence verification method and system based on FPGA prototype verification of the present invention establishes a search circuit and simultaneously verifies the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the circuit models C are compared based on the matched comparison points. RTL C GATE C FPGA Divide into multiple corresponding logic cones, and simultaneously apply the circuit model C RTL C GATE C FPGA The corresponding logic cones are used for equivalence verification. At the same time, equivalence verification is performed between RTL and gate-level netlist, RTL and FPGA netlist, and gate-level netlist and FPGA netlist to ensure the consistency between the FPGA verification results and the test results after the actual product is fabricated.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An equivalence verification method based on FPGA prototype verification, characterized in that, include: Step S1: Receive the circuit model C corresponding to the RTL, gate-level netlist, and FPGA netlist. RTL C GATE C FPGA Each circuit model has N corresponding comparison points, where N is a natural number; Step S2: Establish the search circuit, and simultaneously modify the circuit model C. RTL C GATE C FPGA The comparison points are matched, and the circuit models C are compared based on the matched comparison points. RTL C GATE C FPGA Divide into multiple corresponding logic cones; Step S3: Simultaneously process the circuit model C RTL C GATE C FPGA Equivalence verification is performed on the corresponding logical cones in the model; In step S2, the search circuit is established, including: C RTL The next state is from RPO1 to RPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-master input RPI1 to RPI n C GATE The next state is from IPO1 to IPO. n This means that the next state depends on the basic inputs PI1 to Pi. p and pseudo-main input IPI1 to IPI n C FPGA The next state is HPO1 to HPO n This means that the next state depends on the basic inputs PI1 to Pi. p And pseudo-master input HPI1 to HPI n ; Simultaneously, the circuit model C RTL C GATE C FPGA The comparison points are matched, including: Search for test vectors to make ; Determine if n is less than 2. If n is greater than 2, then let... And continue searching for test vectors. If n is less than 2, end the search and form a comparison point matching pair.

2. The equivalence verification method based on FPGA prototype verification as described in claim 1, characterized in that, Use randomization or the ATPG method to search for test vectors.

3. The equivalence verification method based on FPGA prototype verification as described in claim 1, characterized in that, In step S2, the circuit model C RTL C GATE C FPGA After dividing the circuit into logic cones, the logic cones of each circuit model are stored in the form of linked lists.

4. The equivalence verification method based on FPGA prototype verification as described in claim 1, characterized in that, In step S3, the circuit model C is simultaneously... RTL C GATE C FPGA The corresponding logic is used to perform equivalence verification, including: The circuit model C is respectively RTL C GATE C FPGA The outputs of the three corresponding logic cones are XORed pairwise, and the result is then ORed to output PO. Search for a test vector. If a test vector exists such that PO = 1, then the three corresponding logical cones are not equivalent; otherwise, the three corresponding logical cones are equivalent. If circuit model C RTL C GATE C FPGA If all corresponding logic cones are equivalent, then RTL, gate netlist and FPGA netlist are equivalent; otherwise, they are not equivalent.

5. The equivalence verification method based on FPGA prototype verification as described in claim 4, characterized in that, Use randomization or the ATPG method to search for test vectors.

6. An equivalence verification system based on FPGA prototype verification, characterized in that, When performing prototype verification on an FPGA, the equivalence verification method based on FPGA prototype verification as described in any one of claims 1-5 is adopted.

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