Methods, apparatuses, devices, and media for deep learning model inference

Abstract

The present disclosure provides a method, device, equipment and medium for deep learning model inference, relates to the field of artificial intelligence, and in particular to deep learning technology. The method comprises: obtaining a quantized inference model; creating a plurality of sub-streams for running on an image processing unit; determining a first matrix and a second matrix to be executed in a matrix multiplication during an inference process of the quantized inference model; splitting the first matrix and the second matrix to obtain a plurality of first matrix blocks corresponding to the first matrix and a plurality of second matrix blocks corresponding to the second matrix; transmitting the plurality of first matrix blocks and the plurality of second matrix blocks to corresponding sub-streams in the plurality of sub-streams; performing matrix multiplication on the first matrix blocks and the second matrix blocks transmitted to each of the plurality of sub-streams by using each of the plurality of sub-streams to generate a matrix block multiplication result; and combining the matrix block multiplication results generated by the plurality of sub-streams respectively to obtain a matrix multiplication result of the first matrix and the second matrix.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence, specifically to deep learning technology, and particularly to a method for deep learning model inference, an apparatus for deep learning model inference, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0003] In the field of deep learning, Transformer-type models have achieved significant breakthroughs in performance. For example, in natural language processing, the GPT-3 series (Generated Pre-trained Transformer) models, relying on hundreds of billions of corpus data and 175 billion model parameters, can generate articles that are indistinguishable from genuine ones by humans. The ERNIE-3.0 model with hundreds of billions of parameters achieves industry-leading results in multiple tasks such as article generation, question / answer generation, and corpus classification. Furthermore, in computer vision and multimodal fields, researchers have also recognized the enormous potential of large Transformer models, developing a series of models such as ViT for the precise processing of images, videos, and other information. Leveraging the superior performance of these large models, artificial intelligence technology will more intelligently replace humans in repetitive labor in various industries such as transportation, banking, agriculture, and remote sensing, thus liberating human resources.

[0004] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0005] This disclosure provides a method for deep learning model inference, an apparatus for deep learning model inference, an electronic device, a computer-readable storage medium, and a computer program product.

[0006] According to one aspect of this disclosure, a method for inference in a deep learning model is provided. The method includes: acquiring a quantized inference model; creating multiple substreams for operation on an image processing unit; during the inference process of the quantized inference model, determining a first matrix and a second matrix to be subjected to matrix multiplication; partitioning the first matrix and the second matrix to obtain multiple first matrix blocks corresponding to the first matrix and multiple second matrix blocks corresponding to the second matrix; transmitting each of the multiple first matrix blocks and each of the multiple second matrix blocks to a corresponding substream in the multiple substreams; performing matrix multiplication on the first matrix blocks and second matrix blocks transmitted to that substream using each of the multiple substreams to generate a matrix block multiplication result; and combining the matrix block multiplication results generated by each of the multiple substreams to obtain a matrix multiplication result of the first matrix and the second matrix.

[0007] According to another aspect of this disclosure, an apparatus for deep learning model inference is provided. The apparatus includes: a model acquisition unit configured to acquire a quantized inference model; a creation unit configured to create multiple substreams for operation on an image processing unit; a first determination unit configured to determine a first matrix and a second matrix to be subjected to matrix multiplication during the inference process of the quantized inference model; a segmentation unit configured to segment the first matrix and the second matrix to obtain multiple first matrix blocks corresponding to the first matrix and multiple second matrix blocks corresponding to the second matrix; a transmission unit configured to transmit each of the multiple first matrix blocks and each of the multiple second matrix blocks to a corresponding substream of the multiple substreams; a first matrix multiplication unit configured to perform matrix multiplication on the first matrix blocks and the second matrix blocks transmitted to the substream using each of the multiple substreams to generate a matrix block multiplication result; and a combination unit configured to combine the matrix block multiplication results generated by each of the multiple substreams to obtain a matrix multiplication result of the first matrix and the second matrix.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described above.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform the above-described method.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program implements the above-described method when executed by a processor.

[0011] According to one or more embodiments of this disclosure, by using a quantized inference model, the GPU memory occupied by model inference can be reduced. By decomposing the matrix multiplication in the quantized model and using multiple substreams created on the graphics processing unit (GPU) to perform matrix multiplication on the decomposed matrix blocks, the utilization of GPU resources can be improved and the inference time can be reduced.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0014] Figure 1A A schematic diagram of an exemplary system in which the various methods described herein may be implemented according to embodiments of the present disclosure is shown;

[0015] Figure 1B A schematic diagram of a text generation model according to an exemplary embodiment of the present disclosure is shown;

[0016] Figure 1C A schematic diagram of an encoder block according to an exemplary embodiment of the present disclosure is shown;

[0017] Figure 2 A flowchart is shown of a method for inference of a deep learning model according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 A flowchart is shown of a method for inference of a deep learning model according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of multi-stream inference according to an exemplary embodiment of the present disclosure is shown;

[0020] Figure 5 A flowchart illustrating the determination of a first matrix and a second matrix according to an exemplary embodiment of the present disclosure is shown;

[0021] Figure 6A schematic diagram of the inputs and outputs of an inference engine according to an exemplary embodiment of the present disclosure is shown;

[0022] Figure 7 A structural block diagram of an apparatus for deep learning model inference according to exemplary embodiments of the present disclosure is shown; and

[0023] Figure 8 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0026] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0027] The related technologies require a large amount of GPU memory resources and are very time-consuming when performing deep learning model inference.

[0028] To address the aforementioned issues, this disclosure utilizes a quantized inference model, which reduces the GPU memory consumed by model inference. Furthermore, by decomposing the matrix multiplication in the quantized model and performing matrix multiplication on the decomposed matrix blocks using multiple substreams created on the graphics processing unit (GPU), the utilization of GPU resources can be improved, and inference time can be reduced.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1AA schematic diagram of an exemplary system 100 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 1A The system 100 includes one or more client devices 101, 102, 103, 104, 105 and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105 and 106 can be configured to execute one or more applications.

[0031] In embodiments of this disclosure, server 120 may run one or more services or software applications that enable the execution of methods for deep learning model inference.

[0032] In some embodiments, server 120 may also provide other services or software applications that may include non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 101, 102, 103, 104, 105 and / or 106 under a Software as a Service (SaaS) network.

[0033] exist Figure 1A In the configuration shown, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can sequentially interact with server 120 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 100. Therefore, Figure 1A This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0034] Users can use client devices 101, 102, 103, 104, 105, and / or 106 for human-computer interaction. The client devices provide interfaces that enable users to interact with them. The client devices can also output information to the user through these interfaces. Although... Figure 1A Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0035] Client devices 101, 102, 103, 104, 105, and / or 106 may include various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various types and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices are capable of executing various applications, such as various internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and can use various communication protocols.

[0036] Network 110 can be any type of network well known to those skilled in the art, and can use any of a variety of available protocols (including but not limited to TCP / IP, SNA, IPX, etc.) to support data communication. By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0037] Server 120 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0038] The computing unit in server 120 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 120 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0039] In some implementations, server 120 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0040] In some implementations, server 120 can be a server for a distributed system or a server integrated with blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0041] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. Databases 130 may reside in various locations. For example, a data repository used by server 120 may be local to server 120, or it may be located away from server 120 and may communicate with server 120 via a network-based or dedicated connection. Databases 130 may be of different types. In some embodiments, the database used by server 120 may be a database, such as a relational database. One or more of these databases may store, update, and retrieve data from and from the database in response to commands.

[0042] In some embodiments, one or more of the databases 130 may also be used by an application to store application data. The databases used by the application may be of different types, such as key-value stores, object stores, or regular stores supported by a file system.

[0043] Figure 1AThe system 100 can be configured and operated in various ways to enable the application of the various methods and apparatus described in this disclosure.

[0044] According to one aspect of this disclosure, a method for inference in deep learning models is provided. For example... Figure 2 As shown, the method for deep learning model inference includes: step S201, obtaining a quantized inference model; step S202, creating multiple substreams for operation on an image processing unit; step S203, during the inference process of the quantized inference model, determining a first matrix and a second matrix to be multiplied; step S204, dividing the first matrix and the second matrix to obtain multiple first matrix blocks corresponding to the first matrix and multiple second matrix blocks corresponding to the second matrix; step S205, transmitting each first matrix block and each second matrix block to a corresponding substream in the multiple substreams; step S206, performing matrix multiplication on the first matrix block and the second matrix block transmitted to the substream using each substream in the multiple substreams to generate a matrix block multiplication result; and step S207, combining the matrix block multiplication results generated by each of the multiple substreams to obtain the matrix multiplication result of the first matrix and the second matrix.

[0045] Therefore, by using a quantized inference model, the GPU memory occupied by model inference can be reduced. Furthermore, by decomposing the matrix multiplication in the quantized model and using multiple substreams created on the graphics processing unit (GPU) to perform matrix multiplication on the decomposed matrix blocks, the utilization of GPU resources can be improved and the inference time can be reduced.

[0046] In some embodiments, the methods disclosed herein can be applied to deep learning models with various architectures, such as Transformer-type models. For ease of explanation of the technical concepts and means of this disclosure, this disclosure will primarily use Transformer-type models as examples; however, it is understood that the methods disclosed herein can also be applied to other deep learning models, and are not limited thereto. Furthermore, the methods disclosed herein can be applied to deep learning models in different fields, such as natural language processing, image processing, and speech processing.

[0047] Taking text generation models as an example (because text generation models have the most complex structure), we will first introduce the common Transformer class large model structure. For example... Figure 1BAs shown, the generative model consists of a multi-layer encoder and a multi-layer decoder, with each layer containing an encoder / decoder block. After the input is fed into the model, the multi-layer encoder processes the input first, then the multi-layer decoder processes the output of the multi-layer encoder, and so on iteratively, processing the output of the multi-layer decoder until the final result is obtained.

[0048] Each encoder / decoder block contains several fully connected layers, and each fully connected layer contains several trainable weight parameters. A "trillion-weight generative model" means that there are as many as one hundred billion such weights, occupying 400GB of storage space. Although the weights of the corresponding encoder and decoder blocks (i.e., the same row) are the same, because the encoder and decoder execute sequentially in time, all weights still need to be loaded into GPU memory when performing large model inference.

[0049] like Figure 1C As shown, the internal structure of each encoder block / decoder block consists of four fully connected layers and some intermediate operators. For each fully connected layer (FC) and its associated intermediate operators, this disclosure adopts a general matrix multiplication (GEMM) interface that supports the precision of quantization and employs a multi-stream optimization scheme, as will be described below.

[0050] According to some embodiments, the quantized inference model can be obtained by quantizing a deep learning inference model with a first numerical precision. The quantized inference model has a second numerical precision, which is lower than the first numerical precision. As described above, deep learning inference models (especially "large models" in fields such as natural language processing) have a large number of weight parameters, so performing model inference with high numerical precision would consume a large amount of video memory (i.e., the storage space of the graphics processing unit (GPU)). Therefore, by quantizing the deep learning inference model, the video memory occupied by the model can be significantly reduced.

[0051] According to some embodiments, the first numerical precision can be INT8, and the second numerical precision can be FP32 or FP16.

[0052] In some embodiments, the methods disclosed herein can also be optimized and accelerated using the cuBlasLt library. Current matrix multiplication on GPUs is based on parallel computation using CUDA cores and Tensor cores. CUDA cores perform numerical multiplications once per GPU clock cycle, while Tensor cores perform matrix multiplications once per GPU clock cycle. Therefore, Tensor cores have significantly higher computational power than CUDA cores, greatly increasing throughput. The IMMA function of the cuBlasLt library can leverage the technology of INT8 Tensor cores, thereby providing superior performance for INT8 matrix multiplication operations.

[0053] When using the IMMA kernel, one of the following two sets of requirements must be met:

[0054] Group 1 uses the standard data order

[0055] • All matrix pointers must be 4-byte aligned. For better performance, this should be 16 instead of 4.

[0056] • The first dimension of matrices A, B, and C must be a multiple of 4.

[0057] • Only “TN” format is supported — A must be transposed, B does not need to be transposed.

[0058] • Dimensions m and k must be multiples of 4.

[0059] Group 2 uses IMMA-specific data ordering: matrices A, C, and D use CUBLASLT_ORDER_COL32, and matrix B uses CUBLASLT_ORDER_COL32_4R2_8C (Turing or NVIDIA Ampere GPU architecture) or CUBLASLT_ORDER_COL32_2R_4R4 (NVIDIA Ampere GPU architecture).

[0060] • The leading dimensions of matrices A, B, and C must satisfy conditions specific to memory sorting.

[0061] The Matmul descriptor must specify CUBLAS_OP_T on matrix B and CUBLAS_OP_N (default) on matrices A and C.

[0062] • If CUDA_R_32I is used as the scaleType, the only supported values ​​for alpha and beta are 0 or 1.

[0063] In some embodiments, since requirement 2 requires modification of the matrix arrangement, additional development is needed, and the introduction of arrangement transformation operations will inevitably increase inference time. Therefore, it is preferable to satisfy the requirements of group 1 to save development costs and additional inference overhead. In some embodiments, automatic selection between the two requirements can also be made based on the matrix shape or hardware conditions to improve flexibility.

[0064] According to some embodiments, to further optimize performance, the kernel for GEMM calls can be automatically selected based on the shape of the matrix, thereby achieving optimal performance for different matrix shapes. The method for deep learning model inference may also include: determining the kernel for performing matrix multiplication of the first and second matrices based on their shapes. This approach can improve the utilization of GPU resources and enhance performance.

[0065] In CUDA programming, a stream is an execution queue of CUDA kernels on the GPU. The host device (usually the CPU) emits kernels that need to be executed onto the stream, and the GPU executes them in the order of the stream. CUDA allows the creation of multiple streams, and the host device can emit kernels to different streams, which execute asynchronously. However, the efficiency of asynchronous execution is also affected by the GPU's different kernel resource scheduling strategies. If kernels on a certain stream occupy nearly 100% of the GPU resources at a certain time, kernels on other streams will not be able to achieve the expected execution efficiency.

[0066] The inventors discovered in their research on the quantization inference model that some matrix multiplications with large k values ​​still cannot fully utilize all GPU resources (here, k refers to the second dimension / column number of matrix A and the first dimension / row number of matrix B in the matrix multiplication). Therefore, in step S204, the matrix can be divided along the k-dimensional plane. Then, in steps S205-S206, based on the block multiplication characteristic of the matrix, a matrix multiplication is divided into multiple matrix multiplications and emitted to multiple substreams for computation.

[0067] In one exemplary embodiment, four substreams can be pre-created on the GPU. During inference, the first matrix is ​​column-wise divided into first matrix blocks A1 and A2, and the second matrix is ​​row-wise divided into second matrix blocks B1 and B2. A1 and B1 are then sent to the first substream, A1 and B2 to the second substream, A2 and B1 to the third substream, and A2 and B2 to the fourth substream. Furthermore, matrix multiplication can be performed on the two matrix blocks sent to each substream, and the matrix block multiplication results are then sent to the main stream. Finally, the GPU's main stream can combine the four matrix block multiplication results according to the matrix multiplication principle to obtain a matrix multiplication result equivalent to directly multiplying the first and second matrices.

[0068] By splitting matrix multiplication and sending it to different substreams for computation, the utilization of GPU resources can be improved, thereby reducing inference time. It's important to note that the above approach is for quantized inference models. This is because quantized inference models have lower numerical precision, and matrix multiplication during inference will not consume all GPU resources. However, for non-quantized deep learning inference models, due to their higher numerical precision, matrix multiplication will consume a significant amount of GPU resources, resulting in high GPU utilization. Therefore, there is no need to further improve GPU utilization using multistreaming.

[0069] According to some embodiments, matrix multiplications with smaller k values ​​can be computed on the main stream, and when it is determined that segmentation is needed, the matrix is ​​segmented and emitted to the substream for computation. The number of columns in the first matrix can be greater than a preset value. For example... Figure 3 As shown, the method for deep learning model inference may further include: step S308, determining the third and fourth matrices to be multiplied during the inference process of the quantized inference model, wherein the number of columns of the third matrix is ​​not greater than a preset value; and step S309, performing matrix multiplication on the third and fourth matrices using the mainstream running on the image processing unit to obtain the matrix multiplication result of the third and fourth matrices. Figure 3 The operations of steps S301-S307 in the middle and Figure 2 Steps S201-S207 are similar and will not be described in detail here.

[0070] Since matrix splitting, sending matrix blocks to different substreams, and summarizing and combining the results from the substreams all consume resources, while matrix multiplication with low computational cost does not consume much resource, resource utilization can be improved by performing matrix multiplication with low computational cost on the main stream and splitting matrix multiplication with high computational cost into multiple substreams for execution.

[0071] Aside from matrix multiplication, other kernels can be executed on the main stream. Furthermore, due to the asynchronous nature of streams, CUDA events can be used to synchronize the main stream and substreams to ensure computational correctness.

[0072] In some embodiments, such as Figure 4As shown, kernels 1, 2, and 3 run sequentially on the main stream. After each kernel finishes running, the substreams query the main stream. After kernel 3, synchronization can be achieved via CUDA events, and matrix blocks can be emitted to the corresponding substreams. Subsequently, each substream performs matrix multiplication on the received matrix blocks. After the matrix multiplication operations on the substreams are completed, the main stream queries the operation results from each substream and can synchronize using CUDA events on each substream. This allows the operation results from each substream to be combined to obtain the matrix multiplication result. After this, the main stream can also execute kernel 4.

[0073] According to some embodiments, since quantized matrix multiplication is used, quantization and dequantization are required for the input and output of each matrix multiplication, especially when some other intermediate operators only support floating-point calculations. The method for deep learning model inference may also include dequantizing the matrix multiplication results of the first and second matrices to obtain a target result with a first numerical precision.

[0074] In some embodiments, quantization and dequantization require additional time. To optimize this time consumption, kernel fusion technology can be used, which involves fusing the quantization kernel into the kernel before the fully connected layer and the dequantization kernel into the kernel after the fully connected layer. In this way, the startup time of the quantization and dequantization kernels is eliminated, thereby bringing a speed improvement of 10% to 20% to the model.

[0075] As described above, since the encoder and decoder execute sequentially in time, when performing deep learning model inference, the encoder and decoder may load multiple duplicate weights, resulting in wasted GPU memory.

[0076] According to some embodiments, such as Figure 5 As shown, step S203, during the inference process of the quantization inference model, determining the first matrix and the second matrix to be multiplied by the matrix multiplication can include: step S501, determining the first fully connected layer to be inferred in the quantization inference model, the first fully connected layer being associated with the first matrix and including multiple first weights; and step S502, for each of the multiple first weights, in response to determining that the image processing unit's storage space does not contain the first weight, obtaining the first weight from other storage spaces and storing the first weight into the image processing unit's storage space. Thus, through the above method, it can be ensured that each weight is stored only once in the image processing unit's storage space, avoiding the additional overhead of GPU memory.

[0077] According to some embodiments, the method for deep learning model inference may further include: determining a second fully connected layer to be inferred in the quantized inference model, the second fully connected layer including a plurality of second weights that are at least partially identical to a plurality of first weights; and directly obtaining the plurality of second weights from the storage space of the image processing unit. Thus, weight sharing between different structures of the model is achieved through the above method. Weights are loaded once and used multiple times.

[0078] According to some embodiments, during the inference process of the quantization inference model, determining the first and second matrices to be performed in the matrix multiplication further includes: obtaining pointers corresponding to each of the multiple weights, whereby the pointers indicate whether the storage space of the image processing unit contains the weight corresponding to the pointer. Thus, by using pointers, it is convenient to determine whether the GPU already contains the corresponding weight.

[0079] In one exemplary embodiment, for the PaddlePaddle deep learning development platform, a scope can be used as a pointer to multiple weights. Different operation steps are performed depending on whether the scope already contains weights from the GPU. When constructing a fully connected layer, the scope pointer is passed in. If the scope does not contain GPU weights, preprocessing can be performed and the weights stored, followed by matrix multiplication. If the scope contains GPU weights, matrix multiplication can be constructed directly.

[0080] In one exemplary embodiment, when using ERNIE 3.0 model validation, a deep learning model with numerical precision of FP32 requires 420GB of GPU memory. However, by using techniques such as weight sharing and quantization, the GPU memory requirement is reduced to 133GB, saving nearly three-quarters of the GPU card space. Furthermore, by using multi-streaming and kernel fusion, the inference time can be reduced from 500ms for the FP32 precision model to 186ms, improving inference efficiency by 2.7 times.

[0081] In addition to the advantages mentioned above, the method disclosed herein is very user-friendly. For example... Figure 6 As shown, the user provides the inference engine with an inference model (e.g., a quantized inference model) and corresponding model inputs, along with related configurations, including a quantization switch (indicating whether the user-provided model is quantized), the number of GPU cards, and the number of substreams. The inference engine can execute the methods disclosed herein to generate the model's output and return it to the user. The methods disclosed herein are applicable to various tasks across different domains, such as text and image classification, generation tasks, etc., to generate text, images, classification results, etc. The methods disclosed herein are also used with various models, such as ViT, GPT, ERNIE, etc.

[0082] According to another aspect of this disclosure, an apparatus for inference in deep learning models is provided. For example... Figure 7 As shown, the apparatus 700 includes: a model acquisition unit 710 configured to acquire a quantized inference model; a creation unit 720 configured to create multiple substreams for operation on an image processing unit; a first determination unit 730 configured to determine a first matrix and a second matrix to be multiplied during the inference process of the quantized inference model; a segmentation unit 740 configured to segment the first matrix and the second matrix to obtain multiple first matrix blocks corresponding to the first matrix and multiple second matrix blocks corresponding to the second matrix; a transmission unit 750 configured to transmit each of the multiple first matrix blocks and each of the multiple second matrix blocks to a corresponding substream of the multiple substreams; a first matrix multiplication unit 760 configured to perform matrix multiplication on the first matrix blocks and the second matrix blocks transmitted to the substream using each of the multiple substreams to generate a matrix block multiplication result; and a combination unit 770 configured to combine the matrix block multiplication results generated by the multiple substreams to obtain a matrix multiplication result of the first matrix and the second matrix.

[0083] It is understandable that the operation of units 710-770 in device 700 and Figure 2 The operations of steps S201-S207 are similar and will not be described in detail here.

[0084] According to some embodiments, the number of columns in the first matrix may be greater than a preset value. The apparatus 700 may further include (not shown): a second determining unit configured to determine, during the inference process of the quantization inference model, a third matrix and a fourth matrix to be multiplied, wherein the number of columns in the third matrix is ​​not greater than a preset value; and a second matrix multiplication unit configured to perform matrix multiplication on the third and fourth matrices using a mainstream running on the image processing unit to obtain the matrix multiplication result of the third and fourth matrices.

[0085] According to some embodiments, the quantized inference model can be obtained by quantizing a deep learning inference model with a first numerical precision. The quantized inference model can have a second numerical precision lower than the first numerical precision.

[0086] According to some embodiments, the apparatus 700 may further include (not shown in the figure): an inverse quantization unit configured to inverse quantize the matrix multiplication result of the first matrix and the second matrix to obtain a target result with a first numerical precision.

[0087] According to some embodiments, the first numerical precision can be INT8, and the second numerical precision can be FP32 or FP16.

[0088] According to some embodiments, the apparatus 700 may further include (not shown in the figure): a third determining unit configured to determine a kernel for performing matrix multiplication of the first matrix and the second matrix based on the shapes of the first matrix and the second matrix.

[0089] According to some embodiments, the first determining unit may include: a determining subunit configured to determine a first fully connected layer to be inferred in a quantized inference model, the first fully connected layer being associated with a first matrix and including a plurality of first weights; and a storage subunit configured to, for each of the plurality of first weights, in response to determining that the storage space of the image processing unit does not contain the first weight, obtain the first weight from other storage spaces and store the first weight into the storage space of the image processing unit.

[0090] According to some embodiments, the apparatus 700 may further include (not shown in the figure): a fourth determining unit configured to determine a second fully connected layer to be inferred in a quantized inference model, the second fully connected layer including a plurality of second weights that are at least partially identical to a plurality of first weights; and a weight acquisition unit configured to directly acquire a plurality of second weights from the storage space of the image processing unit.

[0091] According to some embodiments, the first determining unit may further include: an acquisition subunit configured to acquire pointers corresponding to each of the plurality of weights, the pointers indicating whether the storage space of the image processing unit contains the weights corresponding to the pointers.

[0092] According to embodiments of this disclosure, an electronic device, a readable storage medium, and a computer program product are also provided.

[0093] refer to Figure 8 The present invention describes a structural block diagram of an electronic device 800 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0094] like Figure 8As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0095] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, output unit 807, storage unit 808, and communication unit 809. Input unit 806 can be any type of device capable of inputting information to device 800. Input unit 806 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of the electronic device, and can include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 807 can be any type of device capable of presenting information, and can include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 808 can include, but is not limited to, a hard disk and an optical disk. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and can include, but is not limited to, a modem, network card, infrared communication device, wireless communication transceiver, and / or chipset, such as Bluetooth. TM Devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices and / or the like.

[0096] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning network algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as methods for deep learning model inference. For example, in some embodiments, the methods for deep learning model inference can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the methods for deep learning model inference described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform methods for deep learning model inference by any other suitable means (e.g., by means of firmware).

[0097] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0099] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0100] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0101] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0102] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem, addressing the shortcomings of traditional physical hosts and VPS (Virtual Private Server, or simply "VPS") services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0103] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0104] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A method for inference in deep learning models, comprising: A quantized inference model is obtained by quantizing a deep learning inference model with a first numerical precision, and the quantized inference model has a second numerical precision lower than the first numerical precision. Create multiple substreams to run on the image processing unit; In the reasoning process of the quantization reasoning model, determining the first and second matrices to be performed in the matrix multiplication includes: Determine the first fully connected layer to be reasoned in the quantization inference model, the first fully connected layer being associated with the first matrix and including a plurality of first weights; and For each of the plurality of first weights, in response to determining that the storage space of the image processing unit does not contain the first weight, the first weight is obtained from other storage spaces and stored in the storage space of the image processing unit; The first matrix and the second matrix are divided to obtain multiple first matrix blocks corresponding to the first matrix and multiple second matrix blocks corresponding to the second matrix; Each of the plurality of first matrix blocks and each of the plurality of second matrix blocks is transmitted to the corresponding sub-stream in the plurality of sub-streams; Matrix multiplication is performed asynchronously on the first and second matrix blocks emitted to each of the plurality of sub-streams to generate matrix block multiplication results; The matrix multiplication results generated by the multiple substreams are combined using the main stream running on the image processing unit to obtain the matrix multiplication result of the first matrix and the second matrix; and The matrix multiplication result is dequantized to obtain the target result with the first numerical precision. Specifically, for matrix multiplication of the first matrix and the second matrix, the quantization kernel is fused into the kernel before the first fully connected layer, and the dequantization kernel is fused into the kernel after the first fully connected layer.

2. The method according to claim 1, wherein, If the number of columns in the first matrix is ​​greater than a preset value, the method further includes: During the reasoning process of the quantization inference model, the third and fourth matrices to be performed in the matrix multiplication are determined, wherein the number of columns in the third matrix is ​​not greater than the preset value; and The main stream running on the image processing unit performs matrix multiplication on the third matrix and the fourth matrix to obtain the matrix multiplication result of the third matrix and the fourth matrix.

3. The method according to claim 1, wherein, The first numerical precision is INT8, and the second numerical precision is FP32 or FP16.

4. The method according to claim 1, further comprising: Based on the shapes of the first matrix and the second matrix, a kernel for performing matrix multiplication of the first matrix and the second matrix is ​​determined.

5. The method according to claim 1, further comprising: Determine the second fully connected layer to be reasoned in the quantized inference model, wherein the second fully connected layer includes a plurality of second weights that are at least partially the same as the plurality of first weights; as well as The plurality of second weights are obtained directly from the storage space of the image processing unit.

6. The method according to claim 1, wherein, In the reasoning process of the quantization reasoning model, determining the first and second matrices to be performed in the matrix multiplication further includes: Obtain pointers corresponding to each of the plurality of first weights, wherein the pointers indicate whether the storage space of the image processing unit contains the first weight corresponding to the pointer.

7. An apparatus for inference in a deep learning model, comprising: The model acquisition unit is configured to acquire a quantized inference model, which is obtained by quantizing a deep learning inference model with a first numerical precision, and the quantized inference model has a second numerical precision lower than the first numerical precision. The creation unit is configured to create multiple sub-streams for running on the image processing unit; A first determining unit is configured to determine a first matrix and a second matrix to be performed in the reasoning process of the quantization reasoning model, wherein the first determining unit includes: A subunit is determined, configured to determine the first fully connected layer to be reasoned in the quantized inference model, the first fully connected layer being associated with the first matrix and including a plurality of first weights; and A storage subunit is configured to, for each of the plurality of first weights, in response to determining that the storage space of the image processing unit does not contain the first weight, retrieve the first weight from other storage spaces and store the first weight into the storage space of the image processing unit. The segmentation unit is configured to segment the first matrix and the second matrix to obtain a plurality of first matrix blocks corresponding to the first matrix and a plurality of second matrix blocks corresponding to the second matrix; The transmitting unit is configured to transmit each of the plurality of first matrix blocks and each of the plurality of second matrix blocks to a corresponding substream of the plurality of substreams; The first matrix multiplication unit is configured to asynchronously perform matrix multiplication on the first matrix block and the second matrix block emitted to the sub-stream using each of the plurality of sub-streams to generate a matrix block multiplication result; The combining unit is configured to combine the matrix block multiplication results generated by the plurality of substreams respectively using the main stream running on the image processing unit to obtain the matrix multiplication result of the first matrix and the second matrix; and The dequantization unit is configured to dequantize the matrix multiplication result to obtain the target result with the first numerical precision. Specifically, for matrix multiplication of the first matrix and the second matrix, the quantization kernel is fused into the kernel before the first fully connected layer, and the dequantization kernel is fused into the kernel after the first fully connected layer.

8. The apparatus according to claim 7, wherein, The number of columns in the first matrix is ​​greater than a preset value, and the device further includes: The second determining unit is configured to determine the third and fourth matrices to be performed in the matrix multiplication during the reasoning process of the quantization inference model, wherein the number of columns in the third matrix is ​​not greater than the preset value; and The second matrix multiplication unit is configured to perform matrix multiplication on the third matrix and the fourth matrix using the main stream running on the image processing unit to obtain the matrix multiplication result of the third matrix and the fourth matrix.

9. The apparatus according to claim 7, wherein, The first numerical precision is INT8, and the second numerical precision is FP32 or FP16.

10. The apparatus according to claim 7, further comprising: The third determining unit is configured to determine a kernel for performing matrix multiplication of the first matrix and the second matrix based on the shapes of the first matrix and the second matrix.

11. The apparatus of claim 7, further comprising: The fourth determining unit is configured to determine the second fully connected layer to be reasoned in the quantized inference model, the second fully connected layer including a plurality of second weights that are at least partially the same as the plurality of first weights; as well as The weight acquisition unit is configured to directly acquire the plurality of second weights from the storage space of the image processing unit.

12. The apparatus according to claim 7, wherein, The first determining unit further includes: The acquisition subunit is configured to acquire a pointer corresponding to each of the plurality of first weights, the pointer indicating whether the storage space of the image processing unit contains the first weight corresponding to the pointer.

13. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

15. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-6.

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