Dynamic random access memory and operating method thereof

Abstract

A dynamic random access memory (DRAM) and an operating method thereof are provided. The DRAM includes a memory cell array, a refresh counter, row disturb logic circuitry, and refresh logic circuitry. The memory cell array includes a plurality of memory cell rows. The refresh counter provides a current refresh wordline address. The row disturb logic circuitry provides a victim wordline address. The refresh logic circuitry refreshes a target row using the current refresh wordline address during a first sub-period of a tRFC for an auto-refresh operation. The refresh logic circuitry refreshes a victim row using the victim wordline address during a second sub-period of the same tRFC for row disturb protection.

Description

Technical Field

[0001] This invention relates to a memory, and more particularly to a dynamic random access memory (DRAM) and its operation method. Background Technology

[0002] Row hammer is a physical leakage problem in Dynamic Random Access Memory (DRAM). When a specific word line in DRAM is repeatedly turned on multiple times, the memory cells of adjacent word lines may lose stored data due to crosstalk or coupling effects. This interference phenomenon is called row hammer. The auto-refresh command can prevent data loss due to row hammer to some extent. The auto-refresh command scans every word line of the DRAM chip, that is, refreshes the memory cells of each word line one by one. However, refreshing all rows (all word lines) takes a considerable amount of time. In other words, for any given row, the refresh time interval between the current refresh and the next refresh is quite long and lacks flexibility. When a character line (also known as the aggressor word line) is frequently activated multiple times within a refresh interval, the storage units of adjacent character lines (also known as the victim word lines) may lose data due to frequent row interference before the automatic refresh operation is performed. How to prevent data loss due to row interference is one of the many technical challenges in this field. Summary of the Invention

[0003] This invention provides a Dynamic Random Access Memory (DRAM) and its operation method to provide row hammer protection.

[0004] In an embodiment of the present invention, the DRAM includes a memory cell array, a refresh counter, row interference logic circuitry, and refresh logic circuitry. The memory cell array includes a plurality of memory cell rows. The refresh counter provides the current refresh character line address for automatic refresh operations, wherein the current refresh character line address corresponds to a target row among these memory cell rows. The row interference logic circuitry provides the victim character line address for row interference protection, wherein the victim character line address corresponds to a victim row among these memory cell rows. The refresh logic circuitry is coupled to the refresh counter and the row interference logic circuitry to receive the current refresh character line address and the victim character line address. The refresh logic circuitry enters a row refresh cycle time based on a refresh command issued by the memory controller. Specifically, during a first sub-period of the row refresh cycle time, the refresh logic circuitry uses the current refresh character line address to refresh the target row for automatic refresh operations, and during a second sub-period of the row refresh cycle time, the refresh logic circuitry uses the victim character line address to refresh the victim row for row interference protection.

[0005] In an embodiment of the present invention, the above-described operation method includes: providing a current refresh character line address for automatic refresh operation by a refresh counter of the DRAM, wherein the current refresh character line address corresponds to a target row among a plurality of memory cell rows of the DRAM's memory cell array; providing a victim character line address for row interference protection by a row interference logic circuit of the DRAM, wherein the victim character line address corresponds to a victim row among these memory cell rows; entering a row refresh cycle time based on a refresh command issued by the memory controller; using the current refresh character line address to refresh the target row during a first sub-period of the row refresh cycle time by the refresh logic circuit of the DRAM to perform an automatic refresh operation; and using the victim character line address to refresh the victim row during a second sub-period of the row refresh cycle time to perform row interference protection.

[0006] Based on the above, the DRAM described in the embodiments of the present invention enters the row refresh cycle time based on the refresh command issued by the memory controller. The refresh logic circuit can divide a row refresh cycle time into at least a first sub-period and a second sub-period. In addition to using the current refresh character line address provided by the refresh counter to refresh the corresponding target row during the first sub-period of the row refresh cycle time, the refresh logic circuit can also use the victim character line address provided by the row interference logic circuit to refresh the corresponding victim row during the second sub-period of the same row refresh cycle time. Therefore, the DRAM can selectively (flexibly) perform row interference protection in any row refresh cycle time. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a circuit block of dynamic random access memory (DRAM) according to an embodiment of the present invention;

[0008] Figure 2 This is a timing diagram illustrating the automatic refresh operation;

[0009] Figure 3 This is a flowchart illustrating a method for operating dynamic random access memory according to an embodiment of the present invention;

[0010] Figure 4 This is a timing diagram illustrating an automatic refresh operation according to an embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures

[0012] 10: Memory controller

[0013] 100: Dynamic Random Access Memory (DRAM)

[0014] 110: Refresh Counter

[0015] 120: Row hammer logic circuit

[0016] 130: Refresh Logic Circuit

[0017] 140: Array of storage units

[0018] 210, 220, 410, 420: Row refresh cycle time

[0019] 411, 421: First sub-period

[0020] 412, 422: Second sub-period

[0021] MC: Memory cell circuit

[0022] RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, RA11, RA12, RH1, RH2, RH3, RH4: Storage cell rows

[0023] REF_CMD: Refresh command

[0024] REF_RA: Currently refreshing character line address

[0025] RH_RA: Victim character line address

[0026] S310, S320, S330, S340, S350: Steps

[0027] T1, T2, T3, T4: Time points Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0029] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0030] Figure 1 This is a circuit block diagram of a Dynamic Random Access Memory (DRAM) 100 according to an embodiment of the present invention. The memory controller 10 can control and access the DRAM 100. Figure 1 The DRAM 100 shown includes a refresh counter 110, row hammer logic circuitry 120, refresh logic circuitry 130, and a memory cell array 140. The memory cell array 140 includes multiple memory cell rows, for example... Figure 1 The storage cell rows shown are RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, RA11, and RA12. Each storage cell row RA1 to RA12 includes multiple storage cell circuits MC. This embodiment does not limit the specific implementation of the storage cell MC. For example, depending on the actual design, the storage cell circuit MC can include existing storage cell circuits or other storage cell circuits. For the sake of simplicity, the accompanying drawings are provided below. Figure 1 The word line, bit line, and other circuits / components of the storage cell array 140 are not shown.

[0031] Refresh counter 110 can provide the current refresh character line address REF_RA for automatic refresh operations. The current refresh character line address REF_RA corresponds to a target row among the memory cell rows (e.g., RA1 to RA12) of memory cell array 140. Based on the timing of scanning and refreshing these memory cell rows of memory cell array 140, refresh counter 110 can update the current refresh character line address REF_RA to point to the next memory cell row. Refresh logic circuitry 130 is coupled to refresh counter 110 to receive the current refresh character line address REF_RA.

[0032] Figure 2 This is a timing diagram illustrating the automatic refresh operation. Figure 2 The horizontal axis shown represents time. Please refer to... Figure 1 and Figure 2 Based on the refresh command REF_CMD issued by the memory controller 10, the DRAM 100 can enter the RowRefresh Cycle Time. The RowRefresh Cycle Time can be the "tRFC" specified by the DRAM standard. Each tRFC can include multiple Row Address Strobe Active Times (RAS). The Row Address Strobe Active Times can be the "tRAS" specified by the DRAM standard. The definitions of "tRFC" and "tRAS" are well known to those skilled in the art and will not be elaborated here. The number of tRAS in each tRFC can vary depending on the actual design. For example, in some embodiments, the duration of a tRFC can be 350 ns (nanoseconds), the duration of a tRAS can be 50–60 ns, and the number of tRAS in a tRFC can be 6.

[0033] Based on the refresh command REF_CMD issued by the memory controller 10, the DRAM 100 can enter the row refresh cycle time (tRFC) 210 at time point T1. During the row refresh cycle time 210, the refresh counter 110 can update the current refresh character line address REF_RA at different row address enable times (tRAS), and the refresh logic circuit 130 can refresh the target row (e.g., memory cell rows RA1 to RA6) corresponding to the current refresh character line address REF_RA at each row address enable time. After the row refresh cycle time 210 ends, the refresh logic circuit 130 can pause the automatic refresh operation. Based on another refresh command REF_CMD issued by the memory controller 10, the DRAM 100 can enter the row refresh cycle time (tRFC) 220 at time point T2. During the row refresh cycle time 220, the refresh counter 110 and the refresh logic circuit 130 can resume the automatic refresh operation. The refresh counter 110 can update the current refresh character line address REF_RA at different row address enable times (tRAS) during the row refresh cycle time 220, and the refresh logic circuit 130 can refresh the target row (e.g., memory cell rows RA7 to RA12) corresponding to the current refresh character line address REF_RA at each row address enable time (tRAS) during the row refresh cycle time 220.

[0034] Figure 3 This is a flowchart illustrating an operation method of dynamic random access memory (DRAM) according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 3 In step S310, based on the refresh command REF_CMD issued by the memory controller 10, the DRAM 100 can enter the row refresh cycle time (tRFC). The refresh logic circuit can divide a row refresh cycle time into at least a first sub-period and a second sub-period. Based on the actual design, the first sub-period may include one or more row address enable times (tRAS), and the second sub-period may include one or more row address enable times (tRAS).

[0035] In step S320, the refresh counter 110 can provide the current refresh character line address REF_RA for automatic refresh operation. The current refresh character line address REF_RA corresponds to a target row among these memory cell rows (e.g., RA1 to RA12) of the memory cell array 140. In step S330, the refresh logic circuit 130 can use the current refresh character line address REF_RA to refresh the target row during the first sub-period of the row refresh cycle time (tRFC) to perform automatic refresh operation.

[0036] In step S340, the row hammer logic circuit 120 can provide the victim character line address RH_RA for row hammer protection. The victim character line address RH_RA corresponds to a victim row among the memory cell rows (e.g., RA1 to RA12) of the memory cell array 140. This embodiment does not limit the specific implementation of the row hammer logic circuit 120. Depending on the actual design, in some embodiments, the row hammer logic circuit 120 can count the number of times each memory cell row of the memory cell array 140 is opened within a certain period. A memory cell row whose number of openings exceeds a threshold is considered an aggressor word line, and its adjacent character lines are considered victim word lines. The row hammer logic circuit 120 can use the character line address (row address) of the victim word line as the victim character line address RH_RA. In other embodiments, the row hammer logic circuit 120 can use existing row hammer algorithms or other row hammer algorithms to determine the victim character line address RH_RA.

[0037] The refresh logic circuit 130 is coupled to the row interference logic circuit 120 to receive the victim character line address RH_RA. The refresh logic circuit 130 can enter the row refresh cycle time (tRFC) based on the refresh command REF_CMD issued by the memory controller 10. During the second sub-period of the row refresh cycle time (tRFC), the refresh logic circuit 130 can use the victim character line address RH_RA to refresh the victim row for row interference protection (step S350).

[0038] Figure 4 This is a timing diagram illustrating an automatic refresh operation according to an embodiment of the present invention. Figure 4 The horizontal axis shown represents time. Please refer to... Figure 1 , Figure 3 and Figure 4 Based on the refresh command REF_CMD issued by the memory controller 10 at time T3, the refresh logic circuit 130 can enter the row refresh cycle time (tRFC) 410. The row refresh cycle time 410 may include a first sub-period 411 and a second sub-period 412. According to the actual design, the first sub-period 411 may include one or more row address enable times (tRAS), and the second sub-period 412 may include one or more row address enable times (tRAS). Similarly, based on another refresh command REF_CMD issued by the memory controller 10 at time T4, the refresh logic circuit 130 can enter the row refresh cycle time (tRFC) 420 with a first sub-period 421 and a second sub-period 422.

[0039] The refresh counter 110 updates the current refresh character line address REF_RA at different row address enable times (tRAS) during the first sub-period 411 of the row refresh cycle time (tRFC) 410 (step S320). The refresh logic circuit 130 can use the updated current refresh character line address REF_RA at each of these row address enable times (tRAS) during the first sub-period 411 to refresh the target row (e.g., memory cell rows RA1 to RA4) corresponding to the current refresh character line address REF_RA for automatic refresh operation (step S330).

[0040] The row interference logic circuit 120 updates the victim character line address RH_RA at different row address enable times (tRAS) during the second sub-period 412 of the row refresh cycle time (tRFC) 410 (step S340). The refresh logic circuit 130 can use the updated victim character line address RH_RA at each of these row address enable times (tRAS) of the second sub-period 412 to refresh the victim row corresponding to the victim character line address RH_RA (e.g., memory cell rows RH1 and RH2 in memory cell array 140) to perform row interference protection (step S350). Depending on the actual operating scenario, either memory cell row RH1 or RH2 may be one of memory cell rows RA1 to RA12, or it may be in memory cell array 140 but not shown. Figure 1 Other memory cell rows. After the row refresh cycle time 410 ends, the refresh logic circuit 130 can pause the automatic refresh operation.

[0041] During the row refresh cycle time (tRFC) 420, the refresh logic circuit 130 can resume automatic refresh operation. The refresh counter 110 updates the current refresh character line address REF_RA at different row address enable times (tRAS) of the first sub-period 421 of the row refresh cycle time 420 (step S320). In each of these row address enable times (tRAS) of the first sub-period 421, the refresh logic circuit 130 can use the updated current refresh character line address REF_RA to refresh the target row (e.g., memory cell rows RA5 to RA8) corresponding to the current refresh character line address REF_RA to perform automatic refresh operation (step S330).

[0042] The row interference logic circuit 120 updates the victim character line address RH_RA at different row address enable times (tRAS) during the second sub-period 422 of the row refresh cycle time (tRFC) 420 (step S340). The refresh logic circuit 130 can use the victim character line address RH_RA at each of these row address enable times (tRAS) of the second sub-period 422 to refresh the victim row corresponding to the victim character line address RH_RA (e.g., other memory cell rows RH3 and RH4 in the memory cell array 140) to perform row interference protection (step S350). Depending on the actual operating scenario, either memory cell row RH3 or RH4 may be one of memory cell rows RA1 to RA12, or it may be in the memory cell array 140 but not shown. Figure 1 Other storage cell rows.

[0043] In summary, the DRAM 100 described in this embodiment can enter the row refresh cycle time (tRFC) based on the refresh command REF_CMD issued by the memory controller 10. The refresh logic circuit 130 can divide a row refresh cycle time into at least a first sub-period and a second sub-period. For example, the row refresh cycle time 410 includes a first sub-period 411 and a second sub-period 412. In addition to using the current refresh character line address REF_RA provided by the refresh counter 110 to refresh the corresponding target row (e.g., memory cell rows RA1 to RA4) during the first sub-period 411 of the row refresh cycle time (tRFC), the refresh logic circuit 130 can also use the victim character line address RH_RA provided by the row interference logic circuit 120 to refresh the corresponding victim row (e.g., memory cell rows RH1 and RH2) during the second sub-period 412 of the same row refresh cycle time 410. Therefore, the DRAM 100 can selectively (flexibly) perform row interference protection in any row refresh cycle time (tRFC).

[0044] Depending on the design requirements, the refresh counter 110, the row interference logic circuit 120, and / or the refresh logic circuit 130 can be implemented in hardware, firmware, software (i.e., a program), or a combination of these three methods. For example, the refresh counter 110, the row interference logic circuit 120, and / or the refresh logic circuit 130 can be implemented as logic circuits on an integrated circuit. The related functions of the refresh counter 110, the row interference logic circuit 120, and / or the refresh logic circuit 130 can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. The functions of the refresh counter 110, the row interference logic circuit 120, and / or the refresh logic circuit 130 can be implemented in various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dynamic random access memory, characterized in that, The dynamic random access memory includes: An array of storage cells, comprising multiple rows of storage cells; A refresh counter is used to provide the current refresh character line address for the automatic refresh operation, wherein the current refresh character line address corresponds to the target row among the plurality of memory cell rows; Row interference logic circuitry for providing victim character line addresses for row interference protection, wherein the victim character line addresses correspond to victim rows in the plurality of memory cell rows; and A refresh logic circuit, coupled to the refresh counter and the row interference logic circuit, receives the current refresh character line address and the victim character line address. It enters a row refresh cycle time based on a refresh command issued by the memory controller. During a first sub-period of the row refresh cycle time, the refresh logic circuit uses the current refresh character line address to refresh the target row for the automatic refresh operation. During a second sub-period of the row refresh cycle time, the refresh logic circuit uses the victim character line address to refresh the victim row for the row interference protection. The first sub-period of the row refresh cycle time includes multiple row address activation times. The refresh counter updates the current refresh character line address during each of the multiple row address activation times, and the refresh logic circuit refreshes the target row corresponding to the current refresh character line address at each of the multiple row address activation times.

2. The dynamic random access memory according to claim 1, characterized in that, The row refresh cycle time is the tRFC specified by the Dynamic Random Access Memory Standard.

3. A dynamic random access memory, characterized in that, The dynamic random access memory includes: An array of storage cells, comprising multiple rows of storage cells; A refresh counter is used to provide the current refresh character line address for the automatic refresh operation, wherein the current refresh character line address corresponds to the target row among the plurality of memory cell rows; Row interference logic circuitry for providing victim character line addresses for row interference protection, wherein the victim character line addresses correspond to victim rows in the plurality of memory cell rows; and A refresh logic circuit, coupled to the refresh counter and the row interference logic circuit, receives the current refresh character line address and the victim character line address. It enters a row refresh cycle time based on a refresh command issued by the memory controller. The refresh logic circuit uses the current refresh character line address to refresh the target row during a first sub-period of the row refresh cycle time to perform the automatic refresh operation. During a second sub-period of the row refresh cycle time, the refresh logic circuit uses the victim character line address to refresh the victim row to perform the row interference protection. The second sub-period of the row refresh cycle time includes at least one row address activation time. The row interference logic circuit updates the victim character line address during the at least one row address activation time, and the refresh logic circuit refreshes the victim row corresponding to the victim character line address at each of the at least one row address activation times.

4. The dynamic random access memory according to claim 3, characterized in that, The row address enable time is the tRAS specified by the Dynamic Random Access Memory Standard.

5. A method for operating dynamic random access memory, characterized in that, The operation method includes: The current refresh character line address for the automatic refresh operation is provided by the refresh counter of the dynamic random access memory, wherein the current refresh character line address corresponds to the target row in a plurality of storage cell rows of the storage cell array of the dynamic random access memory; The row interference logic circuit of the dynamic random access memory provides the victim character line address for row interference protection, wherein the victim character line address corresponds to the victim row in the plurality of memory cell rows; The row refresh cycle time is entered based on the refresh command issued by the memory controller; The refresh logic circuit of the dynamic random access memory uses the current refresh character line address to refresh the target row during the first sub-period of the row refresh cycle time to perform the automatic refresh operation; and The refresh logic circuit uses the victim character line address to refresh the victim row during the second sub-period of the row refresh cycle time to perform the row interference protection. The first sub-period of the row refresh cycle time includes multiple row address enable times, and the operation method further includes: The refresh counter updates the current refresh character line address at the activation time of the plurality of line addresses; and The refresh logic circuit refreshes the target row corresponding to the currently refreshed character line address at each of the plurality of row address activation times.

6. The operating method according to claim 5, characterized in that, The row refresh cycle time is the tRFC specified by the Dynamic Random Access Memory Standard.

7. A method for operating dynamic random access memory, characterized in that, The operation method includes: The current refresh character line address for the automatic refresh operation is provided by the refresh counter of the dynamic random access memory, wherein the current refresh character line address corresponds to the target row in a plurality of storage cell rows of the storage cell array of the dynamic random access memory; The row interference logic circuit of the dynamic random access memory provides the victim character line address for row interference protection, wherein the victim character line address corresponds to the victim row in the plurality of memory cell rows; The row refresh cycle time is entered based on the refresh command issued by the memory controller; The refresh logic circuit of the dynamic random access memory uses the current refresh character line address to refresh the target row during the first sub-period of the row refresh cycle time to perform the automatic refresh operation; and The refresh logic circuit uses the victim character line address to refresh the victim row during the second sub-period of the row refresh cycle time to perform the row interference protection. The second sub-period of the row refresh cycle time includes at least one row address enable time, and the operation method further includes: The victim character line address is updated by the line interference logic circuit at the at least one line address activation time; and The refresh logic circuit refreshes the victim row corresponding to the victim character line address at each of the at least one row address activation times.

8. The operating method according to claim 7, characterized in that, The row address enable time is the tRAS specified by the Dynamic Random Access Memory Standard.

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