Methods for manufacturing semiconductor devices

Abstract

This disclosure relates to a method of manufacturing a semiconductor device, comprising the steps of: forming a first via surrounded by a liner in a first semiconductor substrate; making a first recess in the semiconductor substrate to expose a first portion of the liner covering an end of the first via; and forming a first diffusion barrier layer covering the first recess in the first semiconductor substrate and exposing a second portion of the liner. The method further comprises the steps of: removing the second portion of the liner and making a second recess in the first diffusion barrier layer. The method further comprises the steps of: forming a second diffusion barrier layer covering the second recess in the first diffusion barrier layer and the top of the liner with the second portion removed, and exposing the top surface of the end of the first via.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor technology, and more specifically to methods for manufacturing semiconductor devices including through-holes. Background Technology

[0002] Semiconductor devices are used as components in a wide variety of electronic applications. They can be used in personal computers, mobile phones, cameras, and more. Various processes are employed to manufacture semiconductor devices. These processes can include depositing conductive, dielectric, or insulating layers on a semiconductor substrate or wafer, and patterning these layers to form circuit components. Furthermore, the processes can include separating a semiconductor substrate with integrated circuit elements into individual dies, and packaging those individual dies.

[0003] As the required integration density of semiconductor devices increases, three-dimensional (3D) semiconductor devices are being developed. 3D semiconductor devices can be configured such that one semiconductor device is stacked on top of another. 3D semiconductor devices may require a smaller form factor. The stacked semiconductor devices can be electrically and signal-connected to each other via interconnect structures including through-holes. Summary of the Invention

[0004] A method for manufacturing a semiconductor device according to this disclosure includes the steps of: forming a first through-hole surrounded by a liner in a first semiconductor substrate; making a first recess in the semiconductor substrate to expose a first portion of the liner covering an end of the first through-hole; and forming a first diffusion barrier layer covering the first recess in the first semiconductor substrate and exposing a second portion of the liner. The method further includes the steps of: removing the second portion of the liner and making a second recess in the first diffusion barrier layer. The method further includes the steps of: forming a second diffusion barrier layer covering the second recess in the first diffusion barrier layer and the top of the liner with the second portion removed, and exposing the top surface of the end of the first through-hole. Attached Figure Description

[0005] Figures 1 to 14 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0006] Figure 15 This is a block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 16 This is a block diagram illustrating an electronic system including a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0008] The terms used herein may correspond to words chosen with regard to their function in the presented embodiments, and the meaning of the terms may be interpreted differently by one of ordinary skill in the art to which the embodiments pertain. Where detailed definitions are provided, these terms may be interpreted according to those definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0009] It should be understood that although the terms “first” and “second,” “side,” “top” and “bottom or lower” may be used herein to describe various devices, these devices should not be limited by these terms. These terms are used only to distinguish one device from another, and not to indicate a particular sequence or number of devices.

[0010] Semiconductor devices can include semiconductor substrates or structures in which multiple semiconductor substrates are stacked. A semiconductor substrate can refer to a semiconductor package structure that encapsulates a structure in which semiconductor substrates are stacked. A semiconductor substrate can refer to a semiconductor wafer, semiconductor die, or semiconductor chip in which electronic components and devices are integrated. A semiconductor chip can refer to a memory chip that integrates memory integrated circuits such as dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), or phase-change random access memory (PCRAM), wherein logic circuitry is integrated in the semiconductor substrate, or a logic die or ASIC chip, or a processor such as an application processor (AP), graphics processing unit (GPU), central processing unit (CPU), or system-on-a-chip (SoC). Semiconductor devices can be used in information and communication systems such as mobile phones, biotechnology or healthcare-related electronic systems, or wearable electronic systems. Semiconductor devices are suitable for the Internet of Things (IoT).

[0011] Throughout this specification, the same reference numerals refer to the same devices. Although a reference numeral may not be mentioned or described with reference to one drawing, it may be mentioned or described with reference to another drawing. Furthermore, even if a reference numeral is not shown in one drawing, it may be shown in another.

[0012] Figures 1 to 14 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 1This is a schematic cross-sectional view showing the process steps of forming an opening 101 in a first semiconductor substrate 100 of a semiconductor device according to an embodiment of the present disclosure.

[0014] Reference Figure 1 The first semiconductor substrate 100 may include a semiconductor material such as silicon (Si). The first semiconductor substrate 100 may be a substrate including an initial first surface 100B and a second surface 100F. The initial first surface 100B and the second surface 100F may be opposing surfaces. The initial first surface 100B may be the back side of the first semiconductor substrate 100, and the second surface 100F may be the front side of the first semiconductor substrate 100. The second surface 100F of the first semiconductor substrate 100 may include an active surface on which integrated circuit elements (not shown) are integrated. The integrated circuit elements may include memory devices such as DRAM devices or NAND devices. The initial first surface 100B of the first semiconductor substrate 100 may be a surface on which no integrated circuit elements are integrated.

[0015] An opening 101 may be formed in a second surface 100F of a first semiconductor substrate 100. The opening 101 may be formed as a recess extending from the second surface 100F of the first semiconductor substrate 100 toward an initial first surface 100B. The opening 101 of the recess may not extend to the initial first surface 100B of the first semiconductor substrate 100, such that the bottom of the opening 101 may be spaced apart from the initial first surface 100B of the first semiconductor substrate 100. The opening 101 may be formed by forming an etching mask (not shown) on the second surface 100F of the first semiconductor substrate 100 and removing the area of ​​the first semiconductor substrate 100 exposed by the etching mask. The process of forming the opening 101 may precede the process of integrating integrated circuit elements into the second surface 100F of the first semiconductor substrate 100.

[0016] Figure 2 This is a schematic cross-sectional view illustrating the process steps of forming a first via 200 in an opening 101 of a semiconductor device according to an embodiment of the present disclosure.

[0017] Reference Figure 2 A liner 300 may be formed in an opening 101 formed in the first semiconductor substrate 100. The liner 300 may be formed as a layer extending to conformally cover the sidewalls and bottom of the opening 101. The liner 300 may be formed as a recessed shape or a nested shape having a shape that follows the shape of the opening 101. A side barrier 220 may be formed to cover the liner 300. The side barrier 220 may be formed as a layer that conformally extends along the shape of the liner 300 or the opening 101. The side barrier 220 may be formed as a recessed shape or a nested shape.

[0018] The via body 210 can be formed to cover the side barrier portion 220 and substantially fill and bury the opening 101. The side barrier portion 220 can be formed as a layer covering the sides and top of the via body 210. The side barrier portion 220 can be formed as a layer extending along the interface between the via body 210 and the bushing 300. The bushing 300 can be formed as a layer extending along the interface between the first via 200 and the first semiconductor substrate 100. The bushing 300 can be formed as a layer extending along the interface between the side barrier portion 220 of the first via 200 and the first semiconductor substrate 100. The first via 200 can be formed in a shape substantially surrounded by the bushing 300.

[0019] A first via 200 can be introduced as a vertical connection member embedded in the first semiconductor substrate 100. The first via 200 may include a conductive material. The first via 200 may be introduced as, for example, a through-silicon via (TSV) vertical connection member. The first via 200 may include copper (Cu), which is a metallic material with lower resistivity than aluminum (Al) or conductive polycrystalline silicon.

[0020] The first via 200 may include a via body 210 and a side barrier 220. The via body 210 may be formed into a cylindrical or plug-shaped shape that substantially comprises copper (Cu). The side barrier 220 may be introduced as a layer to reduce or substantially prevent the diffusion of copper (Cu) ions from the via body 210 toward the semiconductor substrate 100. The side barrier 220 can prevent the diffusion of copper (Cu) ions, thereby reducing or substantially preventing the diffusion of copper (Cu) or copper ions constituting the via body 210 into the first semiconductor substrate 100 and contaminating the first semiconductor substrate 100. The side barrier 220 may be formed of a diffusion barrier material that prevents the diffusion of copper (Cu) ions. The side barrier 220 may include a tantalum (Ta) layer or a tantalum nitride (TaN) layer. The side barrier 220 may include a double layer of tantalum layer and tantalum nitride layer. The tantalum layer may be disposed between the via body 210 and the tantalum nitride layer.

[0021] A liner 300 may be formed at the interface between the side barrier portion 220 and the first semiconductor substrate 100. The liner 300 may be introduced as an insulating layer to electrically isolate the side barrier portion 220 and the first semiconductor substrate 100. The liner 300 may be introduced as an insulating layer to electrically isolate the first via 200 and the first semiconductor substrate 100. The liner 300 may be introduced as a buffer layer to alleviate or reduce stress that may be present between the first via 200 and the first semiconductor substrate 100. The liner 300 may include a silicon dioxide (SiO2) layer, which can be used as a stress buffer. The silicon dioxide (SiO2) layer may include silicon oxide, such as tetraethyl orthosilicate (TEOS).

[0022] Figure 3 This is a schematic cross-sectional view illustrating the process steps for forming the interconnect layer 420 of a semiconductor device according to an embodiment of the present disclosure.

[0023] Reference Figure 3 A multilevel interconnect structure 400 may be further formed beneath the second surface 100F of the first semiconductor substrate 100. A second conductive bump 520 and a fourth diffusion barrier layer 510 may be formed beneath the multilevel interconnect structure 400. The descriptions of "second" or "fourth" are for distinguishing elements and should not be construed as specifying the order of elements. The multilevel interconnect structure 400 may include an interconnect layer 420 electrically connected to the first via 200 and an insulating layer 410 insulating the interconnect layer 420. The multilevel interconnect structure 400 may include multiple interconnect layers 420. The interconnect layers 420 may include conductive patterns located at different levels. The interconnect layers 420 may electrically connect the first via 200 to the second conductive bump 520.

[0024] A second conductive bump 520 can be introduced as a connection member to electrically connect the first semiconductor substrate 100 or the first via 200 to an external device or other semiconductor substrate. A fourth diffusion barrier layer 510 may include a passivation layer covering and protecting the multilevel interconnect structure 400. The second conductive bump 520 can be electrically connected to an integrated circuit element integrated in the first semiconductor substrate 100 via the interconnect layer 420 of the multilevel interconnect structure 400. The second conductive bump 520 may include a metal material substantially the same as the metal material constituting the first via 200 or via body 210. The second conductive bump 520 may substantially include copper (Cu). The fourth diffusion barrier layer 510 may include a diffusion barrier material. The diffusion barrier material may include silicon nitride (Si3N4), which can substantially prevent the copper (Cu) constituting the second conductive bump 520 from undesirably diffusing from the second conductive bump 520.

[0025] Figure 4 This is a schematic cross-sectional view showing the process steps of performing a first-recessing (601) on a first semiconductor substrate 100 of a semiconductor device according to an embodiment of the present disclosure.

[0026] Reference Figure 4The first semiconductor substrate 100 can be recessed (601) from the initial first surface 100B. Since a portion of the first semiconductor substrate 100 is selectively removed through the first recess, the thickness of the first semiconductor substrate 100 can be reduced. Because the first semiconductor substrate 100 is first recessed (601), the first recessed first surface 100B-1 can be formed. The first semiconductor substrate 100 can be first recessed (601) by a dry etching process. The dry etching process can be performed by selectively removing silicon (Si) that may constitute the first semiconductor substrate 100.

[0027] In the first recess (601), a portion of the first semiconductor substrate 100 can be removed such that the end portion 200E of the first via 200 protrudes from the first surface 100B-1 of the first recess of the first semiconductor substrate 100. The end portion 200E of the first via 200 can be a portion of the first via 200 that is closer to the first surface 100B or the first surface 100B-1 of the first recess of the first semiconductor substrate 100 than to the second surface 100F. The end portion 200E of the first via 200 can protrude from the first surface 100B-1 of the first recess of the first semiconductor substrate 100 while being covered by the liner 300. In the first recess (601), a portion of the first semiconductor substrate 100 can be removed to expose a first portion 300S-1 of the liner 300, which is the portion covering the end portion 200E of the first via 200. The first portion 300S-1 of the liner 300 may be the side and top portion of the end 200E of the liner 300 that covers the first through hole 200 and protrudes to the outside of the first recessed first surface 100B-1 of the first semiconductor substrate 100.

[0028] Refer to together Figure 4 and Figure 3 Before performing the first recess (601), the process steps of forming an interconnect layer 420, an insulating layer 410, a second conductive bump 520 and a fourth diffusion barrier layer 510 on a second surface 100F opposite to the initial first surface 100B of the first recess (601) of the first semiconductor substrate 100 can be performed in advance.

[0029] Figure 5 This is a schematic cross-sectional view illustrating the process steps for forming a first diffusion barrier layer 710 of a semiconductor device according to an embodiment of the present disclosure.

[0030] Reference Figure 5 The first diffusion barrier layer 710 can be formed to cover the first recessed first semiconductor substrate 100 and expose the second portion 300S-2 of the substrate 300. The first diffusion barrier layer 710 can be formed such that the first portion of the substrate 300 ( Figure 4The first via 200 (300S-1) is partially covered, and a portion of the end 200E of the first via 200 protrudes from the surface 710T-1 of the first diffusion barrier layer 710, while being covered by the second portion 300S-2 of the liner. The second portion 300S-2 of the liner 300 exposed through the first diffusion barrier layer 710 may be a part of the first portion 300S-1 of the liner 300. The first diffusion barrier layer 710 may include a diffusion barrier material capable of substantially preventing the diffusion of copper (Cu) or copper (Cu) ions constituting the first via 200, via body 210, or second conductive bump 520. The first diffusion barrier layer 710 may include a dielectric material capable of more firmly preventing the diffusion of copper (Cu) ions than the silicon oxide constituting the liner 300. The first diffusion barrier layer 710 may include a silicon nitride layer.

[0031] Figures 6 to 8 It shows the formation Figure 5 A schematic cross-sectional view showing the detailed process steps of the first diffusion barrier layer 710 in the process.

[0032] Reference Figure 6 The initial first diffusion barrier layer 710-1, extending to the end 200E covering the first via 200, can be formed on the first recessed first surface 100B-1 of the first semiconductor substrate 100. The first portion of the cover substrate can be formed by depositing silicon nitride on the first recessed first surface 100B-1 of the first semiconductor substrate 100. Figure 4 The initial first diffusion barrier layer 710-1 in the 300S-1) of the middle.

[0033] Reference Figure 6 and Figure 7 The initial first diffusion barrier layer 710-1 can be planarized. A chemical mechanical polishing (CMP) process can be performed on the initial first diffusion barrier layer 710-1 to form a planarized first diffusion barrier layer 710-2. A CMP process can be performed on the initial first diffusion barrier layer 710-1 to expose a portion of the liner 300 covering the end 200E of the first via 200. The CMP process can be performed to stop polishing at the liner 300. When a portion of the liner 300 is exposed as the planarized surface 710T-2 of the first diffusion barrier layer 710-2, the planarization process can be performed to stop the CMP process.

[0034] Reference Figure 8 and Figure 5 The planarized first diffusion barrier layer 710-2 can be recessed by a third recess (602). The third recess (602) and the first recess ( Figure 4The description in 601) is used to distinguish components and is not to be interpreted as a description for specifying the process sequence. The first diffusion barrier layer 710, which exposes the second portion 300S-2 of the liner 300, can be formed by making a third recess (602) in the planarized first diffusion barrier layer 710-2.

[0035] Figure 9 This is a schematic cross-sectional view showing the process steps of removing a portion 301 of the liner 300 of the semiconductor device (603) according to an embodiment of the present disclosure.

[0036] Reference Figure 9 The process step of removing (603) the portion 301 of the liner 300 surrounding the end 200E of the first via 200 can be performed. When the portion 301 of the liner 300 surrounding the end 200E of the first via 200 is removed, the liner 300 can be confined to the portion between the first semiconductor substrate 100 and the first via 200, and the portion between the first diffusion barrier layer 710 and the first via 200. Therefore, a portion of the side and a portion of the top of the end 200E of the first via 200 can be exposed to the outside of the remaining liner 300. The side barrier portion 220 can remain extended to cover and surround the via body 210 of the first via 200.

[0037] The selectively removed portion 301 of the liner 300 may include a second portion of the liner 300. Figure 5 (300S-2 in the example). Figure 5 As shown, because the second portion 300S-2 of the substrate 300 can protrude and be exposed from the surface 710T-1 of the first diffusion barrier layer 710, the second portion 300S-2 of the substrate 300 can be exposed to the etchant used in the removal (603) process step for etching and removal. The process step of removing (603) portion 301 of the substrate 300 or the second portion 300S-2 of the substrate 300 may include a wet etching process. The wet etching process may be performed as a process for selectively removing the silicon oxide constituting the substrate 300.

[0038] When the portion 301 of the liner 300 surrounding the end 200E of the first through-hole 200 is removed by wet etching, a recessed depression 301D can be introduced or created between the first diffusion barrier layer 710 and the side portion of the end 200E of the first through-hole 200. The depression 301D can be formed as a recessed trench shape in the surface 710T-1 of the first diffusion barrier layer 710. In the process of completely removing the portion 301 of the liner 300 surrounding the end 200E of the first through-hole 200 by wet etching, the liner 300 can be over-etched. Therefore, the recessed depression 301D can be created.

[0039] In the process of depositing another material layer or another diffusion barrier layer on the first diffusion barrier layer 710, the material may not fill the recessed depression 301D, thus potentially creating voids. Such voids can become a detrimental factor to the semiconductor device. Copper (Cu) diffusion can occur through these voids, making them a potential source of contamination for the first semiconductor substrate 100.

[0040] Figure 10 This is a schematic cross-sectional view showing the process steps of making a second recess (604) in the first diffusion barrier layer 710 of a semiconductor device according to an embodiment of the present disclosure.

[0041] Reference Figure 10 The first diffusion barrier layer 710 can be recessed (604). The first diffusion barrier layer 710 can be recessed (604) to have a second recessed surface 710T-3, the height of which is lower than the height of the surface 710T-1 before the second recess (604). In the second recess (604), a portion of the first diffusion barrier layer 710 can be etched and removed, resulting in a recess ( Figure 9 The first diffusion barrier layer 710 can be further recessed (604) so ​​that a portion of the liner 300 (310D) is removed. Figure 9 301 in the middle) or the second part of the liner 300 ( Figure 5 While 300S-2 is removed, the top 300T of the liner 300 is retained. Therefore, the top 300T of the liner 300 protrudes from the second recessed surface 710T-3 of the first diffusion barrier layer 710R. As described above, the recess 301D can be removed by making a second recess (604) in the first diffusion barrier layer 710.

[0042] Figure 11 and Figure 12 This is a schematic cross-sectional view illustrating the process steps for forming a second diffusion barrier layer 720R of a semiconductor device according to an embodiment of the present disclosure. Figure 11 The steps for forming the initial second diffusion barrier layer 720 of the semiconductor device are shown. Figure 12 It shows how to make Figure 11 The initial second diffusion barrier layer 720 is planarized.

[0043] Reference Figure 11 An initial second diffusion barrier layer 720 can be formed on the first diffusion barrier layer 710R to cover the top 300T of the liner 300 and the end 200E of the first through-hole 200. When a portion of the liner 300 ( Figure 9 301) or Part 2 ( Figure 5When 300S-2) is removed, the remaining top 300T of the liner 300 can be exposed over the first diffusion barrier layer 710R, and the end 200E of the first through hole 200 can be partially exposed. The initial second diffusion barrier layer 720 can extend to cover the exposed top 300T of the liner 300 and the exposed portion of the end 200E of the first through hole 200.

[0044] Reference Figure 12 The initial second diffusion barrier layer 720 can be planarized (605) to form a planarized second diffusion barrier layer 720R. Planarization (605) can be performed such that the top surface 200E-T of the end of the first via 200 is exposed to the planarized surface 720T of the planarized second diffusion barrier layer 720R. Planarization (605) can be performed to remove a portion of the side barrier portion 220, such that the top surface of the via body 210 is exposed to the top surface 200E-T of the end 200E of the first via 200.

[0045] The second diffusion barrier layer 720R can be formed to cover and seal the top 300T of the substrate 300. The second diffusion barrier layer 720R can extend to block the space between the top 300T of the substrate 300 and the top surface 200E-T of the end 200E of the first via 200. The top 300T of the substrate 300 and the top surface 200E-T of the end 200E of the first via 200 are blocked by the second diffusion barrier layer 720R, thereby the second diffusion barrier layer 720R can substantially prevent copper (Cu) ions from diffusing from the top surface 200E-T of the end 200E of the first via 200 or the top surface of the via body 210 into the substrate 300. Therefore, the first semiconductor substrate 100 can be substantially prevented from being contaminated by copper (Cu) ions.

[0046] The second diffusion barrier layer 720R may include a dielectric material or a diffusion barrier material substantially the same as that of the first diffusion barrier layer 710R. The second diffusion barrier layer 720R may include a dielectric material different from the dielectric material constituting the substrate 300. The substrate 300 may include silicon oxide, but the second diffusion barrier layer 720R may include silicon nitride.

[0047] The first semiconductor device 10 can be referenced above. Figures 1 to 12The process steps described are used to implement this. The first semiconductor device 10 may include a first via 200 that substantially penetrates the first semiconductor substrate 100 and a second diffusion barrier layer 720R that exposes the top surface 200E-T of the end portion 200E of the first via 200. The first semiconductor device 10 may also include a first diffusion barrier layer 710R together with the second diffusion barrier layer 720R. The composite layer structure of the first diffusion barrier layer 710R and the second diffusion barrier layer 720R can substantially prevent copper (Cu) diffusion or copper (Cu) ion diffusion into the substrate 300, thereby preventing contamination of the first semiconductor substrate 100. Thus, the composite layer structure of the first diffusion barrier layer 710R and the second diffusion barrier layer 720R can prevent the diffusion of copper (Cu) ions, thereby allowing the first via 200 to be formed on the first semiconductor substrate 100 with a structure that exposes the top surface 200E-T of the end portion 200E of the first via 200 to the surface 720T of the second diffusion barrier layer 720R. The composite layer structure of the first diffusion barrier layer 710R and the second diffusion barrier layer 720R can prevent the diffusion of copper (Cu) ions, thereby eliminating the need to introduce additional structures (such as additional conductive pads) on the top surface 200E-T of the end 200E of the first via 200.

[0048] Figure 13 and Figure 14 This is a schematic cross-sectional view illustrating the process steps of directly bonding a second semiconductor device 20 to a first semiconductor device 10 to form a semiconductor device 30 according to an embodiment of the present disclosure.

[0049] Reference Figure 13 The second semiconductor device 20 can be directly bonded to the first semiconductor device 10 to realize a semiconductor device 30 wherein the second semiconductor device 20 is stacked on the first semiconductor device 10. The second semiconductor device 20 can be configured in substantially the same manner as the first semiconductor device 10. The second semiconductor device 20 may include a second semiconductor substrate 2100, a second via 2200, a first conductive bump 2520, and a third diffusion barrier layer 2510. The second semiconductor substrate 2100 of the second semiconductor device 20 may have a configuration substantially the same as that of the first semiconductor substrate 100 of the first semiconductor device 10.

[0050] The second via 2200 of the second semiconductor device 20 may have substantially the same configuration as the first via 200 of the first semiconductor device 10. The second semiconductor device 20 may also include the second via 2200, and the second via 2200 may substantially penetrate the second semiconductor substrate 2100. The second via 2200 may be electrically connected to the first conductive bump 2520.

[0051] The first conductive bump 2520 and the third diffusion barrier layer 2510 of the second semiconductor device 20 can be connected to the second conductive bump of the first semiconductor device 10. Figure 12 520 in the middle) and the fourth diffusion barrier layer ( Figure 12 The first conductive bump 2520 has essentially the same configuration as the second conductive bump (510). Figure 12 520 in the text includes substantially the same metallic material. This metallic material may include copper (Cu). The third diffusion barrier layer 2510 may be compatible with the fourth diffusion barrier layer (…). Figure 12 510 in the middle is formed of substantially the same dielectric material, and may also be formed of substantially the same dielectric material as the second diffusion barrier layer 720R.

[0052] The first semiconductor device 10 can be referenced Figures 1 to 12 The described process steps are formed, and the second semiconductor device 20 can also be formed by referring to... Figures 1 to 12 The described process steps are formed. When a first conductive bump 2520 and a third diffusion barrier layer 2510 are formed in a second semiconductor substrate 2100 and the first conductive bump 2520 is directly bonded to the top surface 200E-T of the end 200E of the first via 200 of the first semiconductor device 10, a process of directly bonding (800) the third diffusion barrier layer 2510 to the surface 720T of the second diffusion barrier layer 720R of the first semiconductor device 10 can be performed. Therefore, as Figure 14 As shown, a semiconductor device 30 in which the second semiconductor device 20 is directly bonded to the first semiconductor device 10 can be formed.

[0053] Reference Figure 14 Each of the first semiconductor device 10 and the second semiconductor device 20 may be in the form of a wafer, such that the semiconductor device 30 may be in the form in which the wafers are stacked at the wafer level. Alternatively, each of the first semiconductor device 10 and the second semiconductor device 20 may be in the form of an individual semiconductor die separated from the semiconductor wafer, such that the semiconductor device 30 may be in the form in which the semiconductor dies are stacked.

[0054] The second semiconductor device 20 can be directly bonded to the first semiconductor device 10. The second semiconductor device 20 and the first semiconductor device 10 can be joined without introducing another bonding member or additional connecting member between them. Connecting members such as solder balls or solder bumps do not need to be inserted between the second semiconductor device 20 and the first semiconductor device 10. No additional organic adhesive layer needs to be inserted between the second semiconductor device 20 and the first semiconductor device 10. The second semiconductor device 20 and the first semiconductor device 10 can be bonded to each other while their facing surfaces are in contact or close proximity. No additional adhesive material or underfill material needs to be introduced into the bonding interface where the second semiconductor device 20 is directly bonded to the first semiconductor device 10. The direct bonding of the first semiconductor device 10 and the second semiconductor device 20 as described above can indicate a hybrid bonding of semiconductor devices 10 and 20.

[0055] In semiconductor device 30, a portion of the surface 720T of the second diffusion barrier layer 720R of the first semiconductor device 10 can contact the first conductive bump 2520 of the second semiconductor device 20. When the width of the first conductive bump 2520 is wider than the width of the first via 200, or when the first conductive bump 2520 is partially misaligned with the first via 200, a portion of the first conductive bump 2520 can overlap and contact a portion of the surface 720T of the second diffusion barrier layer 720R. The second diffusion barrier layer 720R is formed of a diffusion barrier material that prevents the diffusion of copper (Cu) or copper ions, such that even if a portion of the first conductive bump 2520 contacts the surface 720T of the second diffusion barrier layer 720R, copper (Cu) or copper (Cu) ions are substantially difficult to diffuse into the second diffusion barrier layer 720R. Because the second diffusion barrier layer 720R substantially blocks the diffusion of copper (Cu) or copper ions from the first conductive bump 2520, it can substantially prevent the diffusion of copper (Cu) or copper ions from the first conductive bump 2520 into the first semiconductor device 10. Because the second diffusion barrier layer 720R covers the second portion where the substrate has been removed (… Figure 5 The top 300T of the liner 300 (300S-2) and the first conductive bump 2520 are separated from the top 300T of the liner 300, so that copper (Cu) ions can be substantially blocked from diffusing from the first conductive bump 2520 to the liner 300 by the second diffusion barrier layer 720R.

[0056] Figure 15This is a block diagram illustrating an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment of the present disclosure. The memory card 7800 includes a memory device 7810, such as a non-volatile memory device, and a memory controller 7820. The memory device 7810 and the memory controller 7820 can store data or read out stored data. At least one of the memory device 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment of the present disclosure.

[0057] The memory device 7810 may be a non-volatile memory device employing the techniques of embodiments of the present disclosure. The memory controller 7820 may control the memory device 7810 such that stored data or stored data is read in response to a read / write request from the host 7830.

[0058] Figure 16 This is a block diagram illustrating an electronic system 8710 including at least one semiconductor package according to an embodiment of the present disclosure. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory device 8713. The controller 8711, the input / output device 8712, and the memory device 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0059] In an embodiment, controller 8711 may include one or more of a microprocessor, digital signal processor, microcontroller, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory device 8713 may include at least one semiconductor package according to embodiments of the present disclosure. Input / output device 8712 may include at least one selected from a keypad, keyboard, display device, touchscreen, etc. Memory device 8713 is a means for storing data. Memory device 8713 may store commands and / or data, etc., to be executed by controller 8711.

[0060] The memory device 8713 can be a volatile memory device such as a DRAM device or a non-volatile memory device such as a flash memory device. For example, flash memory can be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory can constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

[0061] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0062] The electronic system 8710 can be implemented as a mobile system, personal computer, industrial computer, or logic system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), portable computer, tablet computer, mobile phone, smartphone, cordless phone, laptop computer, memory card, digital music system, and information sending / receiving system.

[0063] If the electronic system 8710 is capable of performing wireless communication, then the electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0064] The teachings of the present invention have been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should be considered from an illustrative rather than restrictive perspective. The scope of the teachings of the present invention is not limited to the foregoing description, but is defined by the appended claims, and all different features within the equivalent scope should be interpreted as being included in the teachings of the present invention.

[0065] Cross-reference of related applications

[0066] This application claims priority to Korean Application No. 10-2021-0144058, filed on October 26, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: A first through-hole surrounded by a liner is formed in a first semiconductor substrate; The first semiconductor substrate is recessed to expose a first portion of the end of the liner that covers the first through hole; as well as A first diffusion barrier layer is formed to cover the first recessed first semiconductor substrate and expose the second portion of the liner; Remove the second portion of the liner; The first diffusion barrier layer is recessed a second time; as well as A second diffusion barrier layer is formed, which covers the second recessed first diffusion barrier layer and the top of the liner with the second portion removed, and exposes the top surface of the end of the first through hole. The step of making a second recess in the first diffusion barrier layer is performed such that the top of the liner, from which the second portion has been removed, protrudes from the second recessed surface of the first diffusion barrier layer.

2. The method according to claim 1, further comprising the following steps: A first conductive bump and a third diffusion barrier layer are formed on a second semiconductor substrate; as well as The third diffusion barrier layer is directly bonded to the second diffusion barrier layer, and the first conductive bump is directly bonded to the top surface of the end of the first through hole.

3. The method according to claim 2, wherein, The second diffusion barrier layer prevents copper Cu ions from diffusing from the first conductive bump into the top of the liner where the second portion has been removed.

4. The method according to claim 2, wherein, The first conductive bump and the first through hole are made of the same metal material.

5. The method according to claim 4, wherein, The metallic material includes copper (Cu).

6. The method according to claim 2, wherein, The third diffusion barrier layer and the second diffusion barrier layer comprise the same dielectric material.

7. The method according to claim 2, further comprising the following step: A second through-hole is formed that penetrates the second semiconductor substrate and is electrically connected to the first conductive bump.

8. The method according to claim 1, wherein, Perform the step of making a first recess in the first semiconductor substrate, such that the end of the first through hole protrudes from the first recessed surface of the first semiconductor substrate, wherein the end is covered by the first portion of the liner.

9. The method according to claim 8, wherein, The steps for forming the first diffusion barrier layer include the following: An initial first diffusion barrier layer is formed on the first recessed surface of the first semiconductor substrate, extending to cover the end of the first through hole; Planarize the initial first diffusion barrier layer; and A third indentation is made in the initial first diffusion barrier layer that has been planarized.

10. The method according to claim 1, wherein, The step of forming the first diffusion barrier layer includes the following steps: forming the first diffusion barrier layer to partially cover the first portion of the liner, wherein a portion of the end of the first through hole protrudes from the surface of the first diffusion barrier layer and is covered by the second portion of the liner.

11. The method according to claim 1, wherein, The step of removing the second portion of the liner includes the following steps: creating a recessed depression between the end of the first through hole and the first diffusion barrier layer.

12. The method according to claim 11, wherein, The step of creating a second recess in the first diffusion barrier layer includes the following steps: etching and removing a portion of the first diffusion barrier layer to remove the recess.

13. The method according to claim 1, wherein, The steps for forming the second diffusion barrier layer include the following: An initial second diffusion barrier layer is formed, the initial second diffusion barrier layer extending to cover the end of the first through-hole where the second portion of the liner has been removed; and The initial second diffusion barrier layer is planarized to expose the top surface of the end of the first through-hole.

14. The method according to claim 13, wherein, The first through hole includes: Through-hole body, the through-hole body comprising copper (Cu); and A side barrier portion, the side barrier portion covering the through-hole body, and The step of planarizing the initial second diffusion barrier layer is performed to remove a portion of the side barrier portion to expose the top surface of the through-hole body.

15. The method according to claim 14, wherein, The side barrier includes a tantalum Ta layer or a tantalum nitride TaN layer.

16. The method according to claim 1, wherein, The second diffusion barrier layer comprises silicon nitride (Si3N4).

17. The method according to claim 1, wherein, The second diffusion barrier layer comprises the same dielectric material as the first diffusion barrier layer.

18. The method of claim 1, further comprising the step of first recessing the first semiconductor substrate prior to the step of: An interconnect layer electrically connected to the first via is formed on another surface of the first semiconductor substrate opposite to the surface on which the first recess is performed; as well as A second conductive bump is formed that is electrically connected to the interconnect layer.

19. The method according to claim 1, wherein, The liner comprises a dielectric material different from the second diffusion barrier layer, and Among them, the different dielectric materials include silicon dioxide (SiO2).

Images