Methods for fabricating contact holes in semiconductor devices

Abstract

This invention provides a method for fabricating contact holes in semiconductor devices, comprising an interlayer dielectric layer, a hard mask layer, and an advanced patterning mask layer. After transferring a photoresist pattern to the hard mask layer via etching, atomic layer deposition of mask sidewalls is performed to achieve precise compensation and control of critical dimensions. This invention optimizes the process flow to achieve stability in pattern transfer and compensation and control of critical dimensions. It can precisely control critical dimensions, thereby ensuring the stability of the total resistance value of the metal filling the contact hole, improving the process window and product yield.

Description

Technical Field

[0001] This invention pertains to the design and manufacture of semiconductor integrated circuits, and particularly relates to a method for preparing contact holes in semiconductor devices. Background Technology

[0002] In logic circuit chip manufacturing processes, the front-end of line (FEOL) and back-end of line (BEOL) processes must be interconnected through contact vias. The conventional process involves: deposition of a silicon oxide dielectric layer; followed by the required planarization process; and then direct photolithography to define the critical dimensions of the contact vias. To reduce the reflectivity of the photolithography process and improve the accuracy of the critical dimension definition, an anti-reflective layer is additionally deposited between the silicon oxide dielectric layer and the photoresist.

[0003] In advanced process nodes, the critical dimensions directly defined by photolithography are close to the physical limits. The conventional way to define the final critical dimension is to first define a large contact hole critical dimension by photolithography, then shrink this critical dimension through the etching process in the anti-reflective layer and advanced mask material layer, then transfer the pattern to the silicon oxide dielectric layer, and then etch down until the contact hole process is completed.

[0004] The above process flow has the following problems: 1) During the etching shrinkage process, if the etching rate or environment of the etching chamber changes, the amount of critical dimension shrinkage may become unstable and deviate, resulting in poor critical dimension stability. 2) The critical dimension stability of contact holes plays a crucial role in product yield. A critical dimension that is too small will cause abnormal subsequent metal plug filling; a critical dimension that is too large will compress the process window for photolithography alignment. Production experience shows that these defects result in extremely high kill ratios, requiring careful control of critical dimension compensation. However, in existing processes, there are no effective additional compensation or control methods for the critical dimension shrinkage process.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing contact holes in semiconductor devices, which solves the problem that there is no effective additional compensation or control method for the process of reducing key dimensions in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating contact holes in a semiconductor device. The method includes: 1) providing a semiconductor structure, the semiconductor structure including a substrate and electrical contacts disposed on the substrate, wherein an interlayer dielectric layer is coated on the substrate; 2) forming a hard mask layer on the interlayer dielectric layer; 3) forming an advanced patterning mask layer, an anti-reflection layer, and a patterned photoresist on the hard mask layer; 4) sequentially etching the anti-reflection layer, the advanced patterning mask layer, and the hard mask layer based on the patterned photoresist to transfer the pattern to the hard mask layer, thereby forming a contact hole in the hard mask layer. 5) Measure the size of the first etched pattern window and calculate the width difference between the current pattern window width and the target width; 6) Deposit an atomic layer hard mask material on the substrate to form a mask sidewall on the sidewall of the first etched pattern window, and control the width of the mask sidewall deposited by the atomic layer based on the width difference to shrink the width of the first etched pattern window to the target width to form a second etched pattern window; 7) Continue to etch the interlayer dielectric layer based on the second etched pattern window to form a contact hole in the interlayer dielectric layer that exposes the electrical contact point.

[0008] Optionally, the semiconductor structure includes a plurality of electronic components, and the electrical contacts are used for the electrical outgoing of the electronic components.

[0009] Optionally, the electronic component includes: a gate structure disposed on the substrate; a source and a drain disposed in the substrate and located on opposite sides of the gate structure, wherein the gate structure, the source, and the drain are all provided with electrical contact points.

[0010] Optionally, an etching stop layer is also formed on the surface of the electrical contact point.

[0011] Optionally, in step 4), the width of the front window of the first etched pattern window is the same as the width of the pattern photoresist.

[0012] Optionally, in step 6), the sidewalls of the first etched pattern window formed in the hard mask layer are perpendicular to the substrate surface.

[0013] Optionally, in step 4), during the formation of the first etched pattern window in the hard mask layer, the interlayer dielectric layer is over-etched to a depth.

[0014] Optionally, the hard mask layer has the same material as the sidewalls of the atomic layer deposition mask.

[0015] Optionally, both the hard mask layer and the atomic layer deposition mask sidewalls have a high etching selectivity with the interlayer dielectric layer.

[0016] Optionally, in step 6), the width of the mask sidewalls of the atomic layer deposition is less than or equal to one-tenth of the width of the first etch pattern window, and the height of the mask sidewalls of the atomic layer deposition is greater than or equal to ten times the thickness of the hard mask material of the atomic layer deposition.

[0017] As described above, the method for preparing semiconductor device contact holes of the present invention has the following beneficial effects:

[0018] This invention discloses a method for fabricating contact holes in semiconductor devices. A hard mask layer is deposited additionally between the interlayer dielectric layer and the advanced pattern mask layer. Then, a photoresist pattern is transferred to the hard mask layer via etching. After pattern transfer, atomic layer deposition of the mask sidewalls is performed to achieve precise compensation and control of critical dimensions. This invention optimizes the process flow to achieve stability in pattern transfer and compensation and control of critical dimensions. This invention can precisely control the critical dimensions of the contact hole, thereby ensuring the stability of the total resistance value of the metal filling the contact hole, improving the process window and product yield. Attached Figure Description

[0019] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0020] Figures 1 to 7 The diagram shows the structural schematics of each step in the method for preparing contact holes in a semiconductor device according to an embodiment of the present invention.

[0021] Component designation explanation

[0022] 10 Substrates

[0023] 11 Gate Structure

[0024] 111 Gate dielectric layer

[0025] 112 Gate electrode layer

[0026] 121 Source Contact Point

[0027] 122 Leakage Contact Point

[0028] 123 Gate contact point

[0029] 13 Gate sidewalls

[0030] 14 Etching Stop Layer

[0031] 15 Interlayer dielectric layer

[0032] 16 Hard mask layers

[0033] 161 First Etching Graphics Window

[0034] 162 Second Etching Graphics Window

[0035] 17 Advanced Patterning Mask Layers

[0036] 18 Anti-reflective layer

[0037] 19. Patterned photoresist

[0038] 20-atom deposition layer of mask sidewall

[0039] 21 Contact Hole Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0042] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0043] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] like Figures 1 to 7 As shown, this embodiment provides a method for preparing a contact hole in a semiconductor device, the method comprising the following steps:

[0048] like Figure 1 As shown, step 1) is performed first, providing a semiconductor structure, the semiconductor structure including a substrate 10 and electrical contact points disposed on the substrate 10, the substrate 10 being covered with an interlayer dielectric layer 15.

[0049] In some embodiments, the substrate 10 may be, for example, a silicon substrate. The substrate 10 may include various layers, including conductive or insulating layers formed on a semiconductor substrate. Additionally, depending on design requirements, the substrate 10 may include various doping configurations. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 10 may include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. Furthermore, the substrate 10 may include epitaxial layers, silicon-on-insulator (SOI) structures, etc.

[0050] The semiconductor structure includes multiple electronic components, and the electrical contacts are used for the electrical outgoing of the electronic components. Examples of various device components formed in and / or on the substrate 10 include metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) field-effect transistors, double-diffused metal-oxide-semiconductor field-effect transistors (DMOS), bipolar junction transistors, bipolar-complementary-metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor (BCD) transistors, high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors, diodes, thyristors, transistors, silicon-based optoelectronic devices (SIPs), optoelectronic devices, resistors, capacitors, inductors, or other suitable components or combinations thereof. Various device components can be formed using various processes, such as deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or combinations thereof. Additionally, in some embodiments, isolation components can be formed in the substrate 10 to define and isolate the various device components formed in and / or on the substrate 10. Isolation components include, for example, shallow trench isolation (STI) structures or localized oxidation of silicon (LOCOS) structures.

[0051] In one embodiment, the electronic component may be a metal-oxide-semiconductor field-effect transistor (MOSFET), the electronic component comprising: a gate structure 11 disposed on the substrate 10, which includes a gate dielectric layer 111, a gate electrode layer 112, and a gate sidewall 13; a source and a drain disposed in the substrate 10 and respectively located on both sides of the gate structure 11, wherein the gate structure 11, the source, and the drain are all provided with electrical contacts, including a gate contact 123, a source contact 121, and a drain contact 122.

[0052] In one embodiment, the material of the electrical contact point can be a metal silicide, such as a nickel-silicon alloy.

[0053] In one embodiment, an etch stop layer 14 is further formed on the surface of the electrical contact point. The etch stop layer 14 may be, for example, a silicon nitride layer, a silicon oxide layer, a silicon carbide layer, or a silicon oxynitride layer, to control the depth of the contact window. In this embodiment, the etching is a silicon nitride layer.

[0054] The interlayer dielectric layer 15 can be, for example, an oxide layer or a low dielectric constant material layer. The oxide layer can be, for example, a phosphosilicate glass layer or a borosilicate glass layer, and the low dielectric constant material layer can be, for example, a fluorosilicate glass.

[0055] like Figure 2 As shown, then step 2) is performed to form a hard mask layer 16 on the interlayer dielectric layer 15.

[0056] In one embodiment, a hard mask layer 16 may be formed on the interlayer dielectric layer 15 by processes such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP), atomic layer deposition (ALD), and low-pressure chemical vapor deposition (LPCVD).

[0057] The hard mask layer 16 is made of a different material than the interlayer dielectric layer 15 and has a high etching selectivity under the specific etching process in this embodiment. For example, the etching selectivity of the interlayer dielectric layer 15 to the hard mask layer 16 can be 50:1 or higher. The hard mask layer 16 can be a single layer or a multilayer material. For example, the material of the hard mask layer 16 can be silicon nitride, silicon oxynitride, polysilicon, carbon, or carbides, such as silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, etc., or it can be a stack of the above materials.

[0058] The thickness of the hard mask layer 16 can be set according to the thickness of the interlayer dielectric layer 15 to be etched below it, for example, it can be 1 micrometer to 1000 micrometers.

[0059] After the hard mask layer 16 is deposited, an annealing process can be added to make it denser and harder, so that it has a better etching barrier effect. The temperature of the annealing process can be adjusted according to the selected material. For example, the temperature of the annealing process can be 400℃~900℃ to avoid the temperature from being too high and affecting the electronic components in the substrate 10.

[0060] like Figure 3 As shown, then step 3) is performed to form an advanced patterned mask layer (APF layer) 17, an anti-reflective layer (DARC) 18 and a patterned photoresist 19 on the hard mask layer 16.

[0061] For example, an advanced patterned mask layer (APF layer) 17 can be formed on the hard mask layer 16 by a deposition process, and then an anti-reflective layer (DARC) can be formed by a deposition process or a coating process (such as spin coating). The anti-reflective layer can be an inorganic anti-reflective layer or an organic anti-reflective layer. Next, a photoresist layer is formed on the anti-reflective layer by a spin coating process, and the photoresist layer is patterned by an exposure process and a development process to form a patterned photoresist 19.

[0062] like Figure 4 As shown, step 4) is then performed, in which the antireflective layer 18, the advanced pattern mask layer 17 and the hard mask layer 16 are etched sequentially based on the pattern photoresist to transfer the pattern to the hard mask layer 16, and a first etched pattern window 161 is formed in the hard mask layer 16. The width of the first etched pattern window 161 is greater than the target width required for the contact hole 21.

[0063] In one embodiment, in step 4), the front window width of the first etched pattern window 161 is the same as the pattern width of the patterned photoresist. In another embodiment, in step 4), the sidewall of the first etched pattern window 161 formed in the hard mask layer 16 is perpendicular to the surface of the substrate 10 to ensure that the first etched pattern window 161 has the same pattern width as the patterned photoresist.

[0064] In one embodiment, during step 4) of forming the first etched pattern window 161 in the hard mask layer 16, the interlayer dielectric layer 15 is over-etched to a depth.

[0065] In one embodiment, the etching step may be, for example, reactive ion etching or capacitively coupled plasma etching, and the reactive gas may be, for example, fluorine-containing gas (CxFy, CHxFy, HF, SF6, NF3, etc.), argon (Ar), oxygen, carbon monoxide (CO), or a mixture thereof.

[0066] Then proceed to step 5), measure the size of the first etched graphic window 161, and calculate the width difference between the current window width and the target width.

[0067] like Figure 5 As shown, then step 6) is performed, in which atomic layer deposition of hard mask material is performed on the substrate 10 to form mask sidewalls 20 on the sidewalls of the first etched pattern window 161. The width of the atomic layer deposition mask sidewalls 20 is controlled based on the width difference, so that the width of the first etched pattern window 161 is reduced to the target width to form the second etched pattern window 162.

[0068] In one embodiment, the mask sidewalls 20 and the interlayer dielectric layer 15 have a high etching selectivity ratio under the specific etching process in this embodiment. For example, the etching selectivity ratio of the interlayer dielectric layer 15 to the mask sidewalls 20 is preferably greater than 50:1.

[0069] In one embodiment, the hard mask layer 16 and the mask sidewall 20 are made of the same material to ensure that the mask sidewall 20 is deposited on the hard mask layer 16 of the same material, thereby improving its growth quality. Of course, the hard mask layer 16 and the mask sidewall 20 can also be made of different materials.

[0070] In one embodiment, in step 6), the width of the mask sidewall 20 is less than or equal to one-tenth of the width of the first etch pattern window 161, in order to avoid the defect that the thickness of the mask sidewall 20 is too large, resulting in an excessively long deposition time.

[0071] In one embodiment, the height of the mask sidewall 20 is greater than or equal to ten times the thickness of the atomic layer deposited hard mask material. This ensures that the height of the mask sidewall 20 is significantly greater than the thickness of the atomic layer deposited hard mask material located at the bottom of the first etching pattern window 161. This allows the mask sidewall 20 to still have sufficient height to maintain its etching blocking function even after the atomic layer deposited hard mask material at the bottom of the first etching pattern window 161 has been completely etched away during subsequent etching processes. This improves the accuracy of the etching dimensions of the contact hole 21. Figure 6 As shown.

[0072] like Figures 6-7 As shown, step 7) is performed last, etching the interlayer dielectric layer 15 based on the second etching pattern window 162 to form a contact hole 21 in the interlayer dielectric layer 15 that exposes the electrical contact point.

[0073] In one embodiment, the highly anisotropic etching step is, for example, reactive ion etching or capacitively coupled plasma etching, and the reactive gas is, for example, a fluorine-containing gas (such as CxFy, CHxFy, HF, etc.), argon (Ar), oxygen, carbon monoxide (CO), or a mixture thereof. After the etching exposes the etch stop layer 14, the etch stop layer 14 is further removed to expose the electrical contact points.

[0074] As described above, the method for preparing semiconductor device contact holes of the present invention has the following beneficial effects:

[0075] This invention discloses a method for fabricating contact holes in semiconductor devices. A hard mask layer is deposited additionally between the interlayer dielectric layer and the advanced patterning mask layer. Then, a photoresist pattern is transferred to the hard mask layer via etching. After pattern transfer, atomic layer deposition of the mask sidewalls achieves precise compensation and control of critical dimensions. This invention optimizes the process flow to achieve stability in pattern transfer and compensation and control of critical dimensions. This invention can precisely control critical dimensions, thereby ensuring the stability of the total resistance value of the metal filling the contact hole, improving the process window and product yield. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a contact hole in a semiconductor device, characterized in that, The preparation method includes: 1) A semiconductor structure is provided, the semiconductor structure including a substrate and electrical contacts disposed on the substrate, the substrate being covered with an interlayer dielectric layer; 2) A hard mask layer is formed on the interlayer dielectric layer; 3) An advanced patterned mask layer, an anti-reflection layer, and a patterned photoresist are formed on the hard mask layer; 4) Based on the patterned photoresist, the anti-reflection layer, the advanced patterned mask layer, and the hard mask layer are etched sequentially to transfer the pattern to the hard mask layer, forming a first etched pattern window in the hard mask layer; 5) Measure the size of the first etched graphic window and calculate the width difference between the current graphic window width and the target width; 6) Perform atomic layer deposition of hard mask material on the substrate to form mask sidewalls on the sidewalls of the first etched pattern window. Control the width of the mask sidewalls deposited by the atomic layer based on the width difference to shrink the width of the first etched pattern window to the target width to form a second etched pattern window. 7) Continue etching the interlayer dielectric layer based on the second etching pattern window to form contact holes in the interlayer dielectric layer that expose the electrical contact points; The width of the mask sidewalls of the atomic layer deposition is less than or equal to one-tenth of the width of the first etch pattern window, and the height of the mask sidewalls of the atomic layer deposition is greater than or equal to ten times the thickness of the hard mask material of the atomic layer deposition.

2. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: The semiconductor structure includes multiple electronic components, and the electrical contacts are used for the electrical outgoing of the electronic components.

3. The method for preparing a semiconductor device contact hole according to claim 2, characterized in that: The electronic components include: A gate structure is disposed on the substrate; The source and drain are disposed in the substrate and located on both sides of the gate structure, wherein the gate structure, the source and the drain are provided with electrical contact points.

4. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: An etching stop layer is also formed on the surface of the electrical contact point.

5. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: In step 4), the width of the front window of the first etched pattern window is the same as the width of the pattern photoresist.

6. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: In step 6), the sidewalls of the first etched pattern window formed in the hard mask layer are perpendicular to the substrate surface.

7. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: Step 4) During the formation of the first etched pattern window in the hard mask layer, the interlayer dielectric layer is over-etched to a depth.

8. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: The hard mask layer and the mask sidewalls are made of the same material.

9. The method for preparing a semiconductor device contact hole according to claim 1, characterized in that: Both the hard mask layer and the mask sidewall have a high etching selectivity for the interlayer dielectric layer under the dielectric layer etching process in step 7).

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