ESD protection devices and their manufacturing methods

Abstract

This invention discloses an ESD protection device and its manufacturing method. The ESD protection device includes a substrate of a first doping type; at least two identical cells located in the substrate; and a third doped region extending from the upper surface of the substrate into it. At least one of the third doped regions is included between each pair of adjacent cells. Each cell includes multiple doped regions, and each pair of adjacent cells forms a thyristor structure. The ESD protection device provided by this invention has simple manufacturing process, small area, low capacitance, low leakage current, and low clamping voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to an ESD protection device and a method for manufacturing the same. Background Technology

[0002] Static electricity has always been a difficult problem to solve for electronic products, especially in high-speed interface applications such as USB, HDMI, and Thunderbolt. Figure 1 The diagram shows a cross-sectional view of a bidirectional thyristor (SCR) in an electrostatic discharge device. From I / O_1 to I / O_2 is SCR1 connected in series with Diode2, and from I / O_2 to I / O_1 is SCR2 connected in series with Diode1. SCR1 and SCR2, and Diode1 and Diode2 are completely symmetrical.

[0003] On a high-resistivity substrate 101 (>100 ohm·cm), NW / PW / N+ / P+ are implanted to form thyristors and diodes. The thyristor SCR is composed of P+ / NW / PW / N+. The junction breakdown voltage of Pt / NW determines the turn-on voltage of the thyristor SCR, and the magnitude of the turn-on voltage determines the Pt / NW junction capacitance. Therefore, the capacitance of the thyristor SCR is mainly affected by the NW / Pt junction capacitance. The diode is composed of Nw / substrate 101. The concentration of substrate 101 and the area of ​​NW determine the capacitance of the diode.

[0004] The main drawbacks of existing electrostatic discharge devices are that the series connection of the thyristor SCR and the diode leads to high clamping voltage and large junction area, and the high Pt concentration leads to high capacitance of the thyristor SCR. Summary of the Invention

[0005] In summary, the present invention provides an ESD protection device to solve the problems existing in the prior art.

[0006] According to a first aspect of the present invention, an ESD protection device is provided, comprising: a substrate of a first doping type; at least two identical cells located in the substrate; and a third doped region extending from the upper surface of the substrate into the substrate, wherein at least one of the third doped regions is included between each two adjacent cells, wherein each cell includes a plurality of doped regions, and each two adjacent cells form a thyristor structure.

[0007] Preferably, each unit includes a first well region extending from the upper surface of the substrate into the substrate, a first doped region extending from the upper surface of the substrate into the substrate, and a second doped region located in the first well region, wherein the third doped region and the second doped region are of a first doping type; and the first doped region and the first well region are of a second doping type.

[0008] Preferably, the first doped region is at least partially located in the first well region.

[0009] Preferably, a third doped region is included between every two adjacent units.

[0010] Preferably, each unit further includes a fourth doped region located in the first well region, wherein the fourth doped region is of the first doping type, and the first doped region is located between the second doped region and the fourth doped region.

[0011] Preferably, each pair of adjacent units includes two third doped regions.

[0012] Preferably, the first well region and the third doped region are not in contact.

[0013] Preferably, the distance between the third doped region and the adjacent first well region is greater than 0 and less than or equal to 1 μm.

[0014] Preferably, it further includes a second well region located between two adjacent units and having a first doping type, to prevent the first well region from penetrating between the two adjacent units.

[0015] Preferably, the width of the second well region is greater than or equal to 1 μm and less than or equal to 2 μm.

[0016] Preferably, the depths of the third doped region and the second well region are less than the depth of the first well region.

[0017] Preferably, the first well region does not completely enclose the first doped region.

[0018] Preferably, the first doped region and the second doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals.

[0019] Preferably, the first doped region, the second doped region, and the fourth doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals.

[0020] Preferably, the distance between adjacent first well regions is greater than or equal to 4 μm and less than or equal to 5 μm.

[0021] Preferably, the third doped region is adjacent to one of the first well regions in two adjacent cells, and the second well region is adjacent to the first doped region in the other cell.

[0022] Preferably, the second well region is located between the two third doped regions.

[0023] According to a second aspect of the present invention, a method for manufacturing an ESD protection device is provided, comprising: forming n identical cells located in a substrate, n being greater than or equal to 2, and forming a third doped region extending from the upper surface of the substrate into the substrate, wherein at least one of the third doped regions is included between two adjacent cells, wherein each cell includes a plurality of doped regions, and every two adjacent cells form a thyristor structure.

[0024] Preferably, the method of forming n identical units includes: forming n first well regions extending from and into the upper surface of the substrate; and forming n first doped regions extending from and into the upper surface of the substrate, wherein a second doped region extending from and into the upper surface of the substrate is formed in each first well region, wherein the substrate, the third doped region, and the second doped region are of a first doping type; and the first well region and the first doped region are of a second doping type.

[0025] Preferably, the first doped region is at least partially located in the first well region.

[0026] Preferably, a third doped region is included between every two adjacent units.

[0027] Preferably, each unit further includes a fourth doped region located in the first well region, wherein the fourth doped region is of the first doping type, and the first doped region is located between the second doped region and the fourth doped region.

[0028] Preferably, each pair of adjacent units includes two third doped regions.

[0029] Preferably, the method further includes forming a second well region with a first doping type between two adjacent units to prevent the first well region from penetrating between the two adjacent units.

[0030] Preferably, the first well region and the third doped region are not in contact.

[0031] Preferably, the distance between the third doped region and the adjacent first well region is greater than 0 and less than or equal to 1 μm.

[0032] Preferably, the first well region does not completely enclose the first doped region.

[0033] Preferably, the width of the second well region is greater than or equal to 1 μm and less than or equal to 2 μm.

[0034] Preferably, the first doped region and the second doped region in each unit are connected to the same input / output terminal, and each two adjacent units are connected to two different input / output terminals.

[0035] Preferably, the first doped region, the second doped region, and the fourth doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals.

[0036] The ESD protection device provided by this invention eliminates the series diode structure, reducing the clamping voltage and chip area. Furthermore, by ensuring the first well region and the third doped region do not contact each other, the junction capacitance between them can be reduced. Additionally, the first well region does not completely enclose the first doped region, further reducing its area. A second well region is placed between two cells to prevent punch-through between adjacent first well regions. The ESD protection device provided by this invention features simple manufacturing process, small area, low capacitance, low leakage current, and low clamping voltage. Attached Figure Description

[0037] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0038] Figure 1 A cross-sectional view of an ESD protection device according to the prior art is shown;

[0039] Figure 2 A cross-sectional view of an ESD protection device according to a first embodiment of the present invention is shown;

[0040] Figure 3 A cross-sectional view of an ESD protection device according to a second embodiment of the present invention is shown. Detailed Implementation

[0041] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0042] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0043] To describe a situation where A is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B". In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0044] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0045] This invention provides an ESD protection device, comprising: a substrate of a first doping type;

[0046] The substrate contains at least two identical cells and a third doped region extending from the upper surface of the substrate into it, wherein at least one of the third doped regions is included between each pair of adjacent cells, wherein each cell includes a plurality of doped regions, and each pair of adjacent cells forms a thyristor structure.

[0047] Figure 2 A cross-sectional view of an ESD protection device according to a first embodiment of the present invention is shown.

[0048] Please refer to Figure 2 The substrate 201 is, for example, composed of silicon and is of a first doping type. The first doping type is either N-type or P-type, and the second doping type is the other of N-type and P-type. In this embodiment, the substrate 201 is preferably a high-resistivity substrate. If the doping concentration of the substrate 201 is too low, leakage current may occur; if the doping concentration of the substrate 201 is too high, it will affect the capacitance of the device. Therefore, the doping concentration of the substrate 201 is preferably 1 × 10⁻⁶. 13 cm -3 ~1×10 14 cm -3 .

[0049] At least two identical units 220 are located in the substrate 201. Each unit 220 includes a first well region 210 extending from the upper surface of the substrate 201 and therein, a first doped region 211 extending from the upper surface of the substrate 201 and therein, and a second doped region 212 extending from the upper surface of the substrate 201 and therein, located in the first well region 210. The second doped region 212 is of a first doping type; the first doped region 211 and the first well region 210 are of a second doping type. Furthermore, the first doped region 211 is at least partially located in the first well region 210. In this embodiment, the first well region 210 does not completely enclose the first doped region 211, i.e., the area of ​​the first well region 210 is reduced, thereby reducing the junction capacitance between the first well region 210 and the substrate 201, and simultaneously reducing the resistance under the first doped region 211, further reducing the clamping voltage. It is important to note that if adjacent first well regions 210 are too close together, there is a risk of punch-through, leading to increased leakage current. Conversely, if the distance is too great, the resistance of the substrate 201 between adjacent first well regions 210 will cause an increase in clamping voltage. Therefore, in this embodiment, the distance between adjacent first well regions 210 is set to be greater than or equal to 4 μm and less than or equal to 5 μm. In this embodiment, the substrate 201 of the ESD protection device includes four identical units, but is not limited to four; it can include two or more, depending on specific design specifications and requirements.

[0050] Each pair of adjacent units forms a thyristor structure. Specifically, from left to right, the units are sequentially named the first unit, the second unit, the third unit, and so on. The first thyristor structure includes a second doped region 212 of the first unit, a first well region 210 of the first unit, a substrate 201, and a first doped region 211 of the second unit. The second doped region 212, the first well region 210, and the substrate 201 of the first unit form the first transistor of the thyristor, while the first well region 210, the substrate 201, and the first doped region 211 of the second unit form the second transistor of the thyristor. For example, in this embodiment, a total of three thyristor structures are formed. The other two thyristor structures are similar to the first thyristor structure and will not be described further here.

[0051] Each pair of adjacent units 220 includes a third doped region 213, which extends from the upper surface of the substrate into the interior of the substrate. The third doped region 213 is of a first doping type. The third doped region 213 is used to turn on the thyristor; that is, the breakdown voltage of the third doped region 213 and the adjacent first well region 210 is the turn-on voltage of the thyristor. The first well region 210 is configured not to contact the adjacent third doped region 213. Preferably, the distance between the first well region 210 and the adjacent third doped region 213 is greater than 0 μm and less than or equal to 1 μm. This configuration ensures both the turn-on voltage of the first well region 210 and the third doped region 213 and effectively reduces the junction capacitance between the first well region 210 and the third doped region 213.

[0052] The ESD protection device further includes a second well region 214 located between two adjacent cells and having a first doping type, to prevent the first well region 210 from penetrating between the two adjacent cells. The width of the second well region 214 is greater than or equal to 1 μm and less than or equal to 2 μm. The depth of the third doped region 213 and the second well region 214 is less than the depth of the first well region 210. The third doped region 213 is adjacent to the first well region 210 of one of the two adjacent cells, and the second well region 214 is adjacent to the first doped region 211 of the other cell.

[0053] The ESD protection device also includes an isolation structure 215 located at the edge of the device, which can be filled with insulating material in the isolation trench.

[0054] The first doped region and the second doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals. In this embodiment, the first doped region 211 and the second doped region 212 in the first unit and the third unit are connected to the input / output terminal I / O_1, and the first doped region 211 and the second doped region 212 in the second unit and the fourth unit are connected to the input / output terminal I / O_2.

[0055] Figure 3 A cross-sectional view of an ESD protection device according to a second embodiment of the present invention is shown.

[0056] Please refer to Figure 3The substrate 301 is, for example, composed of silicon and is of a first doping type. The first doping type is either N-type or P-type, and the second doping type is the other of N-type and P-type. In this embodiment, the substrate 301 is preferably a high-resistivity substrate. If the doping concentration of the substrate 301 is too low, leakage current may occur; if the doping concentration of the substrate 301 is too high, it will affect the capacitance of the device. Therefore, the doping concentration of the substrate 301 is preferably 1 × 10⁻⁶. 13 cm -3 ~1×10 14 cm -3 .

[0057] At least two units 320 are located in the substrate. Each unit 320 includes a first well region 310 extending from the upper surface of the substrate 301 and located therein, a first doped region 312 extending from the upper surface of the substrate 301 and located therein in the first well region 310, a second doped region 313 extending from the upper surface of the substrate 301 and located therein in the first well region 310, and a fourth doped region 311 extending from the upper surface of the substrate 301 and located therein in the first well region 310. The first doped region 312 is located between the second doped region 313 and the fourth doped region 311, which are of a first doping type; the first doped region 312 and the first well region 310 are of a second doping type. In this embodiment, the substrate of the ESD protection device includes two units, but is not limited to two; it may include two or more, depending on specific design specifications and requirements. It is important to note that if the adjacent first well regions 310 are too close, there is a risk of penetration, leading to increased leakage current. Conversely, if the distance is too great, the substrate resistance 301 between adjacent first well regions 310 will cause an increase in clamping voltage. Therefore, in this embodiment, the distance between adjacent first well regions 310 is set to be greater than or equal to 4 μm and less than or equal to 5 μm.

[0058] Each pair of adjacent units forms a thyristor structure. Specifically, from left to right, the units are sequentially named the first unit, the second unit, and so on. The first thyristor structure includes a second doped region 313 of the first unit, a first well region 310 of the first unit, a substrate 301, and a first well region 310 of the second unit. The second doped region 313, the first well region 310, and the substrate 301 of the first unit form the first transistor of the thyristor, while the first well region 310, the substrate 301, and the first well region 310 of the second unit form the second transistor of the thyristor. The ESD protection device in this embodiment is symmetrical; for example, a thyristor structure can be formed from the first unit to the second unit, and similarly, a thyristor structure can be formed from the second unit to the first unit.

[0059] Each pair of adjacent units 320 includes two third doped regions 314, which extend from the upper surface of the substrate into the interior of the substrate 301. The third doped regions 314 are of a first doping type. The third doped regions 314 are used to turn on the thyristor; that is, the breakdown voltage of the third doped region 314 and its adjacent first well region 310 is the turn-on voltage of the thyristor. The first well region 310 is configured not to contact its adjacent third doped regions 314. Preferably, the distance between the first well region 310 and its adjacent third doped regions 314 is greater than 0 μm and less than or equal to 1 μm. This configuration ensures both the turn-on voltage of the first well region 310 and its adjacent third doped regions 314 and effectively reduces the junction capacitance between the first well region 310 and its adjacent third doped regions 314.

[0060] The ESD protection device further includes a second well region 315 located between two adjacent cells and having a first doping type, to prevent the first well region 310 from penetrating between the two adjacent cells. The width of the second well region 315 is greater than or equal to 1 μm and less than or equal to 2 μm. The depth of the third doped region 314 and the second well region 315 is less than the depth of the first well region 310. The second well region 315 is located between two third doped regions 314.

[0061] The ESD protection device also includes an isolation structure 316 located at the edge of the device, which can be filled with insulating material in the isolation trench.

[0062] The first, second, and fourth doped regions in each unit are connected to the same input / output terminals, and each pair of adjacent units are connected to different input / output terminals. In this embodiment, the first doped region 312, the second doped region 313, and the fourth doped region 311 in the first and third units are connected to I / O_1, and the first, second, and fourth doped regions 312, 313, and 311 in the second and fourth units are connected to I / O_2.

[0063] The present invention also provides a method for manufacturing an ESD protection device, comprising: forming n cells located in a substrate, n being greater than or equal to 2, and forming a third doped region extending from the upper surface of the substrate into the substrate, wherein at least one of the third doped regions is included between two adjacent cells, wherein each cell includes multiple doped regions, and every two adjacent cells form a thyristor structure.

[0064] A method for forming n units includes: forming n first well regions extending from and into the upper surface of the substrate; and forming n first doped regions extending from and into the upper surface of the substrate, wherein a second doped region extending from and into the upper surface of the substrate is formed in each first well region, wherein the first doped region is at least partially located in the first well region, the substrate, the third doped region, and the second doped region are of a first doping type; and the first well region and the first doped region are of a second doping type.

[0065] Specifically, with Figure 2 Taking the ESD protection device of the first embodiment as an example, the manufacturing method includes:

[0066] Step 1: Using an ion implantation process, a first well region 210 of the second doped type is formed in the substrate 201, extending from the upper surface of the substrate into it. The junction depth of the first well region 210 should not be too deep, as excessive depth will affect the area of ​​the first well region 210 and thus affect the capacitance of the first well region 210.

[0067] Step 2: Using an ion implantation process, a first doped region 211 of the second doping type and a second doped region 212 of the first doping type are formed in the first well region 210, wherein the first well region 210 does not completely cover the first doped region 211. In this embodiment, the first well region 210 does not completely cover the first doped region 211, that is, the area of ​​the first well region 210 is reduced, thereby reducing the junction capacitance between the first well region 210 and the substrate 201, and at the same time reducing the resistance under the first doped region 211, further reducing the clamping voltage.

[0068] Step 3: Using ion implantation, a third doped region 213 of the first doping type and a second well region 214 of the first doping type are formed between two adjacent cells. The first well region 210 is configured to not contact its adjacent third doped region 213. Preferably, the distance between the first well region 210 and its adjacent third doped region 213 is greater than 0 μm and less than or equal to 1 μm. This configuration ensures the turn-on voltage of the first well region 210 and its adjacent third doped region 213 while effectively reducing their junction capacitance. The second well region 214 prevents the first well region 210 from penetrating between two adjacent cells. The width of the second well region 214 is set to be greater than or equal to 1 μm and less than or equal to 2 μm.

[0069] Step 4: Form an isolation structure 215 at the edge of the ESD protection device. Specifically, form a groove at the edge of the ESD protection device and then fill the groove with insulating material.

[0070] Step 5: Perform back-end processes to form interlayer dielectric layers, metal layers, passivation layers, and input / output terminals, etc.

[0071] Specifically, with Figure 3 Taking the ESD protection device of the second embodiment as an example, the manufacturing method includes:

[0072] Step 1: Using an ion implantation process, a first well region 310 of the second doped type is formed in the substrate 301, extending from the upper surface of the substrate into it. The junction depth of the first well region 310 should not be too deep, as excessive depth will affect the area of ​​the first well region 310 and thus affect the capacitance of the first well region 310.

[0073] Step 2: Form a first doped region 312 of the second doping type, a second doped region 313 of the first doping type, and a fourth doped region 311 of the first doping type in the first well region 210. The second doped region 313 and the fourth doped region 311 are located on opposite sides of the first doped region 312.

[0074] Step 3: Form two third doped regions 314 of the first doping type and one second well region 315 of the first doping type between every two adjacent cells. The second well region 315 is located between two of the third doped regions 314. The first well region 310 is configured not to contact its adjacent third doped region 314. Preferably, the distance between the first well region 310 and its adjacent third doped region 314 is greater than 0 μm and less than or equal to 1 μm. This configuration ensures the turn-on voltage of the first well region 310 and its adjacent third doped region 314 while effectively reducing the junction capacitance between them. The second well region 315 prevents the first well region 310 from penetrating between two adjacent cells. The width of the second well region 315 is greater than or equal to 1 μm and less than or equal to 2 μm.

[0075] Step 4: Form an isolation structure 316 at the edge of the ESD protection device. Specifically, form a groove at the edge of the ESD protection device and then fill the groove with insulating material.

[0076] Step 5: Perform back-end processes to form interlayer dielectric layers, metal layers, passivation layers, and input / output terminals, etc.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An ESD protection device, wherein, include: First type of doped substrate; At least two identical units located in the substrate, and A third doped region extends from the upper surface of the substrate into it, and at least one of the third doped regions is included between every two adjacent cells. Each of the units includes multiple doped regions, and every two adjacent units form a thyristor structure. Each cell includes a first well region extending from the upper surface of the substrate into the substrate, a first doped region extending from the upper surface of the substrate into the substrate, and a second doped region located in the first well region, wherein the third doped region and the second doped region are of a first doping type; and the first doped region and the first well region are of a second doping type. The first doped region is at least partially located in the first well region, and the first well region does not completely enclose the first doped region.

2. The ESD protection device of claim 1, wherein, Each pair of adjacent units includes a third doped region.

3. The ESD protection device of claim 1, wherein, Each cell also includes a fourth doped region located in the first well region, wherein the fourth doped region is of the first doping type and the first doped region is located between the second doped region and the fourth doped region.

4. The ESD protection device of claim 3, wherein, Each pair of adjacent units includes two third doped regions.

5. The ESD protection device of claim 1, wherein, The first well region is not in contact with the third doped region.

6. The ESD protection device according to claim 1, wherein, The distance between the third doped region and its adjacent first well region is greater than 0 and less than or equal to 1 μm.

7. The ESD protection device of claim 1 or 4, wherein, It also includes a second well region located between two adjacent units and having a first doping type, to prevent the first well region from penetrating between the two adjacent units.

8. The ESD protection device of claim 7, wherein, The width of the second well region is greater than or equal to 1 μm and less than or equal to 2 μm.

9. The ESD protection device of claim 7, wherein, The depths of the third doped region and the second well region are less than the depth of the first well region.

10. The ESD protection device according to claim 1, wherein, The first doped region and the second doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals.

11. The ESD protection device according to claim 3, wherein, The first doped region, the second doped region, and the fourth doped region in each unit are connected to the same input / output terminal, and each pair of adjacent units are connected to two different input / output terminals.

12. The ESD protection device of claim 1, wherein, The distance between adjacent first well regions is greater than or equal to 4 μm and less than or equal to 5 μm.

13. The ESD protection device of claim 7, wherein, The third doped region is adjacent to one of the first well regions in two adjacent units, and the second well region is adjacent to the first doped region in the other unit.

14. The ESD protection device of claim 7, wherein, The second well region is located between the two third doped regions.

15. A method of manufacturing an ESD protection device, wherein, include: Form n identical units located in the basis, where n is greater than or equal to 2, and A third doped region is formed extending from the upper surface of the substrate into it, with at least one of the third doped regions between two adjacent cells. Each of the units includes multiple doped regions, and every two adjacent units form a thyristor structure; the method for forming n identical units includes: Forming n first well regions extending from the upper surface of the substrate into it; and n first doped regions are formed extending from the upper surface of the substrate into it. A second doped region is formed in each of the first well regions, extending from the upper surface of the substrate into it. Wherein, the substrate, the third doped region, and the second doped region are of the first doping type; the first well region and the first doped region are of the second doping type; The first doped region is at least partially located in the first well region, and the first well region does not completely enclose the first doped region.

16. The method of claim 15, wherein, Each pair of adjacent units includes a third doped region.

17. The method of claim 15, wherein, Each cell also includes a fourth doped region located in the first well region, wherein the fourth doped region is of the first doping type and the first doped region is located between the second doped region and the fourth doped region.

18. The method of claim 17, wherein, Each pair of adjacent units includes two third doped regions.

19. The method of claim 16 or 18, wherein, It also includes forming a second well region with a first doping type between two adjacent units to prevent the first well region from penetrating between the two adjacent units.

20. The method of claim 15, wherein, The first well region is not in contact with the third doped region.

21. The method of claim 15, wherein, The distance between the third doped region and its adjacent first well region is greater than 0 and less than or equal to 1 μm.

22. The method of claim 19, wherein, The width of the second well region is greater than or equal to 1 μm and less than or equal to 2 μm.

23. The method of claim 15, wherein, The first doped region and the second doped region in each cell are connected to the same input / output terminal, and each two adjacent cells are connected to two different input / output terminals.

24. The method of claim 17, wherein, The first doped region, the second doped region, and the fourth doped region in each cell are connected to the same input / output terminal, and each pair of adjacent cells are connected to two different input / output terminals.

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