Semiconductor structure, method of manufacturing a semiconductor structure, and chip

Abstract

This invention discloses a semiconductor structure, a method for manufacturing the semiconductor structure, and a chip, relating to the field of semiconductor technology, which facilitates efficient and low-cost solutions to antenna effect violations. The semiconductor structure includes: a semiconductor substrate; a first MOS transistor grown in the active region, including a source, a drain, and a gate, with an isolation layer between the source and drain, the isolation layer being part of the field region, and the gate located above the isolation layer; the source, drain, and isolation layer forming a MOS capacitor; the source and drain are respectively connected to the semiconductor substrate, and the gate is connected to an overhead power network; and a physical unit grown in the active region and isolated from the first MOS transistor, one end of the physical unit being connected to the power network, and the other end being connected to the semiconductor substrate. This invention is applicable to chip design and manufacturing scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for manufacturing the semiconductor structure, and a chip. Background Technology

[0002] With the rapid development of integrated circuits, ultra-large-scale SoCs (System-on-a-Chip) have gradually become the focus of the industry. As process dimensions continue to shrink, gate sizes become smaller, and the number of metal layers increases, the risk of antenna effects increases. Antenna effects severely restrict the high-quality development of integrated circuits.

[0003] In the process of realizing this invention, the inventors of this application discovered that in the physical implementation of high-performance CPU large-scale chips, a large number of specific decap cell (Decoupling capacitor cell, also known as decoupling capacitor) structures are used. Due to the special nature of this structure, in the top-level physical implementation above the hard IP, due to the use of power networks and the excessively large metal area, the risk of antenna effect violations is also higher. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor structure, a semiconductor structure manufacturing method, and a chip, which facilitates efficient and low-cost solutions to the problem of antenna effect violations.

[0005] To achieve the above-mentioned objectives, the following technical solution is adopted:

[0006] According to a first aspect of the present invention, a semiconductor structure is provided, comprising:

[0007] A semiconductor substrate for forming an active region and a field region on its surface, the active region for growing a device, and the field region for isolating the active region into different portions;

[0008] The first MOS transistor, grown in the active region, includes a source, a drain, and a gate. An isolation layer is provided between the source and the drain. The isolation layer is part of the field region. The gate is located above the isolation layer. The source, drain, and isolation layer form a MOM capacitor.

[0009] The source and drain are respectively connected to the semiconductor substrate, and the gate is connected to the power network above.

[0010] A physical unit is grown in the active region and isolated from the first MOS transistor. One end of the physical unit is connected to the power network, and the other end of the physical unit is connected to the semiconductor substrate.

[0011] Optionally, the physical unit is a decoupling unit.

[0012] Optionally, the decoupling unit is formed by a second MOS transistor grown in the active region.

[0013] Optionally, the second MOS transistor is a PMOS transistor, and the active region for growing the second MOS transistor is an N-well region.

[0014] Optionally, the semiconductor substrate is a P-type substrate, and the P-type substrate is connected to a ground point.

[0015] According to a second aspect of the present invention, a method for manufacturing a semiconductor structure is provided, the method comprising: providing a semiconductor substrate; forming an active region and a field region on the semiconductor substrate, the field region being used to isolate the active region into different parts; forming a first MOS transistor and a physical unit in the active region, and respectively interconnecting them to an upper power network through upper and lower layers; connecting the power network to the semiconductor substrate through the physical unit; and in a semiconductor etching process, discharging charge ions accumulated in the power network to the semiconductor substrate through the physical unit.

[0016] Optionally, the method further includes: connecting the semiconductor substrate to a ground point before, after, or simultaneously with connecting the power network to the semiconductor substrate through the physical unit; the step of discharging the charge ions accumulated in the power network to the semiconductor substrate through the physical unit in the semiconductor etching process includes: after discharging the charge ions accumulated in the power network to the semiconductor substrate through the physical unit in the semiconductor etching process, releasing the charge ions to the ground point.

[0017] Optionally, the physical unit is a decoupling unit.

[0018] Optionally, the decoupling unit is formed by a capacitor composed of PMOS transistors.

[0019] According to a third aspect of the present invention, a chip is provided, comprising: a semiconductor substrate for forming an active region and a field region on its surface, the active region being used to grow a device, and the field region being used to isolate the active region into different parts; a first MOSFET grown in the active region, comprising: a source, a drain, and a gate, an isolation layer being disposed between the source and the drain, the isolation layer being part of the field region, the gate being located above the isolation layer, and the source, drain, and isolation layer forming a MOM capacitor; the source and drain being respectively connected to the semiconductor substrate; a power network located above the first MOSFET, and one end of the power network being connected to the gate of the MOSFET; and a physical unit grown in the active region and isolated from the first MOSFET, one end of the physical unit being connected to the power network, and the other end of the physical unit being connected to the semiconductor substrate. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram illustrating the application of a specific decap cell structure in a semiconductor structure according to an embodiment.

[0022] Figure 2 This is a schematic diagram of an embodiment of the semiconductor structure of the present invention;

[0023] Figure 3 A schematic diagram of the equivalent circuit structure of an embodiment of the semiconductor structure of the present invention;

[0024] Figure 4 This is a schematic flowchart of an embodiment of the design method for suppressing the antenna effect of a chip power network according to the present invention;

[0025] Figure 5 This is a schematic diagram of the equivalent circuit structure of an embodiment of the chip of the present invention. Detailed Implementation

[0026] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0028] To help understand the technical solutions and their effects provided by the embodiments of the present invention, a brief introduction to the relevant technologies is given below in conjunction with the accompanying drawings:

[0029] Figure 1 This is a schematic diagram illustrating the application of a specific decap cell structure in a semiconductor structure, as shown in the example. Figure 1 As shown, in related technologies, specific decap cells are connected to the top-level physical design. The specific decap cell layout structure consists of MOM capacitors and MOSFETs. The negative terminal of the MOM capacitor is connected to the source and drain of the MOSFET and is connected to the P-type substrate. The positive terminal of the MOM capacitor is connected to the gate of the MOSFET and is connected to the power network of the top-level physical design. Large-scale high-performance CPU digital module physical designs use a large number of such decap cell structures. While antenna effect problems generally do not exist within the IP (in semiconductor technology, this refers to the chip core), in the top-level physical implementation, due to the use of the power network and the excessively large metal area, numerous antenna effect violations occur.

[0030] To address this issue, some related technologies involve repairing the chip by adding reverse diodes. However, this requires calculating the number of diodes needed using antenna effect formulas. Since a large number of diodes are typically used, they occupy chip layout area and are costly. Therefore, this repair method increases the number of components and wastes a significant amount of chip area, resulting in high costs.

[0031] In other related technologies, repairing the antenna effect by using jumpers is also a common method. However, it is difficult to repair all metal layers completely, and the iteration cycle is long, resulting in low efficiency.

[0032] To efficiently, cost-effectively, and quickly resolve antenna effect violations, this invention provides a novel semiconductor structure that saves chip layout area and reduces chip cost. Applicable to chip (sometimes called integrated circuit, or simply chip) design and manufacturing scenarios, it can be used to eliminate antenna effect violations (referring to situations exceeding specified thresholds) to ensure chip quality after production.

[0033] Figure 2 This is a schematic diagram of an embodiment of the semiconductor structure of the present invention; Figure 3 A schematic diagram of the equivalent circuit structure of an embodiment of the semiconductor structure of the present invention; please refer to... Figure 2 and Figure 3As shown, taking a P-type semiconductor substrate as an example, the technical solution of this invention can also be implemented on an N-type semiconductor substrate, only the process of growing the MOS transistor is slightly different. In some embodiments, the semiconductor structure 100 provided by this invention is applicable to chip design and manufacturing scenarios, including: a semiconductor substrate 10, for forming an active region 11 and a field region 12 on its surface, wherein the active region 11 is used for growing devices, and the field region 12 is used to isolate the active region into different parts;

[0034] The first MOS transistor 20 is grown in the active region 11 and includes a source, a drain and a gate. An isolation layer 13 is provided between the source and the drain. The isolation layer 13 is part of the field region. The gate is located above the isolation layer 13. The source, drain and isolation layer form a MOM capacitor.

[0035] The source and drain are respectively connected to the semiconductor substrate, and the gate is connected to the power network above.

[0036] Physical unit 30 is grown in the active region 11 and isolated from the first MOS transistor 20. One end of the physical unit 30 is connected to the power network, and the other end of the physical unit is connected to the semiconductor substrate 10.

[0037] Specifically, the physical cell 30 is grown in the N-well region.

[0038] MOM capacitors, also known as finger intercalation capacitors, are mainly formed by the parasitic capacitance between the edges of the same layer of metal or between two plates. Sometimes, multiple layers of metal can be stacked.

[0039] Of course, since the source and drain of the first MOS transistor are equivalent to a capacitor structure, and it is connected to the semiconductor substrate, it can also form a charge discharge circuit to discharge the charge ions in the physical implementation process of the power network.

[0040] Additionally, it should be noted that a MOSFET is a four-terminal device, marked with substrate contact 14 in the diagram. The substrate contact refers to the N+ ring around which the power supply is connected for a PMOS transistor, and the P+ ring around which the power supply is connected for an NMOS transistor. Generally, the substrate contact is N+ for PMOS transistors and P+ for NMOS transistors. By setting the substrate contact, latch-up can be prevented, improving the performance of the semiconductor structure.

[0041] In some embodiments, the substrate contact distance from the MOS transistor source is less than 25 μm.Figure 1 The diagram illustrates a method for arranging substrate contacts 14. Multiple contacts can also be arranged around the MOS transistor, although this may increase the area occupied by the semiconductor structure.

[0042] also, Figure 1 In order to highlight the innovative nature of this invention, some general structures have been simplified, such as the connection structure between the metal layers at the top layer and the active region.

[0043] In some embodiments, the physical unit 30 is a decap cell, also known as a decoupling unit. Specifically, the decap cell is formed by a second MOS transistor grown in the active region. When a P-type semiconductor substrate is used, and the second MOS transistor is a PMOS transistor, in order to form a PMOS transistor, an N-well region needs to be etched on the P-type semiconductor substrate, and then a mask is used to form the PMOS transistor by ion implantation.

[0044] Therefore, in some embodiments, the second MOS transistor is a PMOS transistor, and the active region for growing the second MOS transistor is an N-well region.

[0045] For example, the physical unit mainly includes an NW-OD (N well-Gate Oxide and Diffusion, active region; at the foundry level, it is also called ACT or AA, all referring to the concept of an active region used to grow devices). One end of it is connected to the power network of the top layer, and the other end is grounded through the semiconductor substrate. This forms a reverse-biased diode, but compared to using an off-the-shelf diode, the carrier concentration of this reverse-biased diode is more uniform and the conductivity is more stable. The charge discharge circuit formed in this way can discharge the charge generated by the accumulated plasma etching to the substrate during the etching process, so that the accumulated charge does not pose a threat to the gate oxide, thereby playing a role in protecting against the antenna effect.

[0046] Generally, to fabricate a PMOS transistor on a P-substrate, an N-well region needs to be photolithographically formed on the substrate first. In some embodiments, the decoupling unit is formed by a capacitor composed of a PMOS transistor.

[0047] In this embodiment, the semiconductor substrate is a P-type substrate, which is connected to a ground point. Thus, the charge discharge loop formed between the power network and ground will discharge the accumulated charge generated by plasma etching to the substrate and release it to the ground point, preventing the accumulated charge from threatening the gate oxide and suppressing antenna effect violations, thereby protecting against antenna effects.

[0048] The semiconductor structure provided in this embodiment uses a custom physical cell connected between the substrate and the power network to form a charge discharge circuit. Compared with finished diode devices, the effective area for charge discharge is larger, thereby saving chip area and reducing chip cost while achieving charge discharge.

[0049] Furthermore, by employing a custom physical unit inserted between the power network and the substrate, charge can be directly discharged during ion etching, mitigating or even avoiding antenna effect violations. Compared to modifying the chip IP to address antenna effects, this approach improves the efficiency of antenna effect repair, reduces iteration cycles, and accelerates physical verification convergence, thereby improving semiconductor structure design efficiency and, to some extent, enhancing chip design efficiency.

[0050] It should be understood that a chip is fabricated based on a completed layout design, a photomask is created, and the chip is then manufactured using photolithography. After the hard IPcore is completed, the next step is to process and manufacture the semiconductor structure. The hard IPcore refers to the physical design based on semiconductor technology, which has a fixed topology and specific processes, and has been verified by both front-end and back-end development. It cannot be modified, has guaranteed performance, and is a complete set of technical documents ready for delivery to the user. Therefore, Figure 3 This is a schematic diagram of a semiconductor structure manufacturing method according to an embodiment of the present invention. Please refer to it. Figure 3 As shown, to address the antenna effect caused by the power network on a specific decap cell, this invention also provides a method for manufacturing a semiconductor structure, applicable to the fabrication of semiconductor structures such as CMOS and inverters; the method includes the following steps:

[0051] S210, Provide a semiconductor substrate.

[0052] In this embodiment, a P-type semiconductor substrate is preferred.

[0053] S220. An active region and a field region are formed on the semiconductor substrate, wherein the field region is used to isolate the active region into different parts;

[0054] The field region, sometimes also called the field oxygen region, is mainly used to isolate the active device.

[0055] The process for forming the active and field regions can be as follows: First, a thin oxide layer, such as silicon dioxide, is formed on the surface of the semiconductor substrate; then, a photoresist layer is coated on the thin oxide layer; using a mask, photolithography is performed to obtain the active region, which is used to grow the device; and dopant ions are implanted into the active region according to the type of MOS transistor.

[0056] A thin oxide layer is then grown, and a nitride layer, such as silicon nitride, is formed on this thin oxide layer. A second photolithography process is then performed to etch the field region. Field oxide, typically silicon dioxide, is grown in the field region.

[0057] S230. A first MOS transistor and a physical unit are formed in the active region and interconnected to the power network above through the upper and lower layers respectively.

[0058] The process of forming the first MOS transistor can be: implanting doped ions into the active region to form the source and drain of the MOS transistor.

[0059] Remove the nitride and active region oxide layers. Regenerate an oxide layer, generally called gate oxide; grow polysilicon on the gate oxide, photolithographically etch the polysilicon, photolithographically etch the gate, and remove excess polysilicon.

[0060] After the gate is photolithographically formed, the upper and lower layers are interconnected by fabricating an interlayer interconnect (VIA). The power network is then connected to the physical cells of the active region via the VIA and the contact transformer (CT).

[0061] S240. Connect the power network to the semiconductor substrate through the physical unit;

[0062] The power network is connected to the physical units of the active region through interlayer VIAs (vias) and CTs (contacts). The vias, also known as metallized vias, are generally formed by photolithography of a mask with predetermined holes, and then a layer of metal, such as tungsten or copper, is deposited on the wall of the via using chemical deposition to connect the interlayer metal layers.

[0063] S250. In the semiconductor etching process, the charged ions accumulated in the power network are discharged to the semiconductor substrate through physical units.

[0064] In semiconductor structure etching processes, the effects of antenna effects can be avoided by discharging the charged ions accumulated in the power network to the semiconductor substrate through physical units.

[0065] In this embodiment, the charge discharge circuit formed in step S240 is used in the semiconductor etching process to discharge the accumulated charge ions in the power network to the semiconductor substrate through the physical unit. The accumulated charge then poses no threat to the gate oxide, thereby mitigating or even avoiding damage to electronic components caused by antenna effect violations, effectively protecting electronic components such as MOSFETs. Therefore, this embodiment of the invention provides a convenient, efficient, and low-cost solution to the problem of antenna effect violations.

[0066] In some embodiments, the method further includes: connecting the semiconductor substrate to a ground point before, after, or simultaneously with connecting the power network to the semiconductor substrate via the physical unit; the step of discharging the charge ions accumulated in the power network to the semiconductor substrate via the physical unit during the semiconductor etching process (step S250) includes: after discharging the charge ions accumulated in the power network to the semiconductor substrate via the physical unit during the semiconductor etching process, releasing the charge ions to the ground point. This further protects the devices or substrate in the chip from the adverse effects of antenna effects.

[0067] In some embodiments, the physical unit is a decoupling unit. Specifically, one end of the decoupling unit is connected to a decoupling unit power supply, and the other end is grounded. The decoupling unit is formed by a capacitor composed of PMOS transistors.

[0068] One or more embodiments in this embodiment are basically similar or the same as the technical solutions disclosed in Embodiment 1 in terms of implementation principle and technical effect. They will not be described in detail here, but can be referred to each other.

[0069] The design method for suppressing antenna effects in chip power networks provided in this invention offers a novel solution to the antenna effect violation problem that exists in the top-level physical design implementation when using a specific decap cell structure during CPU physical design. This solution can save chip area, thereby reducing chip cost. Furthermore, it can further improve the efficiency of antenna effect repair, reduce iteration cycles, and accelerate physical verification convergence speed, thereby improving semiconductor structure design efficiency and, to a certain extent, chip design efficiency.

[0070] Since a chip is composed of individual transistors, the specific number of transistors in a chip varies depending on its function, but the fundamental component is always transistors; the only difference lies in the quantity. Therefore, based on the semiconductor structure provided in Embodiment 1, this invention also provides a chip, which can be found in the following embodiment. Figure 4 As shown. The chip includes: a semiconductor substrate for forming an active region and a field region on its surface, the active region for growing a device, and the field region for isolating the active region into different portions;

[0071] The first MOS transistor, grown in the active region, includes a source, a drain, and a gate. An isolation layer is provided between the source and the drain. The isolation layer is part of the field region. The gate is located above the isolation layer. The source, drain, and isolation layer form a MOM capacitor.

[0072] The source and drain are respectively connected to the semiconductor substrate;

[0073] A power network is located above the first MOS transistor, and one end of the power network is connected to the gate of the MOS transistor.

[0074] A physical unit is grown in the active region and isolated from the first MOS transistor. One end of the physical unit is connected to the power network, and the other end of the physical unit is connected to the semiconductor substrate.

[0075] It is understood that since the chip described in this embodiment is based on the same technical concept as the aforementioned semiconductor structure embodiment, the structure of the chip in this embodiment is briefly described without affecting the sufficiency of disclosure. For the specific structure, please refer to the relevant description in the aforementioned embodiment, and it will not be repeated here.

[0076] The chip provided in this invention utilizes a charge discharge circuit to dissipate accumulated charge ions during manufacturing, thus eliminating the threat of accumulated charge to the gate oxide and mitigating or even preventing damage to electronic components caused by antenna effect violations. This effectively protects electronic components such as MOSFETs. Consequently, the quality and operational reliability of the manufactured chip are improved.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate for forming an active region and a field region on its surface, the active region for growing a device, and the field region for isolating the active region into different portions; The first MOS transistor, grown in the active region, includes a source, a drain, and a gate. An isolation layer is provided between the source and the drain. The isolation layer is part of the field region. The gate is located above the isolation layer. The source, drain, and isolation layer form a MOM capacitor. The source and drain are respectively connected to the semiconductor substrate, and the gate is connected to the power network above, forming a first discharge path; A physical unit is grown in the active region and isolated from the first MOS transistor. One end of the physical unit is connected to the power network, and the other end of the physical unit is grounded through the semiconductor substrate to form a reverse-biased diode structure to form a second discharge path. The first discharge path and the second discharge path are used to discharge the charge ions accumulated in the power network. The physical unit is formed by a second MOS transistor grown in the active region. The second MOS transistor is a PMOS transistor, and an N+ type substrate contact is disposed around the second MOS transistor.

2. The semiconductor structure according to claim 1, characterized in that, The physical unit is a decoupling unit.

3. The semiconductor structure according to claim 1, characterized in that, The active region for growing the second MOS transistor is an N-well region.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor substrate is a P-type substrate, and the P-type substrate is connected to a ground point.

5. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Provide a semiconductor substrate; An active region and a field region are formed on the semiconductor substrate, wherein the field region is used to isolate the active region into different parts; A first MOS transistor and a physical unit are formed in the active region and interconnected to the upper power network through inter-layer interconnection; wherein the first MOS transistor is isolated from the physical unit; the source and drain of the first MOS transistor are respectively connected to the semiconductor substrate to form a first discharge path; The power network is connected to one end of the physical unit, and the other end of the physical unit is grounded through the semiconductor substrate to form a reverse bias diode structure to form a second discharge path; the physical unit is formed by a second MOS transistor grown in the active region, the second MOS transistor is a PMOS transistor, and an N+ type substrate contact is provided around the second MOS transistor; In the semiconductor etching process, the charged ions accumulated in the power network are discharged to the semiconductor substrate through physical units.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The method further includes connecting the semiconductor substrate to a ground point before, after, or simultaneously with connecting the power network to the semiconductor substrate via the physical unit. The step of discharging the charge ions accumulated in the power network to the semiconductor substrate through the physical unit in the semiconductor etching process includes: after discharging the charge ions accumulated in the power network to the semiconductor substrate through the physical unit in the semiconductor etching process, releasing the charge ions to the ground point.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The physical unit is a decoupling unit.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The decoupling unit is formed by a capacitor composed of PMOS transistors.

9. A chip, characterized in that, include: A semiconductor substrate for forming an active region and a field region on its surface, the active region for growing a device, and the field region for isolating the active region into different portions; The first MOS transistor, grown in the active region, includes a source, a drain, and a gate. An isolation layer is provided between the source and the drain. The isolation layer is part of the field region. The gate is located above the isolation layer. The source, drain, and isolation layer form a MOM capacitor. The source and drain are respectively connected to the semiconductor substrate to form a first discharge path; A power network is located above the first MOSFET, and one end of the power network is connected to the gate of the first MOSFET. A physical unit, grown in the active region and isolated from the first MOS transistor, has one end connected to the power network and the other end grounded through the semiconductor substrate, forming a reverse-biased diode structure to form a second discharge path. The physical unit is formed by a second MOS transistor grown in the active region, which is a PMOS transistor. An N+ type substrate contact is disposed around the second MOS transistor. The first discharge path and the second discharge path are used to discharge the charge ions accumulated in the power network.

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