An iTOF pixel circuit with a storage capacitor capable of flexible configuration

Abstract

The application discloses an iTOF pixel circuit with a flexible configuration of a storage capacitor, and relative to a traditional iTOF pixel circuit, a storage node is connected in series in the pixel circuit, which leads to the problem that the design of the pixel storage node is complex, and the voltage configuration of the storage transistor is also limited. The pixel storage capacitor of the circuit is connected in parallel in the pixel circuit, the pixel adopting the architecture can reduce the complexity of the design of the storage node, the capacitor voltage can be flexibly configured, the flexible configuration of the storage capacitor is achieved, the iTOF pixel structure is greatly optimized, the pixel layout design is facilitated, and the application range of the pixel is expanded. The SG used for opening the channel silicon gate SG is cancelled above the SGN, which ensures that the potential formed in the SGN is flat, and the potential on the charge transfer channel is always monotonic. Meanwhile, the edge potential difference formed by the SGN and the SGI region can promote the rapid transfer of charges, and effectively improves the modulation efficiency of the pixel.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and in particular relates to an iTOF pixel circuit with flexibly configurable storage capacitors. Background Technology

[0002] iTOF (Indirect Time Of Flight) is a sensor capable of measuring distance. Its principle is similar to radar; during operation, its built-in active light source projects a modulated light signal towards the target. Simultaneously, the sensor's pixels receive the reflected light signal. Finally, the received modulated signal is deduced from the intensity of the received light, and the phase difference between the projected and received signals is calculated. The spatial distance is then calculated based on this phase difference. A common iTOF sensor pixel structure with storage nodes is shown below. Figure 1 As shown;

[0003] A 2-tap iTOF pixel consists of a photodiode (PD), a modulation transistor (TX), a storage transistor (SG), and two output circuits (A and B): TG, RST, SF, and SEL (four transistors in total). In operation, the two TX transistors turn on sequentially according to the modulation frequency. During each modulation, the PD receives the light signal of that phase and converts the collected photons into electrons. These electrons are then transferred through the TX transistors to the channels under the gates of the corresponding SG transistors. After modulation, the electrons stored in the SG channels are transferred to the FD (Floating Diffusion). Finally, through the pixel's readout circuit (composed of the SF, SEL, and RST transistors), the electrons are transmitted via the COL lines to the analog circuitry within the chip for processing.

[0004] Its charge transfer path structure is as follows Figure 2 As shown, its working sequence is as follows:

[0005] 1. High voltage is applied to TG and RST transistors to turn them on, and high voltage VDD clears the charge in SGN and FD. Then TG transistor is turned off.

[0006] 2. Applying high voltage to the SG tube will pull the potential of the SGN to a high level.

[0007] 3. When a high on-state voltage is applied to TX, the photoelectrons accumulated in PD are transferred to the buried trench SGN under SG through the channel under TX, and TX is turned off to prevent electron backflow.

[0008] 4. When a high on-state voltage is applied to the TG tube, electrons in the SGN are transferred to the FD through the conductive channel under the TG. At the same time, the voltage of 5SG is reduced from the high voltage, which allows the charge to flow into the FD more completely.

[0009] 5. Once charge transfer is complete, turn off the TG tube;

[0010] In this structure, a buried trench transistor—SG—is connected in series between the TX and TG pixels, serving as both a switch and a storage device. In this operating mode, photoelectrons transfer from the PD to the SGN and then from the SGN to N+. Any non-uniform doping along the transfer path will create potential barriers and wells, leading to incomplete charge transfer, image ghosting, and a decrease in the sensor's light sensitivity in low-light environments, severely impacting sensor performance. Therefore, special optimization of the doping concentration, dosage, and relative relationships of different dopants along the charge transfer path is required. Furthermore, to ensure complete photocharge transfer, the SG's on / off voltage is limited and cannot be flexibly configured, thus limiting the SGN's capacitance and affecting the full-well operation of the sensor pixels, severely restricting the sensor's application in high-light environments. Summary of the Invention

[0011] This invention provides an iTOF pixel circuit with flexibly configurable storage capacitors, which solves the above problems.

[0012] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0013] This invention discloses an iTOF pixel circuit with flexibly configurable storage capacitor, comprising a photodiode, a first modulation transistor, a first transistor, and a first output transistor sequentially connected to one side of the photodiode, and a second modulation transistor, a second transistor, and a second output transistor sequentially connected to the other side of the photodiode; the photodiode is positioned at the midpoint between the first and second modulation transistors; a third transistor is connected between the first and second output transistors; a fourth transistor is connected between the second and third output transistors; a fifth transistor is connected to the first output transistor; a sixth transistor is connected to the second output transistor; a seventh transistor is connected between the first and second modulation transistors; and a power supply voltage is applied to the first, third, seventh, fourth, and second output transistors.

[0014] A first storage transistor is connected in parallel to the conduction circuit between the first modulation transistor and the first transistor, and a second storage transistor is connected in parallel to the conduction circuit between the second transistor and the second modulation transistor.

[0015] In this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of a pixel on one side includes a photodiode, a capacitor, a first low-resistance transistor formed by semiconductor doping on the photodiode, and a second low-resistance transistor; the first low-resistance transistor is connected to the second modulation transistor and the second transistor on both sides respectively; the capacitor is connected in parallel to the circuit in the vertical direction through the first low-resistance transistor.

[0016] In this iTOF pixel circuit, the capacitively coupled pixel structure includes a photodiode, a second modulation transistor, a capacitor, a first low-resistance transistor, and a second low-resistance transistor. The photodiode, the first low-resistance transistor, and the second low-resistance transistor are all regions in silicon, formed by silicon doping. The second modulation transistor, the second transistor, and the capacitor are polycrystalline gates or aluminum gates of semiconductors. They are isolated from the underlying silicon by silicon dioxide. When a high voltage is applied, the underlying silicon forms a conductive channel in which electrons flow.

[0017] In this iTOF pixel circuit, the accumulated photogenerated charge is transferred from the photodiode to the first low-resistance circuit. To accelerate the charge transfer, a voltage is applied to the capacitor, and the charge flow is accelerated by the edge electric field. This process includes:

[0018] S1. When a high voltage is applied to the second modulation transistor, charge flows from the photodiode to the first low-resistance transistor;

[0019] S2. When a high voltage is applied to the capacitor, the charge moves from the first low resistance to the second low resistance.

[0020] During this process, electrons flow from the photodiode with high potential energy to the first low resistance with low potential energy, and then to the second low resistance with the lowest potential energy.

[0021] When the second transistor is turned on by applying a high voltage, charge is transferred from the first low-resistance position to the connection point. After the charge transfer is complete, the second transistor is turned off. This process includes:

[0022] P1, the second transistor is turned on by applying a high voltage, and the charge in the first low-resistance transistor is first transferred to the connection position;

[0023] When a negative voltage is applied to capacitor P2, the potential energy of the second low resistance increases, and the charge flows from the second low resistance to the first low resistance, and then to the connection position.

[0024] In this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of the pixel on the other side is symmetrically arranged with the structure described above, and the process method is the same.

[0025] The present invention has the following advantages over the prior art:

[0026] (1) Compared with the traditional iTOF pixel circuit, which uses a series connection of storage nodes in the pixel circuit, resulting in complex pixel storage node design and limited storage transistor voltage configuration, this technical solution connects the pixel storage capacitors in the pixel circuit in parallel. The pixel with this architecture can reduce the complexity of storage node design, and the capacitor voltage can be flexibly configured, thereby realizing flexible configuration of storage capacitors, greatly optimizing the iTOF pixel structure, facilitating pixel layout design, and expanding the application range of pixels;

[0027] (2) In this technical solution, the silicon gate SG used to open the channel is removed above the first low-resistance SGN. This ensures that the potential formed in the first low-resistance SGN is flat, and the potential on the charge transfer channel is always monotonic. At the same time, the edge potential difference formed by the first low-resistance SGN and the second low-resistance SGI region can promote rapid charge transfer and effectively improve the modulation efficiency of the pixel. Throughout the entire operation, the second transistor SGB does not act as a switch, but only as a storage capacitor.

[0028] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a diagram of the pixel structure of a common iTOF sensor with storage nodes;

[0031] Figure 2 for Figure 1 A schematic diagram of the charge transfer path in the middle;

[0032] Figure 3 This is a schematic diagram of the pixel circuit structure of the present invention;

[0033] Figure 4 for Figure 3 The storage nodes are coupled to the cross-sectional structure of the pixels;

[0034] Figure 5 for Figure 3 Schematic diagram of the structure of a capacitor connected in parallel to a pixel;

[0035] Figure 6 A schematic diagram of the potential along the charge transfer path from PD to SGI;

[0036] Figure 7 This is a potential diagram along the charge transfer path from SGI to FD;

[0037] Figure 8 This is a top view of the iTOF pixels with parallel coupling capacitors in specific embodiment 1;

[0038] Figure 9 This is a schematic diagram of the iTOF pixel connected to the boost circuit via a coupling capacitor in specific embodiment 2.

[0039] The attached diagram lists the components represented by each number as follows:

[0040] PD - Photodiode, TXA - First modulation transistor, TGA - First transistor, SF1 - First output transistor, TXB - Second modulation transistor, SF2 - Second output transistor, FD - Connection position, RSTA - Third transistor, RSTB - Fourth transistor, SELA - Fifth transistor, SELB - Sixth transistor, ABG - Seventh transistor, SGA - First storage transistor, SGB - Second storage transistor, SG - Capacitor, SGN - First low resistance, SGI - Second low resistance, VDD - Power supply voltage. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] In the description of this invention, it should be understood that the terms "one side", "the other side", "middle", "below", etc., which indicate orientation or positional relationship, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this invention.

[0043] like Figure 1 The diagram shows an iTOF pixel circuit, a type of sensor capable of measuring distance. Its principle is similar to radar; during operation, its built-in active light source projects a modulated light signal onto the target. Simultaneously, the sensor's pixels receive the reflected light signal. Finally, the received modulated signal is deduced from the received light intensity, and the phase difference between the projected and received signals is calculated. The spatial distance is then calculated based on this phase difference. A common iTOF sensor pixel structure with a storage node is shown below. Figure 1 As shown;

[0044] A 2-tap iTOF pixel consists of a photodiode (PD), a modulation transistor (TX), a storage transistor (SG), and two output circuits (A and B): TG, RST, SF, and SEL (four transistors in total). In operation, the two TX transistors turn on sequentially according to the modulation frequency. During each modulation, the PD receives the light signal of that phase and converts the collected photons into electrons. These electrons are then transferred through the TX transistors to the channels under the gates of the corresponding SG transistors. After modulation, the electrons stored in the SG channels are transferred to the FD (Floating Diffusion). Finally, through the pixel's readout circuit (composed of the SF, SEL, and RST transistors), the electrons are transmitted via the COL lines to the analog circuitry within the chip for processing.

[0045] Its charge transfer path structure is as follows Figure 2 As shown, its working sequence is as follows:

[0046] 1. High voltage is applied to TG and RST transistors to turn them on, and high voltage VDD clears the charge in SGN and FD. Then TG transistor is turned off.

[0047] 2. Applying high voltage to the SG tube will pull the potential of the SGN to a high level.

[0048] 3. When a high on-state voltage is applied to TX, the photoelectrons accumulated in PD are transferred to the buried trench SGN under SG through the channel under TX, and TX is turned off to prevent electron backflow.

[0049] 4. When a high on-state voltage is applied to the TG tube, electrons in the SGN are transferred to the FD through the conductive channel under the TG. At the same time, the SG voltage is reduced from high voltage, which allows the charge to flow into the FD more completely.

[0050] 5. Once the charge transfer is complete, turn off the TG tube.

[0051] In this structure, a buried trench transistor—SG—is connected in series between the TX and TG pixels, serving as both a switch and a storage device. In this operating mode, photoelectrons transfer from the PD to the SGN and then from the SGN to N+. Any non-uniform doping along the transfer path will create potential barriers and wells, leading to incomplete charge transfer, image ghosting, and a decrease in the sensor's light sensitivity in low-light environments, severely impacting sensor performance. Therefore, special optimization of the doping concentration, dosage, and relative relationships of different dopants along the charge transfer path is required. Furthermore, to ensure complete photocharge transfer, the SG's on / off voltage is limited and cannot be flexibly configured, thus limiting the SGN's capacitance and affecting the full-well operation of the sensor pixels, severely restricting the sensor's application in high-light environments.

[0052] To address the issue that traditional iTOF pixel storage nodes are connected in series within the pixel circuit, leading to complex pixel storage node design and limited storage transistor voltage configuration, this invention creatively proposes a novel pixel design method. In this method, the pixel storage capacitors are connected in parallel within the pixel circuit. Pixels using this architecture reduce the complexity of storage node design, and the capacitor voltage can be flexibly configured, thus achieving flexible configuration of the storage capacitors. This significantly optimizes the iTOF pixel structure, facilitates pixel layout design, and expands the application range of pixels. The principle of the pixel circuit structure is as follows: Figure 3 As shown;

[0053] Please see Figure 3 As shown, an iTOF pixel circuit with flexibly configurable storage capacitor according to the present invention includes a photodiode PD. A first modulation transistor TXA, a first transistor TGA, and a first output transistor SF1 are sequentially connected to one side of the photodiode PD. A second modulation transistor TXB, a second transistor TGB, and a second output transistor SF2 are sequentially connected to the other side of the photodiode PD. The photodiode PD is positioned in the middle of the connection point between the first modulation transistor TXA and the second modulation transistor TXB. A third transistor RSTA is connected at the connection point FD between the first output transistor SF1 and the first transistor TGA. A fourth transistor RSTB is connected at the connection point FD between the second output transistor SF2 and the second transistor TGB. A fifth transistor SELA is connected to the first output transistor SF1, and a sixth transistor SELB is connected to the second output transistor SF2. A seventh transistor ABG is connected between the first modulation transistor TXA and the second modulation transistor TXB. A power supply voltage VDD is connected to the first output transistor SF1, the third transistor RSTA, the seventh transistor ABG, the fourth transistor RSTB, and the second output transistor SF2.

[0054] A first storage transistor SGA is connected in parallel on the conduction circuit between the first modulation transistor TXA and the first transistor TGA, and a second storage transistor SGB is connected in parallel on the conduction circuit between the second transistor TGB and the second modulation transistor TXB.

[0055] like Figure 4-5 As shown, in this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of a pixel on one side includes a photodiode PD, a capacitor SG, a first low-resistance SGN formed by semiconductor doping on the photodiode PD, and a second low-resistance SGI; the second modulation transistor TXB and the second transistor TGB are respectively connected on both sides of the first low-resistance SGN; the capacitor SG is connected in parallel to the circuit in the vertical direction through the first low-resistance SGN.

[0056] like Figure 5The diagram shows the cross-sectional structure of the storage node coupled to the pixel. In this iTOF pixel circuit, the capacitively coupled pixel structure includes a photodiode PD, a second modulation transistor TXB, a capacitor SG, a first low-resistance transistor SGN, and a second low-resistance transistor SGI. The photodiode PD, the first low-resistance transistor SGN, and the second low-resistance transistor SGI are all regions in silicon, formed by silicon doping. The second modulation transistor TXB, the second transistor TGB, and the capacitor SG are polycrystalline gates or aluminum gates of semiconductors. They are isolated from the underlying silicon by silicon dioxide. When a high voltage is applied, the underlying silicon forms a conductive channel in which electrons flow.

[0057] like Figure 6 As shown, in this iTOF pixel circuit, the accumulated photogenerated charge is transferred from the photodiode PD to the first low-resistance SGN. To accelerate the charge transfer, a voltage is applied to the capacitor SG, and the charge flow is accelerated by the edge electric field. This process includes:

[0058] S1. When a high voltage is applied to the second modulation transistor TXB, charge flows from the photodiode PD to the first low-resistance SGN.

[0059] S2, capacitor SG applies a high voltage, and charge moves from the first low-resistance SGN to the second low-resistance SGI;

[0060] During this process, electrons flow from the high potential energy photodiode PD to the low potential first low resistance SGN, and then to the lowest potential second low resistance SGI.

[0061] like Figure 7 As shown, when the second transistor TGB is turned on by applying a high voltage, charge is transferred from the first low-resistance SGN to the connection position FD. After the charge transfer is complete, the second transistor TGB is turned off. This process includes:

[0062] P1, the second transistor TGB is turned on by applying a high voltage, and the charge in the first low-resistance SGN is first transferred to the connection position FD;

[0063] P2 and capacitor SG are subjected to negative voltage, the potential energy of the second low resistance SGI is raised, and the charge flows from the second low resistance SGI to the first low resistance SGN, and then to the connection position FD.

[0064] In this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of the pixel on the other side is symmetrically arranged with the structure described above, and the process method is the same. Specific Implementation Example 1:

[0066] In this example, the pixels are connected in parallel with storage capacitors, such as the pixel top view. Figure 8 As shown, it is an iTOF pixel with parallel coupling capacitors. The pixel mainly consists of two parts:

[0067] 1. Structures used for charge collection and transfer: PD, TX, SGN, SGI, FD.

[0068] 2. Readout circuits used to read out signals: RST, SF, and SEL.

[0069] In the design, the SG gate needs to overlap with the SGN, and the SG channel is coupled through the SGI and SGN. The TG tube is designed in an L-shape, which effectively increases the width of the TG, which is more conducive to the transfer of charge from the SGI to the N+.

[0070] It should be noted that in semiconductor manufacturing processes, for the sake of convenient process design and cost savings, the doping concentration of SGI and SGN can be consistent during manufacturing, meaning they share the same photomask. This reduces the requirements for the doping order, dose, energy, and relative relationships along the path from PD to FD. When electrons transfer from PD to SGI, SG must be connected to a positive bias voltage to lower the potential energy of SGI. Conversely, when charge transfers from SGI to N+, SGI needs to be connected to a negative bias voltage to raise the potential energy of SGI.

[0071] For ease of circuit design and to reduce the use of negative voltage in the circuit, the N-type doping concentration of SGI is lower than that of SGN. During the transfer of electrons from PD to SGI, SG must be connected to a positive bias voltage to reduce the potential energy of SGI. Conversely, during the transfer of charge from SGI to N+, SGI needs to be connected to ground potential. Due to the concentration difference, the potential energy of SGI is naturally higher than that of SGN. Specific Implementation Example 2:

[0073] To further improve the capacity of the lower channel of the SG and expand the application of pixels in high-light environments, the gate voltage of the SG can be connected to a boost circuit. Its schematic diagram is shown below. Figure 9 As shown.

[0074] Connect the gate of SG to point b, and use the circuit shown in the dashed box to control the voltage of the SG gate. The working process is as follows:

[0075] In normal mode:

[0076] When s1 is turned on, SG is turned off, the SG gate voltage is set to VSG_L, the potential of SGI is at a high potential, and the potential energy decreases.

[0077] S4 is turned on, SG is turned on, the SG gate voltage is set to VSG_L; the potential of SGI is at a low potential, and the potential energy rises.

[0078] In this example, in order to further increase the gate voltage of SG when it is turned on,

[0079] S1 is open, SG is closed, and S2 is also open. Both substrates a and b of the capacitor are placed at potential VSG_L.

[0080] With S2 off and S4 on, capacitor substrate b is at a high potential VSG_H (the highest voltage in normal mode).

[0081] In this example, an additional step is added.

[0082] With S4 off and S3 on, the potential of capacitor substrate a rises from VSG_L to Vin.

[0083] At substrate b, the voltage will be raised to VSG_H+(Vin-VSG_L);

[0084] Because the gate voltage of SG is raised by Vin-VSG_L, its lower channel potential will increase and the potential energy will decrease, thereby increasing the capacitance of SG. This allows the lower channel of SG to store more photogenerated electrons, thus increasing the image sensor's ability to operate in strong light environments.

[0085] Among them, S1-S4 are switches made of MOS transistors, and VSG_L VSG_H Vin is the voltage.

[0086] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An iTOF pixel circuit with flexibly configurable storage capacitor, comprising a photodiode (PD), a first modulation transistor (TXA), a first transistor (TGA), and a first output transistor (SF1) sequentially connected on one side of the photodiode (PD), and a second modulation transistor (TXB), a second transistor (TGB), and a second output transistor (SF2) sequentially connected on the other side of the photodiode (PD); the photodiode (PD) is positioned at the midpoint between the connection points of the first modulation transistor (TXA) and the second modulation transistor (TXB); a third transistor is connected at the connection point (FD) between the first output transistor (SF1) and the first transistor (TGA). The transistor consists of a body transistor (RSTA); a fourth transistor (RSTB) is connected at the connection point (FD) between the second output transistor (SF2) and the second transistor (TGB); a fifth transistor (SELA) is connected to the first output transistor (SF1), and a sixth transistor (SELB) is connected to the second output transistor (SF2); a seventh transistor (ABG) is connected between the first modulation transistor (TXA) and the second modulation transistor (TXB); the first output transistor (SF1), the third transistor (RSTA), the seventh transistor (ABG), the fourth transistor (RSTB), and the second output transistor (SF2) are all connected to a power supply voltage (VDD), characterized in that: A first storage transistor (SGA) is connected in parallel on the conduction circuit between the first modulation transistor (TXA) and the first transistor (TGA), and a second storage transistor (SGB) is connected in parallel on the conduction circuit between the second transistor (TGB) and the second modulation transistor (TXB). In this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of a pixel on one side includes a photodiode (PD), a capacitor (SG), a first low-resistance transistor (SGN) and a second low-resistance transistor (SGI) formed by semiconductor doping on the photodiode (PD); the second modulation transistor (TXB) and the second transistor (TGB) are respectively connected on both sides of the first low-resistance transistor (SGN); the capacitor (SG) is connected in parallel to the circuit in the vertical direction through the first low-resistance transistor (SGN); In this iTOF pixel circuit, the capacitively coupled pixel structure includes a photodiode (PD), a second modulation transistor (TXB), a capacitor (SG), a first low-resistance transistor (SGN), and a second low-resistance transistor (SGI). The photodiode (PD), first low-resistance transistor (SGN), and second low-resistance transistor (SGI) are all regions in silicon, formed by silicon doping. The second modulation transistor (TXB), second transistor (TXB), and capacitor (SG) are polycrystalline gates or aluminum gates in semiconductors. Silicon dioxide acts as an insulator between them and the underlying silicon. When a high voltage is applied, the underlying silicon forms a conductive channel, allowing electrons to flow within it. In this iTOF pixel circuit, the accumulated photogenerated charge is transferred from the photodiode (PD) to the first low-resistance (SGN). To accelerate charge transfer, a voltage is applied to the capacitor (SG), and the charge flow is accelerated through the edge electric field. This process includes: S1. When a high voltage is applied to the second modulation transistor (TXB), charge flows from the photodiode (PD) to the first low-resistance transistor (SGN); S2, a high voltage is applied to the capacitor (SG), and the charge moves from the first low resistance (SGN) to the second low resistance (SGI); During this process, electrons flow from the high potential photodiode (PD) to the low potential first low resistance (SGN), and then to the lowest potential second low resistance (SGI). When the second transistor (TGB) is turned on by applying a high voltage, charge is transferred from the first low-resistance transistor (SGN) to the connection location (FD). After the charge transfer is complete, the second transistor (TGB) is turned off. This process includes: P1, the second transistor (TGB) is turned on by applying a high voltage, and the charge in the first low-resistance transistor (SGN) is first transferred to the connection position (FD); When a negative voltage is applied to P2 and capacitor (SG), the potential energy of the second low resistance (SGI) is raised, and the charge flows from the second low resistance (SGI) to the first low resistance (SGN), and then to the connection position (FD). In this iTOF pixel circuit, the charge coupling structure corresponding to the charge path of the pixel on the other side is symmetrically arranged with the structure described above, and the process method is the same.

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