Semiconductor device and method of manufacturing a semiconductor device

Abstract

Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate having a gate region and a contact region; a buried insulating layer formed on the substrate; a fin-type insulating pattern formed on the buried insulating layer and extending in a first horizontal direction; a lower metal layer covering upper and side surfaces of the fin-type insulating pattern in the contact region; a channel layer covering upper and side surfaces of the lower metal layer in the contact region and covering upper and side surfaces of the fin-type insulating pattern in the gate region; a gate pattern disposed on the channel layer in the gate region and extending in a second horizontal direction; and a source / drain contact pattern disposed on the channel layer in the contact region. The lower metal layer includes a Ti-based metal. The channel layer includes an oxide semiconductor material.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0144316, filed on October 27, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure provide a semiconductor device having a multioxide semiconductor channel layer and a method for manufacturing the semiconductor device. Background Technology

[0004] Oxide semiconductors typically have lower carrier mobilities than silicon bulk. This can improve the cutoff characteristics of transistors with oxide semiconductor channels. However, due to the low carrier mobility, the transistors may have lower drive capability and higher resistance. Therefore, it may be difficult to apply such transistors to highly integrated and high-performance semiconductor devices. Summary of the Invention

[0005] The various embodiments disclosed in this invention provide a transistor having a multi-oxide-semiconductor channel, and a semiconductor device including the transistor.

[0006] Various embodiments of this disclosure provide a method for manufacturing a transistor having a multi-oxide-semiconductor channel, and a method for manufacturing a semiconductor device including the transistor.

[0007] A semiconductor device according to an embodiment of the present disclosure includes: a substrate having a gate region and a contact region; a buried insulating layer formed on the substrate; a fin-type insulating pattern formed on the buried insulating layer and extending in a first horizontal direction; a lower metal layer covering the upper surface and side surface of the fin-type insulating pattern in the contact region; a channel layer covering the upper surface and side surface of the lower metal layer in the contact region, and covering the upper surface and side surface of the fin-type insulating pattern in the gate region; a gate pattern disposed on the channel layer in the gate region and extending in a second horizontal direction; and a source / drain contact pattern disposed on the channel layer in the contact region. The lower metal layer comprises a Ti-based metal. The channel layer comprises an oxide semiconductor material.

[0008] A semiconductor device according to an embodiment of the present disclosure includes: a substrate having a gate region and a contact region; a fin-type insulating pattern extending in a first horizontal direction on the substrate; a lower Ti-based metal layer covering the upper surface and side surface of the fin-type insulating pattern in the contact region; an oxide semiconductor layer covering the upper surface and side surface of the lower Ti-based metal layer in the contact region, and covering the upper surface and side surface of the fin-type insulating pattern in the gate region; a buffer insulating layer on the oxide semiconductor layer; a gate pattern extending in a second horizontal direction on the oxide semiconductor layer in the gate region; and a source / drain contact pattern on the oxide semiconductor layer in the contact region.

[0009] A semiconductor device according to an embodiment of the present disclosure includes: a substrate having a gate region and a contact region; a buried insulating layer on the substrate; a fin-type insulating pattern on the buried insulating layer, the fin-type insulating pattern extending in a first horizontal direction and formed in the gate region and the contact region; a lower Ti-based metal layer on the upper surface and side surface of the fin-type insulating pattern in the contact region; a channel layer formed on the fin-type insulating pattern in the gate region and on the lower Ti-based metal layer in the contact region; a gate electrode extending in a second horizontal direction and formed on the channel layer in the gate region; an upper Ti-based metal layer on the channel layer in the contact region; and a source / drain contact pattern on the upper Ti-based metal layer in the contact region.

[0010] A method of manufacturing a semiconductor device according to an embodiment of the present disclosure includes: providing a substrate having a gate region and a contact region; forming a fin-type insulating pattern extending in a first horizontal direction on the substrate; forming a lower Ti-based metal layer on an upper surface and a side surface of the fin-type insulating pattern in the contact region; forming an oxide semiconductor layer on the lower Ti-based metal layer and the upper surface and a side surface of the fin-type insulating pattern; forming a sacrificial gate electrode extending in a second horizontal direction on the oxide semiconductor layer in the gate region; forming a lower interlayer insulating layer on the oxide semiconductor layer in the contact region; forming a gate trench in the gate region by removing the sacrificial gate electrode; forming a gate electrode in the gate trench; forming a contact slit in the contact region to expose a channel layer; and forming a source / drain contact pattern on the channel layer exposed in the contact slit. Attached Figure Description

[0011] Figure 1 This is a perspective view schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 2A to 2C The semiconductor device according to embodiments of this disclosure is along Figure 1 The longitudinal cross-sectional views shown are taken from lines I-I', II-II', and III-III'.

[0013] Figures 3A to 3C These are the edges of the semiconductor devices according to embodiments of this disclosure. Figure 1 The longitudinal cross-sectional views shown are taken from lines I-I', II-II', and III-III'.

[0014] Figures 4A to 4C These are the edges of the semiconductor devices according to embodiments of this disclosure. Figure 1 The longitudinal cross-sectional views shown are taken from lines I-I', II-II', and III-III'.

[0015] Figures 5A to 12C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 13A to 14C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 15A to 15C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0018] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure exhaustive and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the invention.

[0019] It should be understood that although the terms "first" and / or "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. Similarly, the second element may also be referred to as the first element.

[0020] Other expressions explaining the relationship between elements, such as “between,” “directly between,” “adjacent,” or “directly adjacent,” should be interpreted in the same way.

[0021] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer without an intermediate layer, but also to the case where an intermediate layer is formed between the first and second layers. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly" on, "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers.

[0022] Figure 1 This is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure. (Refer to...) Figure 1 The semiconductor device according to embodiments of the present disclosure may include a buried insulating layer 15 integrally formed on a substrate 10, a fin-shaped insulating pattern 20 formed on the buried insulating layer 15 having a linear shape extending in a first horizontal direction X on the buried insulating layer 15, a source / drain pattern 30 covering a portion of the upper surface and a portion of the side surface of the fin-shaped insulating pattern 20, and a gate pattern 50 covering a portion of the upper surface and a portion of the side surface of the fin-shaped insulating pattern 20 on the buried insulating layer 15 extending in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. In one embodiment, the source / drain pattern 30 and the gate pattern 50 may each have a cross-section of the Greek letter pi (cut at right angles to the first horizontal direction X), with the bottom surface of the legs of pi contacting the top surface of the buried insulating layer 15.

[0023] Figures 2A to 2C The semiconductor device according to embodiments of this disclosure is along Figure 1 The diagram shows longitudinal cross-sectional views taken along lines I-I', II-II', and III-III'. (Refer to...) Figures 2A to 2C The semiconductor device according to embodiments of the present disclosure may include a buried insulating layer 15, a fin insulating pattern 20, a source / drain pattern 30, a gate pattern 50, a lower source / drain contact pattern 61, an upper source / drain contact pattern 62, a gate contact pattern 63, and insulating layers 41, 42, 43, and 44 on a substrate 10.

[0024] Substrate 10 may include a semiconductor layer such as a silicon wafer. In some embodiments, substrate 10 may include one of a compound semiconductor layer, an epitaxially grown silicon layer, silicon-on-insulator (SOI), or other semiconductor material layers. Substrate 10 may have a gate region GA and a contact region CA. Gate pattern 50 and gate contact pattern 63 may be formed in the gate region GA. Source / drain pattern 30, lower source / drain contact pattern 61, and upper source / drain contact pattern 62 may be formed in the contact region CA.

[0025] The buried insulating layer 15 can be integrally formed on the substrate 10, meaning that the entire bottom surface of the buried insulating layer 15 can contact the top surface of the substrate 10. The buried insulating layer 15 may include at least one insulating material such as silicon oxide (SiO2), silicon oxycarbide (SiOC), and silicon nitride (SiN).

[0026] The fin-shaped insulating pattern 20 may have a fin-shaped or strip-shaped structure that protrudes from the upper surface of the embedded insulating layer 15 and extends in a first horizontal direction X. The fin-shaped insulating pattern 20 may include an insulating material such as silicon oxide (SiO2).

[0027] The source / drain pattern 30 may cover the upper and side surfaces of the fin insulating pattern 20 in the contact region CA. The source / drain pattern 30 may include a lower metal layer 31, a channel layer 32, and a buffer insulating layer 33. The lower metal layer 31 may be formed directly on the upper and side surfaces of the fin insulating pattern 20. The lower metal layer 31 may include a Ti (titanium)-based metal. For example, the lower metal layer 31 may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), and titanium aluminum nitride (TiAlN). In one embodiment, the lower metal layer 31 may include either titanium carbide (TiC) or titanium aluminum (TiAl). The channel layer 32 may be formed directly on the lower metal layer 31. The channel layer 32 may include an oxide semiconductor material. For example, the channel layer 32 may include at least one of InGaZnO, InGaZnSnO, InSnO, InSnZnO, SiInGaZnO, SiInGaZnSnO, SiInSnO, SiInSnO, AlGaZnO, AlGaZnSnO, AlSnO, AlSnZnO, SiAlGaZnO, SiAlGaZnO, SiAlGaZnSnO, SiAlSnO, SiAlSnO, SiAlSnZnO, InGaMgO, InGaMgSnO, InSnMgO, SiInGaMgO, SiInGaMgSnO, SiInSnMgO, AlGaMgO, AlGaMgSnO, AlSnMgO, SiAlGaMgO, SiAlGaMgSnO, SiAlSnMgO, SiAlGaMgO, SiAlSnMgO, or SiAlSnMgO. A buffer insulating layer 33 may be formed on the channel layer 32. The buffer insulating layer 33 may include silicon oxide (SiO2) or aluminum oxide (Al2O3). A portion of the buffer insulation layer 33 can be removed so that the channel layer 32 and the lower source / drain contact pattern 61 can contact each other in the contact area CA.

[0028] Gate pattern 50 may extend in the gate region GA around the upper and side surfaces of fin-type insulating pattern 20 and in the second horizontal direction Y. Gate pattern 50 may be formed on buffer insulating layer 33 in gate region GA. Gate pattern 50 may include gate insulating layer 52 and gate electrode 55. In one embodiment, gate insulating layer 52 may be formed to at least partially contact the upper surface of buffer insulating layer 33. Gate electrode 55 may be formed on gate insulating layer 52. Gate insulating layer 52 may include at least one of a hafnium (Hf) compound (such as hafnium oxide (HfO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), alumina hafnium (HfAlO), or alumina hafnium oxynitride (HfAlON)) or a compound containing lanthanum (La), erbium (Er), strontium (Sr), barium (Ba), or zirconium (Zr). Gate electrode 55 may include at least one of polysilicon, silicide, metal, metal alloy, and metal compound. In one embodiment, a barrier metal layer may also be formed between the gate insulating layer 52 and the gate electrode 55. For example, the barrier metal layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN).

[0029] Insulating layers 41, 42, 43, and 44 may include a lower interlayer insulating layer 41, a cap insulating layer 42, an intermediate interlayer insulating layer 43, and an upper interlayer insulating layer 44. The lower interlayer insulating layer 41 may be formed on the buried insulating layer 15 to surround the lower source / drain contact pattern 61 and the gate pattern 50. The cap insulating layer 42 may be formed on the upper surface of the lower interlayer insulating layer 41. The upper interlayer insulating layer 44 may be formed on the cap insulating layer 42 to surround the upper source / drain contact pattern 62 and the gate contact pattern 63. The lower and upper interlayer insulating layers 41 and 44 may include silicon oxide-based insulating materials, such as silicon oxide (SiO2), silicon hydroxide (SiHO), silicon carbide (SiOC), or silicon oxycarbide (SiHOC). The cap insulating layer 42 may include an insulating material that is denser and harder than the lower and upper interlayer insulating layers 41 and 44. For example, the cover insulating layer 42 may include silicon nitride (SiN).

[0030] The lower source / drain contact pattern 61 may have a wall shape, wherein the width in the second horizontal direction Y is several times the width in the first horizontal direction X, and the upper source / drain contact pattern 62 may have a column shape, wherein the width in the second horizontal direction Y is similar to the width in the first horizontal direction X. The lower source / drain contact pattern 61 may include a lower source / drain contact barrier layer 61a and a lower source / drain contact plug 61b. The lower source / drain contact barrier layer 61a may surround the side surface of the lower source / drain contact plug 61b. The lower source / drain contact barrier layer 61a may contact the channel layer 32. The lower source / drain contact barrier layer 61a may include titanium (Ti). For example, the lower source / drain contact barrier layer 61a may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). The lower source / drain contact plug 61b may include at least one of polysilicon, silicide, metal, metal alloy, or metal compound. The upper source / drain contact pattern 62 may include an upper source / drain contact barrier layer 62a and an upper source / drain contact plug 62b. The upper source / drain contact barrier layer 62a may contact the upper source / drain contact plug 62b. The upper source / drain contact barrier layer 62a may cover the lower surface and side surface of the upper source / drain contact plug 62b. The upper source / drain contact barrier layer 62a may include a barrier metal, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The upper source / drain contact plug 62b may include at least one of polysilicon, silicide, metal, metal alloy, or metal compound.

[0031] Gate contact pattern 63 may be connected to gate electrode 55. Gate contact pattern 63 may be cylindrical. Gate contact pattern 63 may include gate contact barrier layer 63a and gate contact plug 63b. Gate contact barrier layer 63a may cover the lower surface and side surface of gate contact plug 63b. Gate contact barrier layer 63a may include a barrier metal, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). Gate contact plug 63b may include at least one of polysilicon, silicide, metal, metal alloy, and metal compound.

[0032] Figures 3A to 3C These are the edges of the semiconductor devices according to embodiments of this disclosure. Figure 1 The diagram shows longitudinal cross-sectional views taken along lines I-I', II-II', and III-III'. (Refer to...) Figures 3A to 3C , and reference Figures 2A to 2CCompared to the described semiconductor device, the semiconductor device according to embodiments of this disclosure may further include an interface insulating layer 51 formed between the channel layer 32 and the gate insulating layer 52. Figures 2A to 2C In the semiconductor device shown, the interface insulating layer 51 can replace the buffer insulating layer 33 between the lower metal layer 31 and the gate insulating layer 52 in the gate region GA. That is, the interface insulating layer 51 can be formed in the region where the buffer insulating layer 33 has been removed. The interface insulating layer 51 may include aluminum oxide (Al2O3). The buffer insulating layer 33 may include silicon oxide (SiO2). Reference numerals not described may be found in the figures. Figures 2A to 2C To understand.

[0033] Figures 4A to 4C These are the edges of the semiconductor devices according to embodiments of this disclosure. Figure 1 The diagram shows longitudinal cross-sectional views taken along lines I-I', II-II', and III-III'. (Refer to...) Figures 4A to 4C , and reference Figures 2A to 2C The semiconductor devices described and references Figures 3A to 3C Compared to the described semiconductor device, the semiconductor device according to embodiments of this disclosure may further include an upper metal layer 34 surrounding the lower surface and side surfaces of the lower source / drain contact pattern 61. The upper metal layer 34 may be formed as a portion surrounding the upper surface and side surfaces of the channel layer 32 in the contact region CA and the upper surface of the buried insulating layer 15. The upper metal layer 34 may be horizontally spaced from the gate pattern 50. Therefore, the parasitic capacitance between the lower source / drain contact pattern 61 and the gate pattern 50 caused by the upper metal layer 34 can be reduced. The upper metal layer 34 may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), and titanium aluminum nitride (TiAlN). In one embodiment, the upper metal layer 34 may include one of titanium carbide (TiC) or titanium aluminum (TiAl). For example, the lower metal layer 31 and the upper metal layer 34 may be formed of the same material. (Refer to...) Figures 4A to 4C For reference to the undescribed figure labels, please refer to the following. Figures 2A to 2C and Figures 3A to 3C To understand.

[0034] The semiconductor device according to embodiments of the present disclosure can have a multi-channel structure having a three-dimensional structure covering the side and top surfaces of the fin-type insulating pattern 20. Therefore, the driving capability of the transistor can be improved.

[0035] Oxide semiconductor materials have lower carrier mobility than intrinsic silicon. Therefore, when using oxide semiconductor materials as the channel material of a transistor, the transistor's cutoff current can be reduced. However, oxide semiconductor materials have high resistance due to their low carrier concentration and carrier mobility. The semiconductor device according to this embodiment may include a lower metal layer 31 disposed below a channel layer 32 comprising an oxide semiconductor material. The lower metal layer 31 may include a Ti-based metal layer. The Ti-based metal layer can provide oxygen vacancies to the oxide semiconductor material through a scavenging phenomenon. Oxygen vacancies can increase the carrier concentration. Therefore, the resistance of the channel layer 32 corresponding to the source / drain can be reduced and the conductivity can be increased.

[0036] The semiconductor device according to this embodiment may further include an upper metal layer 34 comprising a Ti-based metal. Therefore, the conductivity of the oxide semiconductor channel layer 32 can be further improved. Furthermore, the contact resistance between the channel layer 32 and the lower source / drain contact pattern 61 can be reduced.

[0037] Figures 5A to 12C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 5A to 12A It is along Figure 1 The longitudinal cross-section diagram taken from line I-I' in the diagram. Figures 5B to 12B It is along Figure 1 The longitudinal cross-section diagram taken from line II-II' in the diagram, and Figures 5C to 12C It is along Figure 1 The longitudinal cross-section diagram taken from line III-III' in the figure.

[0038] Reference Figures 5A to 5C A method for manufacturing a semiconductor device according to embodiments of the present disclosure may include the following steps: forming a buried insulating layer 15 on a substrate 10; forming a fin-shaped insulating pattern 20 on the buried insulating layer 15; and forming a lower metal layer 31 on the fin-shaped insulating pattern 20.

[0039] Substrate 10 may include a semiconductor layer such as a silicon wafer. Substrate 10 may have a gate region GA and a contact region CA.

[0040] Forming the buried insulating layer 15 may include integrally forming an insulating material such as silicon oxide (SiO2) on the substrate 10 by performing a deposition process. In one embodiment, the buried insulating layer 15 may include multiple insulating layers.

[0041] Forming the fin-shaped insulating pattern 20 may include forming an insulating material such as (SiO2) having fin-shaped or strip-shaped extensions in a first horizontal direction X by performing a deposition process, a photolithography process, and an etching process.

[0042] Forming the lower metal layer 31 may include forming a Ti-based metal layer covering the fin-shaped insulating pattern 20 in the contact region CA by performing a deposition process and a patterning process. The Ti-based metal layer may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), or titanium aluminum (TiAl). The lower metal layer 31 may cover the side and top surfaces of the fin-shaped insulating pattern 20 in the contact region CA in the form of pads. In one embodiment, the lower metal layer 31 may partially extend to the top surface of the buried insulating layer 15 in the contact region CA. In the gate region GA, the lower metal layer 31 may not cover the fin-shaped insulating pattern 20. That is, the lower metal layer 31 may not be formed in the gate region GA.

[0043] Reference Figures 6A to 6C The method may include the following steps: forming a channel layer 32 on a lower metal layer 31 and an exposed fin-shaped insulating pattern 20, and forming a buffer insulating layer 33 on the channel layer 32. Forming the channel layer 32 may include: integrally forming an oxide semiconductor material by performing a deposition process. The oxide semiconductor material may include indium (In), gallium (Ga), and zinc (Zn). For example, the oxide semiconductor material may include at least one of InGaZnO, InGaZnSnO, InSnO, InSnZnO, SiInGaZnO, SiInGaZnSnO, SiInSnO, SiInSnZnO, AlGaZnO, AlGaZnSnO, AlSnO, AlSnZnO, SiAlGaZnO, SiAlGaZnO, SiAlGaZnSnO, SiAlSnO, SiAlSnZnO, InGaMgO, InGaMgSnO, InSnMgO, SiInGaMgO, SiInGaMgSnO, SiInSnMgO, AlGaMgO, AlGaMgSnO, AlSnMgO, SiAlGaMgO, SiAlGaMgSnO, SiAlSnMgO, or other oxide-based semiconductor materials. Forming the buffer insulating layer 33 may include integrally forming an insulating material such as silicon oxide (SiO2) or aluminum oxide (Al2O3) on the channel layer 32 by performing a deposition process. In one embodiment, the channel layer 32 and the buffer insulating layer 33 may be formed to extend partially to the upper surface of the buried insulating layer 15, respectively. The method may also include removing the channel layer 32 and the buffer insulating layer 33 on the buried insulating layer 15 by performing a patterning process. In one embodiment, the channel layer 32 and the buffer insulating layer 33 may not be removed and may be partially retained on the buried insulating layer 15.

[0044] Reference Figures 7A to 7CThe method may further include forming a sacrificial gate electrode 35 and a lower interlayer insulating layer 41. Forming the sacrificial gate electrode 35 may include forming polysilicon on a buffer insulating layer 33 and a buried insulating layer 15 in the gate region GA by performing a deposition process and a patterning process. Forming the lower interlayer insulating layer 41 may include integrally forming an insulating material such as silicon oxide (SiO2) or silicon carbide (SiOC) by performing a deposition process, and planarizing the insulating material by performing a planarization process such as chemical mechanical polishing (CMP). Through the planarization process, the upper surface of the sacrificial gate electrode 35 and the upper surface of the lower interlayer insulating layer 41 may be coplanar.

[0045] Reference Figures 8A to 8C The method may further include forming a gate trench GT in the gate region GA by removing the sacrificial gate electrode 35. The buffer insulating layer 33 and the buried insulating layer 15 may be exposed in the gate trench GT.

[0046] Reference Figures 9A to 9C The method may further include forming a gate insulating layer 52 and a gate electrode 55 in a gate trench GT. Forming the gate insulating layer 52 may include conformally forming a high-k material on the bottom and inner walls of the gate trench GT by performing a deposition process.

[0047] The gate insulating layer 52 may include at least one of a hafnium (Hf) compound (such as hafnium oxide (HfO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), hafnium aluminum oxide (HfAlO), or hafnium oxynitride aluminum (HfAlON)) or a compound containing lanthanum (La), erbium (Er), strontium (Sr), barium (Ba), or zirconium (Zr). The gate electrode 55 may include polysilicon, silicide, metal, metal alloy, or metal compound. The method may further include coplanarizing the upper surface of the lower interlayer insulating layer 41, the upper surface of the gate insulating layer 52, and the upper surface of the gate electrode 55 by performing a planarization process such as CMP.

[0048] Reference Figures 10A to 10CThe method may further include the following steps: forming a capping insulating layer 42 on the lower interlayer insulating layer 41 and the gate electrode 55; forming an intermediate interlayer insulating layer 43 on the capping insulating layer 42; and forming a lower source / drain contact slit CS of the channel layer 32 in the exposed contact region CA. Forming the capping insulating layer 42 may include: integrally forming a material that is denser and harder than the lower interlayer insulating layer 41 by performing a deposition process. The capping insulating layer 42 may include a barrier insulating material that prevents reaction between the gate electrode 55 and the upper interlayer insulating layer 44. For example, the capping insulating layer 42 may include silicon nitride (SiN). Forming the intermediate interlayer insulating layer 43 may include: forming an insulating material such as silicon oxide (SiO2) or silicon carbide (SiOC) on the capping insulating layer 42 by performing a deposition process. Forming the lower source / drain contact slit CS may include selectively etching the intermediate interlayer insulating layer 43, the cap insulating layer 42, and the lower interlayer insulating layer 41 to expose the buffer insulating layer 33, and removing the exposed buffer insulating layer 33 to expose the channel layer 32. The lower source / drain contact slit CS may be horizontally spaced from the gate electrode 55. The lower source / drain contact slit CS may expose the surface of the channel layer 32 formed on the sidewalls of the fin insulating pattern 20 and the upper surface of the buried insulating layer 15.

[0049] Reference Figures 11A to 11C The method may further include forming a lower source / drain contact barrier layer 61a in the lower source / drain contact slit CS. Forming the lower source / drain contact barrier layer 61a may include conformally forming a metal layer comprising titanium (Ti) on the inner wall and bottom surface of the lower source / drain contact slit CS by performing a deposition process. Therefore, the lower source / drain contact barrier layer 61a can be directly formed on the channel layer 32 exposed in the lower source / drain contact slit CS. For example, the lower source / drain contact barrier layer 61a may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), or titanium aluminum nitride (TiAlN). In one embodiment, the lower source / drain contact barrier layer 61a may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or other barrier metals.

[0050] Reference Figures 12A to 12C The method may further include forming a lower source / drain contact plug 61b by filling the lower source / drain contact slit CS with a conductive material. The lower source / drain contact plug 61b may include a metal such as tungsten (W). The method may further include making the upper surface of the lower source / drain contact plug 61b and the upper surface of the intermediate interlayer insulating layer 43 coplanar by performing a planarization process such as CMP.

[0051] Subsequently, further reference Figures 2A to 2CThe method may include the following steps: forming an upper interlayer insulating layer 44, and forming an upper source / drain contact pattern 62 and a gate contact pattern 63. Forming the upper interlayer insulating layer 44 may include: forming an insulating material such as silicon oxide (SiO2) or silicon carbide (SiOC) by performing a deposition process. Forming the upper source / drain contact pattern 62 may include: performing an etching process to form a hole perpendicularly penetrating the upper interlayer insulating layer 44 to expose the upper surface of the lower source / drain contact pattern 61; performing a deposition process to conformally form an upper source / drain contact barrier layer 62a on the inner wall and bottom surface of the hole; and performing a filling process to form an upper source / drain contact plug 62b filling the hole. Forming the gate contact pattern 63 may include: forming a hole perpendicularly penetrating the upper interlayer insulating layer 44 to expose the gate electrode 55 by performing an etching process; conformally forming a gate contact barrier layer 63a on the inner wall and bottom surface of the hole by performing a deposition process; and forming a gate contact plug 63b filling the hole by performing a filling process. The upper source / drain contact barrier layer 62a and the gate contact barrier layer 63a may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and other barrier metals. The upper source / drain contact plug 62b and the gate contact plug 63b may include a metal such as tungsten (W).

[0052] Figures 13A to 14C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 13A and Figure 14A It is along Figure 1 The longitudinal cross-section diagram taken from line I-I'. Figure 13B and Figure 14B It is along Figure 1 The longitudinal section view taken from line II-II', and Figure 13C and Figure 14C It is along Figure 1 The longitudinal cross-section diagram taken from line III-III'.

[0053] Reference Figures 13A to 13C A method for manufacturing a semiconductor device according to embodiments of the present disclosure may include: performing a procedure as described above. Figures 5A to 8C The process described, and the channel layer 32 in the gate trench GT exposed by removing the buffer insulating layer 33 exposed in the gate trench GT.

[0054] Reference Figures 14A to 14C The method may further include forming an interface insulating layer 51 on the exposed trench layer 32. The interface insulating layer 51 may include at least one of silicon oxide (SiO2), aluminum oxide (Al2O3), or other insulating materials. In one embodiment, the interface insulating layer 51 may extend onto the embedded insulating layer 15.

[0055] Subsequently, the method also includes: executing the reference Figures 9A to 12C The described process, and references Figures 3A to 3C An upper interlayer insulating layer 44 is formed, and an upper source / drain contact pattern 62 and a gate contact pattern 63 are formed.

[0056] Figures 15A to 15C This is a longitudinal cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 15A It is along Figure 1 The longitudinal cross-section diagram taken from line I-I'. Figure 15B It is along Figure 1 The longitudinal section view taken from line II-II', and Figure 15C It is along Figure 1 The longitudinal cross-sectional view taken from line III-III'. (Refer to...) Figures 15A to 15C A method for manufacturing a semiconductor device according to embodiments of the present disclosure may include: performing a procedure as described above. Figures 5A to 10C The described process involves forming an upper metal layer 34 on the bottom surface of the lower source / drain contact slit CS. The upper metal layer 34 can be formed on the channel layer 32 and the buried insulating layer 15 exposed through the lower source / drain contact slit CS. The upper metal layer 34 can also be conformally formed on the inner wall of the lower source / drain contact slit CS.

[0057] Subsequently, the method also includes: executing the reference Figures 11A to 12C The described process, refer to Figures 4A to 4C An upper interlayer insulating layer 44 is formed, and an upper source / drain contact pattern 62 and a gate contact pattern 63 are formed.

[0058] According to embodiments of this disclosure, a semiconductor device may include a transistor having multiple oxide semiconductor channels. Because the transistor has oxide semiconductor channels, it can have low cutoff current characteristics. Because the transistor has multiple channels, it can have excellent drive capability. The resistance of the oxide semiconductor channels cleared by the Ti-based metal can be reduced. Therefore, the resistance of the source / drain contacts can be reduced.

[0059] Although the present invention has been specifically described with reference to the preferred embodiments described above, it should be noted that the embodiments described above are for illustrative purposes and not for limiting purposes. Furthermore, those skilled in the art will understand that various embodiments are possible within the scope of the present invention.

Claims

1. A semiconductor device, comprising: The substrate has a gate region and a contact region; An insulating layer is embedded and formed on the substrate; A fin-shaped insulating pattern is formed on the embedded insulating layer and extends in a first horizontal direction; A lower metal layer covers the upper and side surfaces of the fin-shaped insulating pattern in the contact area; A channel layer covers the upper and side surfaces of the lower metal layer in the contact region, and also covers the upper and side surfaces of the fin insulating pattern in the gate region; A gate pattern is disposed on the channel layer in the gate region and extends in a second horizontal direction; as well as Source / drain contact patterns are disposed on the channel layer in the contact area. in: The lower metal layer comprises a Ti-based metal, and The channel layer comprises an oxide semiconductor material.

2. The semiconductor device according to claim 1, wherein, The Ti-based metal includes at least one of TiC or TiAl.

3. The semiconductor device according to claim 1, in, The gate pattern includes: Interface insulating layer; The gate insulating layer on the interface insulating layer; and The gate electrode on the gate insulating layer.

4. The semiconductor device according to claim 1, further comprising: An upper metal layer is disposed between the channel layer and the source / drain contact pattern, and is horizontally spaced from the gate pattern in the contact region. The upper metal layer includes the Ti-based metal.

5. The semiconductor device according to claim 4, wherein, The upper metal layer surrounds the upper side and side surface of the channel layer, a portion of the upper surface of the buried insulating layer, and the lower and side surfaces of the source / drain contact pattern.

6. The semiconductor device according to claim 5, wherein: The source / drain contact pattern includes a source / drain contact barrier layer and a source / drain contact plug, and The source / drain contact barrier layer surrounds the bottom and side surfaces of the source / drain contact plug.

7. The semiconductor device according to claim 5, wherein: The source / drain contact pattern includes a lower source / drain contact pattern and an upper source / drain contact pattern, and The width of the lower source / drain contact pattern in the second horizontal direction is greater than the width of the lower source / drain contact pattern in the first horizontal direction.

8. The semiconductor device according to claim 1, further comprising: A buffer insulating layer is provided on the channel layer; as well as A lower interlayer insulating layer, on top of the buffer insulating layer, surrounds the side surface of the source / drain contact pattern. in: The buffer insulating layer comprises silicon oxide or aluminum oxide, and The lower interlayer insulating layer includes silicon oxide or silicon carbide.

9. The semiconductor device according to claim 1, wherein, The first horizontal direction is perpendicular to the second horizontal direction.

10. A semiconductor device, comprising: The substrate has a gate region and a contact region; A fin-shaped insulating pattern extends on the substrate in a first horizontal direction; A lower Ti-based metal layer covers the upper and side surfaces of the fin-shaped insulating pattern in the contact area; An oxide semiconductor layer covers the upper and side surfaces of the lower Ti-based metal layer in the contact region, and also covers the upper and side surfaces of the fin-shaped insulating pattern in the gate region; A buffer insulating layer is provided on the oxide semiconductor layer; A gate pattern extends in a second horizontal direction on the oxide semiconductor layer in the gate region; as well as Source / drain contact patterns on the oxide semiconductor layer in the contact region.

11. The semiconductor device according to claim 10, wherein, The gate pattern penetrates the buffer insulating layer to make direct contact with the oxide semiconductor layer.

12. The semiconductor device according to claim 11, in, The buffer insulating layer comprises silicon oxide. The gate pattern includes: Interface insulating layer; The gate insulating layer on the interface insulating layer; and The gate electrode on the gate insulating layer, and The interface insulating layer includes aluminum oxide.

13. The semiconductor device according to claim 10, wherein, The source / drain contact pattern penetrates the buffer insulating layer to make direct contact with the oxide semiconductor layer.

14. The semiconductor device of claim 10, wherein: The source / drain contact pattern includes a source / drain contact barrier layer and a source / drain contact plug, and The source / drain contact barrier layer surrounds the bottom and side surfaces of the source / drain contact plug.

15. The semiconductor device of claim 10, further comprising: The upper Ti-based metal layer between the oxide semiconductor layer and the source / drain contact pattern.

16. The semiconductor device according to claim 15, wherein, The upper Ti-based metal layer surrounds the bottom and side surfaces of the source / drain contact pattern.

17. The semiconductor device according to claim 10, wherein, The first horizontal direction is perpendicular to the second horizontal direction.

18. A semiconductor device, comprising: The substrate has a gate region and a contact region; An insulating layer is embedded in the substrate; A fin-shaped insulating pattern extends in a first horizontal direction and forms in the gate region and the contact region on the buried insulating layer; A lower Ti-based metal layer is applied to the upper and side surfaces of the fin-shaped insulating pattern in the contact area. A channel layer is formed on the fin-type insulating pattern in the gate region and on the lower Ti-based metal layer in the contact region; A gate electrode extends in a second horizontal direction and is formed on the channel layer in the gate region; An upper Ti-based metal layer is placed on the channel layer in the contact region; as well as Source / drain contact pattern on the upper Ti-based metal layer in the contact region. The channel layer comprises an oxide semiconductor material.

19. The semiconductor device according to claim 18, wherein, The underlying Ti-based metal layer includes either TiC or TiAl.

20. The semiconductor device according to claim 18, wherein, The upper Ti-based metal layer includes at least one of Ti, TiN, TiC, TiAl, and TiAlN.

21. The semiconductor device according to claim 18, wherein, The upper Ti-based metal layer conformally covers the upper surface of the channel layer on the upper surface of the lower Ti-based metal layer on the upper surface of the fin-shaped insulating pattern, the side surface of the channel layer on the side surface of the lower Ti-based metal layer on the side surface of the fin-shaped insulating pattern, a portion of the upper surface of the buried insulating layer, and the bottom and side surfaces of the source / drain contact pattern.

22. The semiconductor device according to claim 18, wherein, The first horizontal direction is perpendicular to the second horizontal direction.

23. A method for manufacturing a semiconductor device, comprising: Provide a substrate having a gate region and a contact region; A fin-shaped insulating pattern extending in a first horizontal direction is formed on the substrate; A lower Ti-based metal layer is formed on the upper and side surfaces of the fin-shaped insulating pattern in the contact area; An oxide semiconductor layer is formed on the upper and side surfaces of the fin-shaped insulating pattern and the lower Ti-based metal layer; A sacrificial gate electrode extending in a second horizontal direction is formed on the oxide semiconductor layer in the gate region; A lower interlayer insulating layer is formed on the oxide semiconductor layer in the contact region; A gate trench is formed in the gate region by removing the sacrificial gate electrode; A gate electrode is formed in the gate trench; A contact slit is formed in the contact area to expose the oxide semiconductor layer; as well as Source / drain contact patterns are formed on the oxide semiconductor layer exposed in the contact slit.

24. The method of claim 23, further comprising: A buffer insulating layer is formed on the oxide semiconductor layer. in: The sacrificial gate electrode and the lower interlayer insulating layer are disposed on the buffer insulating layer, and The gate trench exposes the buffer insulating layer.

25. The method of claim 23, further comprising: An upper Ti-based metal layer is conformally formed on the upper surface of the oxide semiconductor layer exposed in the contact slit and on the side surface of the lower interlayer insulating layer.

26. The method according to claim 23, in, Forming the gate electrode includes: An interface insulating layer is formed on the oxide semiconductor layer exposed in the gate trench; A gate insulating layer is formed on the interface insulating layer; and The gate electrode is formed on the gate insulating layer.

27. The method according to claim 23, in, Forming the source / drain contact pattern includes: A source / drain contact barrier layer is conformally formed on the bottom and side surfaces of the contact slit, and Source / drain contact plugs are formed on the source / drain contact blocking layer to fill the contact slits.

28. The method according to claim 23, wherein, The first horizontal direction is perpendicular to the second horizontal direction.

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