Delay buffer unit and operation method thereof, computing device and operation method thereof

Abstract

A kind of delay buffer unit and its operating method, computing device and its operating method.The delay buffer unit includes first stage inverter, second stage inverter and delay adjustment subunit, the input end of first stage inverter is as the input end of delay buffer unit;The input end of second stage inverter is connected the output end of first stage inverter, and the output end of second stage inverter is as the output end of delay buffer unit;Delay adjustment subunit is connected between the first end of first stage inverter and first operating voltage end, and delay adjustment subunit includes memristor and is configured to control the transmission delay of first stage inverter using memristor according to first control signal.The delay buffer unit and its operating method can flexibly regulate and control the size of delay according to actual demand, and can be used for storage and calculation integrated to realize matrix vector multiplication operation, the computing device and its operating method can realize large-scale matrix operation of high precision, low energy consumption, improve computing efficiency.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a delay buffer unit and its operation method, and a computing device and its operation method. Background Technology

[0002] Memristors (e.g., resistive random access memory, phase-change memory, bridged memory, etc.) are non-volatile devices whose conductance can be adjusted by applying external stimuli. As a two-terminal device, memristors have adjustable and non-volatile resistance, making them widely used in in-memory computing. According to Kirchhoff's current law and Ohm's law, an array of memristors can perform multiplication and accumulation calculations in parallel, with both storage and computation occurring within the array's individual devices.

[0003] Because memristors have the characteristics of high speed, low power consumption and compatibility with CMOS technology, in-memory computing based on memristors is a new type of computing method. Compared with the traditional von Neumann architecture, its storage and computing integration design can avoid the huge latency and energy consumption caused by data migration. It has a natural advantage in neural networks, especially in matrix-vector multiplication, and can reduce the computational complexity of matrix-vector multiplication from O(n2) to O(1). Summary of the Invention

[0004] At least one embodiment of this disclosure provides a delay buffer unit, which includes: a first-stage inverter, a second-stage inverter, and a delay adjustment subunit. The input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit. The input terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter, and the output terminal of the second-stage inverter serves as the output terminal of the delay buffer unit. The delay adjustment subunit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment subunit includes a memristor and is configured to control the use of the memristor to adjust the transmission delay of the first-stage inverter according to a first control signal.

[0005] For example, in the delay buffer unit provided in at least one embodiment of this disclosure, the delay adjustment subunit further includes a control switch, the control switch including a first pole, a second pole and a control pole, the control pole receiving the first control signal to turn the first pole and the second pole on or off according to the first control signal, the first pole of the control switch being electrically connected to the first terminal of the first-stage inverter; the first terminal of the memristor being electrically connected to the first pole of the control switch and the first terminal of the first-stage inverter, and the second terminal of the memristor being electrically connected to the first operating voltage terminal.

[0006] For example, in the delay buffer unit provided in at least one embodiment of this disclosure, the second pole of the control switch is electrically connected to the first operating voltage terminal, or electrically connected to a second operating voltage terminal different from the first operating voltage terminal.

[0007] At least one embodiment of this disclosure also provides an operation method for a delay buffer unit, the operation method comprising: receiving an input signal of the delay buffer unit at the input terminal of a first-stage inverter, and outputting an output signal of the delay buffer unit at the output terminal of a second-stage inverter; receiving a first control signal by a delay adjustment subunit, and controlling the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal.

[0008] For example, in at least one embodiment of the operation method provided in this disclosure, the delay adjustment subunit further includes a control switch, the control switch including a first electrode, a second electrode, and a control electrode, and the first terminal of the memristor is electrically connected to the first electrode of the control switch.

[0009] The delay adjustment subunit receives the first control signal and controls the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal, including:

[0010] The control switch controls whether the memristor is connected between the first terminal of the first stage inverter and the first operating voltage terminal according to the first control signal;

[0011] The memristor is used to change the source degenerate resistance of the first-stage inverter according to the input signal, so as to adjust the propagation delay of the first-stage inverter.

[0012] For example, in an operating method provided in at least one embodiment of this disclosure, when the memristor is connected between the first terminal of the first-stage inverter and the first operating voltage terminal according to the first control signal, the propagation delay of the first-stage inverter is the propagation delay adjusted by the memristor; when the memristor is bypassed between the first terminal of the first-stage inverter and the first operating voltage terminal according to the first control signal, the propagation delay of the first-stage inverter is the intrinsic delay of the first-stage inverter.

[0013] For example, at least one embodiment of the present disclosure provides an operation method that further includes: disconnecting the conductive path between the delay adjustment subunit and the first stage inverter according to the input signal; connecting the delay adjustment subunit to a first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal.

[0014] For example, in at least one embodiment of the operation method provided in this disclosure, the delay adjustment subunit further includes a control switch, the control switch including a first electrode, a second electrode, and a control electrode, and the first terminal of the memristor is electrically connected to the first electrode of the control switch.

[0015] Connect the delay adjustment subunit to a first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal, including:

[0016] Connect the second terminal of the control switch to the first operating voltage terminal, and connect the second terminal of the memristor to the second operating voltage terminal;

[0017] The control switch is turned on according to the first control signal, so as to adjust the resistance value of the memristor by the first processing operation voltage between the first operating voltage terminal and the second operating voltage terminal.

[0018] For example, in the operation method provided in at least one embodiment of this disclosure, the first processing operation includes a set operation, a reset operation, a read operation, or an initialization operation.

[0019] At least one embodiment of this disclosure also provides a computing device, the computing device comprising: a delay computing array, including 2M rows and N columns of delay buffer units, 2N word lines corresponding to the N columns, N bit lines corresponding to the N columns, and 2M source lines corresponding to the 2M rows, wherein N delay buffer units in each row are connected in series to form a delay chain, and each pair of adjacent delay chains constitutes a delay processing combination, wherein the two delay chains in each delay processing combination receive the same input signal; two delay buffer units located in the same column in each delay processing combination are respectively connected to two word lines corresponding to the same column; each delay buffer unit includes a first-stage inverter. The system comprises a second-stage inverter and a delay adjustment subunit, wherein the input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit, the input terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter, and the output terminal of the second-stage inverter serves as the output terminal of the delay buffer unit, the delay adjustment subunit is connected to a first terminal of the first-stage inverter, and is connected to a source line corresponding to the row, a bit line corresponding to the column, and a word line corresponding to the column, the delay adjustment subunit includes a memristor, and is configured to control the use of the memristor to adjust the transmission delay of the first-stage inverter according to a first control signal provided by the corresponding word line.

[0020] For example, in a computing device provided in at least one embodiment of this disclosure, the delay adjustment subunit further includes a control switch. The control switch includes a first electrode, a second electrode, and a control electrode. The control electrode of the control switch is connected to the word line corresponding to the column where the delay adjustment subunit is located. The first electrode of the control switch is connected to the first terminal of the first-stage inverter and the first terminal of the memristor. The second electrode of the control switch is connected to the source line corresponding to the row where the delay adjustment subunit is located. The second terminal of the memristor is connected to the bit line corresponding to the column where the delay adjustment subunit is located.

[0021] For example, at least one embodiment of the computing device provided in this disclosure further includes: at least one delayed charge conversion module connected to the delayed processing assembly and configured to quantize the delay difference of the output signals of the two delayed chains in the delayed processing assembly into a voltage output signal; and at least one analog-to-digital conversion module connected to the delayed charge conversion module and configured to convert the voltage output signal output from the delayed charge conversion module into a digital signal.

[0022] For example, in a computing device provided in at least one embodiment of this disclosure, the computing device includes a plurality of delayed charge conversion modules, which are connected to one of the analog-to-digital conversion modules to time-division multiplex the analog-to-digital conversion module.

[0023] For example, at least one embodiment of the computing device provided in this disclosure further includes: an intrinsic delay calibration module, which is connected in combination with the delay processing and configured to calibrate the intrinsic delay of the two delay chains so that the intrinsic delay of the two delay chains matches.

[0024] At least one embodiment of this disclosure also provides a method for operating the above-described computing device, the method comprising: controlling at least one delay processing combination in the delay computing array via the 2N word lines according to a combination of control signals, wherein the combination of control signals includes 2N first control signals respectively applied to the 2N word lines; applying corresponding input signals to the input terminals of the at least one delay processing combination respectively; and receiving an output signal after delay processing of the corresponding input signals at the output terminal of the at least one delay processing combination.

[0025] For example, at least one embodiment of the present disclosure provides an operation method that further includes: for each delay buffer unit in the delay processing combination, selecting an operation mode according to the corresponding input signal, and performing an operation corresponding to the operation mode according to the control signal combination.

[0026] For example, in the operation method provided in at least one embodiment of this disclosure, the operation mode includes a first operation mode and a second operation mode. The operation method further includes: in the first operation mode, connecting the bit line of the column where the delay buffer unit is located to a first operation voltage terminal, connecting the source line of the row where the delay buffer unit is located to a second operation voltage terminal, and performing a first processing operation on the memristor in the delay buffer unit according to a first control signal corresponding to the delay buffer unit; in the second operation mode, connecting the bit line of the column where the delay buffer unit is located and the source line of the row where the delay buffer unit is located to the first operation voltage terminal, and performing a calculation operation or a calibration read operation on the at least one delay processing combination according to the control signal combination.

[0027] For example, in the operation method provided in at least one embodiment of this disclosure, a calculation operation is performed on at least one selected delay processing combination according to a combination of control signals, including: applying 2N first control signals as calculation input signals to 2N delay buffer units in the at least one delay processing combination through the 2N word lines; and obtaining differential delay calculation results from the output terminal of the at least one delay processing combination.

[0028] For example, in an operation method provided in at least one embodiment of this disclosure, a calibration read operation is performed on at least one selected delay processing combination according to a combination of control signals, including: determining a target column in the at least one delay processing combination for performing the calibration read operation; applying a first control signal for accessing the memristor and a first control signal for bypassing the memristor to two delay buffer units on the target column in the at least one delay processing combination, respectively; applying a first control signal for bypassing the memristor to multiple columns in the at least one delay processing combination other than the target column; and obtaining a differential delay read result from the output of the at least one delay processing combination.

[0029] For example, at least one embodiment of this disclosure provides an operation method that further includes: determining whether to perform the first processing operation on at least one memristor in two delay buffer units on the target column based on the differential delay read result; if the differential delay read result does not reach the expected weight value, then performing the first processing operation again on the at least one memristor.

[0030] For example, in the operation method provided in at least one embodiment of this disclosure, the first processing operation includes a set operation, a reset operation, a read operation, or an initialization operation. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figure 1A This is a schematic diagram of the structure of an exemplary delay buffer unit provided in at least one embodiment of the present disclosure;

[0033] Figure 1B This is a schematic diagram of the structure of another exemplary delay buffer unit provided in at least one embodiment of the present disclosure;

[0034] Figure 2 A schematic diagram of the structure of an exemplary memristor provided for at least one embodiment of this disclosure;

[0035] Figure 3 A block diagram of an exemplary delay chain provided for at least one embodiment of this disclosure;

[0036] Figure 4 This is a schematic diagram of the structure of an exemplary delay computing array provided in at least one embodiment of the present disclosure;

[0037] Figure 5A This is a schematic diagram illustrating a set or initialization operation on a delay computing array, provided for at least one embodiment of this disclosure.

[0038] Figure 5B This is a schematic diagram illustrating a reset operation for a delay computing array, provided for at least one embodiment of this disclosure.

[0039] Figure 6 This is a schematic diagram illustrating a calibration readout operation for a delay computing array, provided for at least one embodiment of the present disclosure;

[0040] Figure 7 This is a schematic diagram of the structure of a computing device provided in at least one embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of the structure of an exemplary current mirror control unit provided in at least one embodiment of the present disclosure;

[0042] Figure 9 A timing diagram illustrating a delayed charge conversion process provided for at least one embodiment of this disclosure;

[0043] Figure 10 A schematic diagram of an exemplary quantization circuit provided for at least one embodiment of this disclosure;

[0044] Figure 11 A timing diagram illustrating a forward computation process provided for at least one embodiment of this disclosure;

[0045] Figure 12 This diagram illustrates how the intrinsic delay deviation and mismatch between adjacent delay chains erodes the dynamic range of the ADC; and

[0046] Figure 13 This is a schematic diagram of an exemplary intrinsic delay calibration module provided for at least one embodiment of the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0049] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numerals in each drawing.

[0050] Memristors are a novel type of information processing device with in-memory computing capabilities, enabling computational operations to be performed on stored data in-situ, thus eliminating the significant overhead of data transfer. Furthermore, memristors can perform operations directly in the analog domain (e.g., multiplication based on Ohm's law and addition based on Kirchhoff's current law), thereby achieving matrix-vector multiplication in one step without the overhead of analog-to-digital conversion. Significant progress has been made in memristor-based in-memory computing in recent years. However, due to the limited power supply of terminal devices, memristor-based in-memory computing devices must not only have higher computational accuracy but also lower power consumption and higher energy efficiency. To address these requirements, memristor-based in-memory computing designs have undergone numerous improvements in array structure and peripheral circuit design.

[0051] For example, one improved approach is voltage-domain quantization, which uses voltage pre-charge readout to replace the current-based readout with its excessive static current overhead. However, this approach has a limited output range. Another improved approach is time-domain quantization, which converts the output to the time domain to increase the output range, thus simplifying and efficiently distinguishing different output states. However, time-domain quantization suffers from nonlinearity. Furthermore, both voltage-domain and time-domain quantization methods need to handle the large current flowing through the memristor array when it is turned on in parallel, resulting in significant power consumption in the memristor array and its peripheral circuits. Yet another improved approach is a current-based analog computing scheme based on a 2T2R array structure. This scheme mitigates the IR drop problem by reducing the accumulated output current, offering high parallelism and computing power. However, to ensure computational accuracy, this method requires significant input power and clamping circuit power, which also leads to substantial power consumption when the array size is large. Therefore, achieving low-power and high-efficiency in-memory computing has become a pressing issue.

[0052] At least one embodiment of this disclosure provides a delay buffer unit and its operation method. The delay buffer unit includes: a first-stage inverter, a second-stage inverter, and a delay adjustment subunit. The input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit. The input terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter, and the output terminal of the second-stage inverter serves as the output terminal of the delay buffer unit. The delay adjustment subunit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal. The delay adjustment subunit includes a memristor and is configured to control the use of the memristor to adjust the transmission delay of the first-stage inverter according to a first control signal.

[0053] The operation method of the delay buffer unit includes: receiving the input signal of the delay buffer unit at the input terminal of the first-stage inverter, and outputting the output signal of the delay buffer unit at the output terminal of the second-stage inverter; receiving the first control signal by the delay adjustment subunit, and controlling the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal.

[0054] The delay buffer unit and its operation method provided in at least one embodiment of this disclosure can change the transmission delay of the delay buffer unit according to whether a memristor is used, and can also change the transmission delay of the delay buffer unit by controlling the change of the resistance value of the memristor, thereby realizing dynamic control of the delay buffer unit and flexibly and efficiently adjusting the delay size according to actual needs. Furthermore, in at least one embodiment of this disclosure, the delay buffer unit can also be used to implement in-memory matrix-vector multiplication. In the case of multiple delay buffer units cascaded, the computational weights are mapped to the delay of the delay buffer units, and the cumulative delay is obtained from the output terminals of the multiple delay buffer units as the output result of the matrix-vector multiplication.

[0055] At least one embodiment of this disclosure also provides a computing device and its operation method. The computing device includes a delay computing array, which includes 2M rows and N columns of delay buffer units, 2N word lines corresponding to N columns, N bit lines corresponding to N columns, and 2M source lines corresponding to 2M rows. N delay buffer units in each row are connected in series to form a delay chain. Each pair of adjacent delay chains constitutes a delay processing combination. The two delay chains in each delay processing combination receive the same input signal. Two delay buffer units in the same column of each delay processing combination are respectively connected to two word lines corresponding to the same column. Each delay... The buffer unit includes a first-stage inverter, a second-stage inverter, and a delay adjustment subunit. The input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit. The input terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter, and the output terminal of the second-stage inverter serves as the output terminal of the delay buffer unit. The delay adjustment subunit is connected to the first terminal of the first-stage inverter and is also connected to the source line corresponding to the row, the bit line corresponding to the column, and the word line corresponding to the column. The delay adjustment subunit includes a memristor and is configured to control the adjustment of the transmission delay of the first-stage inverter using the memristor according to a first control signal provided by the corresponding word line.

[0056] The operation method of the computing device includes: controlling at least one delay processing combination in the delay computing array through 2N word lines according to a combination of control signals, wherein the combination of control signals includes 2N first control signals respectively applied to the 2N word lines; applying corresponding input signals to the input terminals of the at least one delay processing combination respectively; and receiving output signals after delay processing of the corresponding input signals at the output terminal of the at least one delay processing combination.

[0057] The computing device and its operation method provided in at least one embodiment of this disclosure can realize in-memory computing by utilizing a delay buffer unit. By converting the calculation result of matrix-vector multiplication into the delay of the delay buffer unit, high-precision, low-power large-scale matrix operations can be achieved, thereby improving the computational efficiency of matrix-vector multiplication operations.

[0058] The following will describe several embodiments of the delay buffer unit and its operation method, and the computing device and its operation method disclosed herein.

[0059] Figure 1A A schematic diagram of the structure of an exemplary delay buffer unit provided according to at least one embodiment of the present disclosure is shown; Figure 1B A schematic diagram of another exemplary delay buffer unit provided according to at least one embodiment of the present disclosure is shown. The following is in conjunction with... Figure 1A and Figure 1B The circuit structure of the delay buffer unit is described in detail.

[0060] like Figure 1A and Figure 1B As shown, the delay buffer unit 10 includes a first-stage inverter P1, a second-stage inverter P2, and a delay adjustment subunit 11.

[0061] For example, the input terminal of the first-stage inverter P1 serves as the input terminal INT of the delay buffer unit 10. The input signal of the delay buffer unit can be received from the input terminal of the first-stage inverter P1; this input signal can be, for example, a rising edge trigger signal (such as...). Figure 1A (as shown) or falling edge trigger signal (such as Figure 1B (As shown). For example, the first-stage inverter P1 includes two transistors T1 and T2. T1 is, for example, an NMOS transistor, and T2 is, for example, a PMOS transistor. The gate terminals of transistors T1 and T2 can serve as input terminals, that is, as the input terminal INT of the delay buffer unit 10 to receive input signals. For example, when the input signal is high, transistor T1 is turned on and transistor T2 is turned off; when the input signal is low, transistor T1 is turned off and transistor T2 is turned on. The drain terminals of transistors T1 and T2 are electrically connected to each other and serve as the output terminal of the first-stage inverter P1. The source terminal of transistor T1 or T2 can be connected to the ground terminal or the power supply terminal, or it can serve as the first terminal of the first-stage inverter P1.

[0062] For example, the input terminal of the second-stage inverter P2 is connected to the output terminal of the first-stage inverter P1, and the output terminal of the second-stage inverter P2 serves as the output terminal OUT of the delay buffer unit 10. The circuit structure of the second-stage inverter P2 is similar to that of the first-stage inverter P1, and will not be described again here. It should be noted that the circuit structures of the first-stage inverter P1 and the second-stage inverter P2 can also be implemented in other ways, and the embodiments disclosed herein are not limited thereto.

[0063] For example, the output signal of the delay buffer unit 10 can be output from the output terminal of the second-stage inverter P2. This output signal corresponds to the input signal and has a certain delay relative to the input signal. This delay consists of the propagation delay of the first-stage inverter P1 and the second-stage inverter P2. For example, as... Figure 1A As shown, when the input signal received from the input terminal INT of the delay buffer unit 10 is a rising edge trigger signal, the output signal output from the output terminal OUT of the delay buffer unit 10 is relative to the rising edge trigger signal (in the... Figure 1A The output terminal OUT in the diagram is represented by gray lines for the rising edge trigger signal and black lines for the output signal, respectively, and has a certain delay t. For example, as shown... Figure 1B As shown, when the input signal received from the input terminal INT of the delay buffer unit 10 is a falling edge trigger signal, the output signal output from the output terminal OUT of the delay buffer unit 10 is relative to the falling edge trigger signal (in the... Figure 1B The output terminal OUT is represented by gray lines and black lines respectively to indicate the falling edge trigger signal and the output signal, which have a certain delay t.

[0064] For example, the delay adjustment subunit 11 is connected between the first terminal of the first-stage inverter P1 and the first operating voltage terminal 1, and the delay adjustment subunit 11 includes a memristor (here, resistive random access memory (RRAM) is used as an example). The delay adjustment subunit 11 is configured to control the use of the memristor RRAM to adjust the propagation delay of the first-stage inverter P1 according to a first control signal. For example, the first control signal is provided by the first control terminal NWL and is used to control whether the delay adjustment subunit 11 uses the memristor RRAM to adjust the propagation delay of the first-stage inverter P1, thereby adjusting the delay difference (delay t) between the output signal and the input signal of the delay buffer unit 10.

[0065] For example, the delay adjustment subunit 11 also includes a control switch, which can be an N-type transistor or a P-type transistor, and the embodiments of this disclosure are not limited thereto. The control switch (here, an N-type transistor (NM1) is used as an example) includes a first terminal, a second terminal, and a control terminal. The first terminal, second terminal, and control terminal of the control switch NM1 can be, for example, the source, drain, and gate of an N-type transistor, respectively. The control terminal of the control switch NM1 is connected to a first control terminal NWL. The control switch NM1 receives a first control signal from the first control terminal NWL and turns on or off the first and second terminals of the control switch NM1 according to the first control signal. For example, the first terminal of the control switch NM1 is electrically connected to the first terminal of the first-stage inverter P1, and the second terminal of the control switch NM1 is electrically connected to the first operating voltage terminal 1. When the control switch NM1 is open, the first-stage inverter P1 is connected to the first operating voltage terminal 1; when the control switch NM1 is closed, the first-stage inverter P1 is disconnected from the first operating voltage terminal 1. The control switch NM1 can be an N-type transistor (e.g., Figure 1A (As shown), it can also be a P-type transistor, and the embodiments of this disclosure are not limited to this.

[0066] For example, the memristor RRAM in the delay adjustment subunit 11 includes a first terminal and a second terminal. The first terminal of the memristor RRAM is electrically connected to the first terminal of the control switch NM1 and the first terminal of the first-stage inverter P1. In at least one embodiment of this disclosure, the second terminal of the memristor RRAM and the second terminal of the control switch NM1 can be connected to the same operating voltage terminal or different operating voltage terminals. Here, connecting the second terminal of the memristor RRAM and the second terminal of the control switch NM1 to the same operating voltage terminal means that the voltage signals obtained by both from the same (or different) operating voltage terminals are the same; connecting the second terminal of the memristor RRAM and the second terminal of the control switch NM1 to different operating voltage terminals means that the voltage signals obtained by both from different operating voltage terminals are different.

[0067] For example, in one example, the second terminal of the memristor RRAM is electrically connected to the first operating voltage terminal 1 (e.g., Figure 1B As shown), that is, the second terminal of the memristor RRAM and the second terminal of the control switch NM1 are connected together to the first operating voltage terminal, which can be, for example, a power supply terminal (such as...). Figure 1B (as shown) or ground terminal. For example, in another example, such as Figure 1AAs shown, the second terminal of the memristor RRAM is electrically connected to the second operating voltage terminal 2, and the second terminal of the control switch NM1 is electrically connected to the first operating voltage terminal 1. The voltage signals provided by the first operating voltage terminal 1 and the second operating voltage terminal 2 are different. For example, in another example, the second terminal of the memristor RRAM is electrically connected to the first operating voltage terminal 1, and the second terminal of the control switch NM1 is electrically connected to the second operating voltage terminal 2. The first operating voltage terminal 1 and the second operating voltage terminal 2 are different.

[0068] In at least one embodiment of this disclosure, the delay adjustment subunit 11 is connected to a first terminal of the first-stage inverter P1, for example, to the source terminal of the first-stage inverter P1. For example, as... Figure 1A As shown, the delay adjustment subunit 11 is connected between the NMOS transistor T1 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in Figure 1A In the delay adjustment subunit 11 shown, the first terminal (e.g., drain) of the control switch NM1 is connected to the source terminal of the NMOS transistor T1 in the first-stage inverter P1, and the first terminal of the memristor RRAM is connected to the source terminal of the NMOS transistor T1 in the first-stage inverter P1. For example, as Figure 1B As shown, the delay adjustment subunit 11 is connected between the PMOS transistor T2 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in... Figure 1B In the delay adjustment subunit 11 shown, the first terminal (e.g., the source terminal) of the control switch NM1 is connected to the source terminal of the PMOS transistor T2 in the first-stage inverter P1, and the first terminal of the memristor RRAM is connected to the source terminal of the PMOS transistor T2 in the first-stage inverter P1.

[0069] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors (e.g., MOS field-effect transistors), or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. The embodiments of this disclosure do not limit the type of transistor used.

[0070] For example, the delay buffer unit 10 also includes a capacitor C1. The first terminal of capacitor C1 is connected between the output terminal of the first-stage inverter P1 and the input terminal of the second-stage inverter P2, and the second terminal of capacitor C1 is grounded. Capacitor C1 can be, for example, a specially manufactured capacitor element or a parasitic capacitor, etc., and the embodiments of this disclosure are not limited in this respect.

[0071] The operation method of the delay buffer unit 10 according to at least one embodiment of the present disclosure will be described below. The operation method includes the following steps S100 and S200:

[0072] Step S100: Receive the input signal of the delay buffer unit at the input terminal of the first-stage inverter, and output the output signal of the delay buffer unit at the output terminal of the second-stage inverter;

[0073] Step S200: The delay adjustment subunit receives the first control signal and controls the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal.

[0074] For example, in step S100, the input signal of the delay buffer unit 10 is received at the input terminal INT of the first-stage inverter P1. This input signal may be, for example, a rising edge trigger signal (such as...). Figure 1A (as shown) or falling edge trigger signal (such as Figure 1B (As shown). The output signal of the delay buffer unit 10 is output at the output terminal OUT of the second-stage inverter P2. This output signal corresponds to the input signal and has a certain delay relative to the input signal. This delay consists of the two-stage flip delay of the first-stage inverter P1 and the second-stage inverter P2. For example, the propagation delay of the first-stage inverter P1 can be the intrinsic delay of the first-stage inverter P1 or the propagation delay adjusted by the memristor, and the propagation delay of the second-stage inverter P2 is the intrinsic delay of the second-stage inverter P2.

[0075] For example, in at least one example of the embodiments of this disclosure, step S200, namely, receiving a first control signal by the delay adjustment subunit and controlling the use of a memristor to adjust the propagation delay of the first-stage inverter according to the first control signal, may include: controlling whether to connect a memristor between the first terminal and the first operating voltage terminal of the first-stage inverter by a control switch according to the first control signal; and using the memristor to change the source degenerate resistance of the first-stage inverter according to the input signal to adjust the propagation delay of the first-stage inverter.

[0076] According to one embodiment of this disclosure, when the control switch bypasses the memristor between the first terminal and the first operating voltage terminal of the first-stage inverter according to the first control signal, the propagation delay of the first-stage inverter is the intrinsic delay of the first-stage inverter. When the memristor is connected between the first terminal and the first operating voltage terminal of the first-stage inverter according to the first control signal, the propagation delay of the first-stage inverter is the propagation delay adjusted by the memristor.

[0077] For example, in Figure 1A In the delay buffer unit 10 shown, the second terminal of the control switch NM1 in the delay adjustment subunit 11 and the second terminal of the memristor RRAM are connected to the same operating voltage terminal, such as the ground terminal. Alternatively, the second terminal of the control switch NM1 in the delay adjustment subunit 11 and the second terminal of the memristor RRAM are connected to the first operating voltage terminal 1 and the second operating voltage terminal 2, respectively, and both the first operating voltage terminal 1 and the second operating voltage terminal 2 are grounded.

[0078] For example, when the input signal received from the input terminal INT of the delay buffer unit 10 is a high-level signal, the PMOS transistor T2 in the first-stage inverter P1 is turned off, and the NMOS transistor T1 is turned on. That is, the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1 is opened according to the input signal. In this case, the delay adjustment subunit 11 can control whether a memristor is connected between the first terminal (source terminal of T1) of the first-stage inverter P1 and the first operating voltage terminal 1 according to the first control signal by controlling the switch NM1. This adjusts the delay difference t between the rising edge of the output signal and the rising edge of the input signal.

[0079] For example, when the first control signal received by the delay adjustment subunit 11 is high, the control switch NM1 is turned on, thereby connecting the first-stage inverter P1 to the ground terminal through the control switch NM1, thus bypassing the memristor RRAM. At this time, the delay t between the output signal and the input signal of the delay buffer unit 10 is the sum of the intrinsic delay of the first-stage inverter P1 and the intrinsic delay of the second-stage inverter P2.

[0080] For example, when the first control signal received by the delay adjustment subunit 11 is low, the control switch NM1 is closed, thereby making the first-stage inverter P1 conduct through the memristor RRAM to the ground terminal. That is, the memristor RRAM is connected between the first terminal (e.g., the source terminal of T1) of the first-stage inverter P1 and the first operating voltage terminal (ground terminal). At this time, the delay t between the output signal and the input signal of the delay buffer unit 10 is the sum of the propagation delay of the first-stage inverter P1 after adjustment by the memristor and the intrinsic delay of the second-stage inverter P2.

[0081] For example, when a memristor is connected, the resistance value of the memristor determines the source degenerate resistance of the first-stage inverter P1, which in turn affects the discharge rate of the charge. Therefore, the delay of the delay buffer unit 10 can be adjusted by changing the resistance value of the memristor. That is, when the resistance value of the memristor is small, the charge discharge rate is fast, and the output delay t of the delay buffer unit 10 is small; when the resistance value of the memristor is large, the charge discharge rate is slow, and the output delay t of the delay buffer unit 10 is large.

[0082] For example, in Figure 1B In the delay buffer unit 10 shown, the second terminal (e.g., the drain) of the control switch NM1 in the delay adjustment subunit 11 and the second terminal of the memristor RRAM are connected to the same operating voltage terminal, such as the power supply terminal.

[0083] For example, when the input signal received from the input terminal INT of the delay buffer unit 10 is a low-level signal, the NMOS transistor T1 in the first-stage inverter P1 is turned off, and the PMOS transistor T2 is turned on. That is, the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1 is opened according to the input signal. In this case, the delay adjustment subunit 11 can control whether a memristor is connected between the first terminal (source terminal of T2) of the first-stage inverter P1 and the first operating voltage terminal 1 by controlling the switch NM1 according to the first control signal, thereby adjusting the delay difference t between the falling edge of the output signal and the falling edge of the input signal.

[0084] For example, when the first control signal received by the delay adjustment subunit 11 is high, the control switch NM1 is turned on, thereby connecting the first-stage inverter P1 to the power supply through the control switch NM1, thus bypassing the memristor RRAM. At this time, the delay t between the output signal and the input signal of the delay buffer unit 10 is the sum of the intrinsic delay of the first-stage inverter P1 and the intrinsic delay of the second-stage inverter P2.

[0085] For example, when the first control signal received by the delay adjustment subunit 11 is low, the control switch NM1 is closed, thereby enabling the first-stage inverter P1 to conduct through the memristor RRAM to the power supply terminal. That is, the memristor RRAM is connected between the first terminal (e.g., the source terminal of T2) of the first-stage inverter P1 and the first operating voltage terminal 1 (power supply terminal). At this time, the delay t between the output signal and the input signal of the delay buffer unit 10 is the sum of the propagation delay of the first-stage inverter P1 after adjustment by the memristor and the intrinsic delay of the second-stage inverter P2.

[0086] For example, when a memristor is connected, the resistance value of the memristor determines the source degeneration resistance of the first-stage inverter P1. When the source degeneration resistance connected in series with the capacitor changes, the charging speed of the charge also changes. Therefore, the delay of the delay buffer unit 10 can be adjusted by changing the resistance value of the memristor. That is, when the resistance value of the memristor is small, the charge charging speed is fast, and the output delay t of the delay buffer unit 10 is small; when the resistance value of the memristor is large, the charge charging speed is slow, and the output delay t of the delay buffer unit 10 is large.

[0087] The above operation method may further include steps S300 and S400:

[0088] Step S300: Disconnect the conductive path between the delay adjustment subunit and the first-stage inverter according to the input signal;

[0089] Step S400: Connect the delay adjustment subunit to the first operating voltage terminal and the second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal.

[0090] For example, in Figure 1A In the delay buffer unit 10 shown, when the input signal received from the input terminal INT of the delay buffer unit 10 is a low-level signal, the NMOS transistor T1 in the first-stage inverter P1 is turned off and the PMOS transistor T2 is turned on, thereby disconnecting the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1. In this case, the delay adjustment subunit 11 can be connected to the first operating voltage terminal 1 and the second operating voltage terminal 2 to perform a first processing operation on the memristor RRAM according to the first control signal. For example, the first processing operation performed on the memristor RRAM can be a set operation, a reset operation, or an initialization operation to change the resistance value of the memristor.

[0091] For example, in at least one example of the embodiments of this disclosure, step S400, which connects the delay adjustment subunit to the first operating voltage terminal and the second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal, may include: connecting the second terminal of the control switch to the first operating voltage terminal and connecting the second terminal of the memristor to the second operating voltage terminal; turning on the control switch according to the first control signal to adjust the resistance value of the memristor through the first processing operation voltage between the first operating voltage terminal and the second operating voltage terminal.

[0092] For example, such as Figure 1A As shown, when the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1 is disconnected, the control switch NM1 in the delay adjustment subunit 11 is connected to the first operating voltage terminal, the memristor is connected to the second operating voltage terminal, and the operating voltage of the first processing operation is applied between the first operating voltage terminal and the second operating voltage terminal, thereby performing the first processing operation on the memristor.

[0093] The following is combined Figure 2 The composition and structure of the memristor and the process of performing the first processing operation on the memristor are explained.

[0094] Figure 2 A structural diagram of an exemplary memristor is shown. (As shown) Figure 2As shown, the memristor RRAM includes a resistive switching layer 111 and an upper electrode 113 (e.g., the first end in this disclosure) and a lower electrode 114 (e.g., the second end in this disclosure) located on both sides of the resistive switching layer 111. In at least one example, it may also include a functional layer 112. The functional layer 112 is an optional layer, and its addition or omission can be determined according to the optimization direction of the memristor performance, and it can be designed accordingly. The resistive switching layer 111 can be a single layer, including a single type of binary metal oxide (e.g., NiO, AlOx, etc.), graphene oxide, multi-component perovskite oxide (e.g., STO, SZO, PCMO, etc.), or it can be a multilayer, such as any optional stack of the above materials, for example, a stack of TixN and AlOx.

[0095] For memristors (e.g., resistive switching memory), an additional initialization process is typically required. After initialization, the resistance of the memristor can vary with an applied voltage signal. Since there are no conductive filaments inside the memristor when it is fabricated, an initialization operation is needed to form conductive filaments inside the memristor. This initialization operation typically only needs to be performed once during the memristor's lifetime.

[0096] For example, in Figure 1A In the delay buffer unit 10 shown, after the conductive path between the delay adjustment subunit 11 and the first-stage inverter P1 is broken, an initialization voltage can be applied between the first operating voltage terminal 1 and the second operating voltage terminal 2 to initialize the memristor, causing conductive filaments to form inside the memristor. For example, after initialization to form conductive filaments inside the memristor RRAM, the memristor RRAM has a threshold voltage.

[0097] For example, the mainstream approach is that when the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the memristor RRAM is less than the threshold voltage of the memristor RRAM, the resistance (or conductance) value of the memristor RRAM will not change. In this case, a read voltage can be applied between the first operating voltage terminal and the second operating voltage terminal to read the current resistance value of the memristor RRAM. This read voltage is less than the threshold voltage of the memristor RRAM, thus allowing the current resistance value of the memristor to be read without changing its resistance value.

[0098] For example, when the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the memristor RRAM is greater than the threshold voltage of the memristor RRAM, the resistance (or conductance) value of the memristor RRAM can be changed according to the set voltage or reset voltage applied between the upper electrode 113 and the lower electrode 114 of the memristor RRAM. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. For example, applying a set voltage to the memristor RRAM can make the resistance value of the memristor RRAM decrease, and applying a reset voltage to the memristor RRAM can make the resistance value of the memristor RRAM increase. In the embodiments of this disclosure, applying a set voltage to the memristor is called a set operation, and applying a reset voltage to the memristor is called a reset operation.

[0099] For example, for Figure 1A The delay buffer unit shown can reduce the resistance value of the memristor RRAM by applying a set voltage between the first operating voltage terminal and the second operating voltage terminal when the delay adjustment subunit 11 is disconnected from the first-stage inverter P1. Thus, when the delay adjustment subunit 11 is electrically connected to the first-stage inverter P1, the output delay t of the delay buffer unit 10 is reduced by incorporating an RRAM with a small resistance value.

[0100] For example, when the delay adjustment subunit 11 is disconnected from the first-stage inverter P1, a reset voltage can be applied between the first operating voltage terminal and the second operating voltage terminal to increase the resistance value of the memristor RRAM. Thus, when the delay adjustment subunit 11 is electrically connected to the first-stage inverter P1, the output delay t of the delay buffer unit 10 can be increased by incorporating an RRAM with a larger resistance value.

[0101] As described above, the delay buffer unit and its operation method provided in at least one embodiment of this disclosure can change the transmission delay of the delay buffer unit according to whether or not a memristor is used, and can also change the transmission delay of the delay buffer unit by controlling the change of the resistance value of the memristor, thereby realizing dynamic control of the delay buffer unit, thereby enabling flexible and efficient control of the delay size according to actual needs.

[0102] When performing matrix-vector multiplication, such as multiplying vector V with matrix G to obtain the corresponding vector I, current memristor-based in-memory computing solutions map the conductance matrix to a memristor array. That is, the values ​​of multiple elements (or computational weights in a neural network) G11 to Gmn of matrix G are mapped to the conductance (or resistance) values ​​of multiple memristors in the memristor array. Then, the values ​​of multiple elements V1, V2, ..., Vm of the input vector V are mapped to multiple input voltage values ​​of the memristor array, and these input voltages are applied to multiple bit lines BL of the memristor array. According to Ohm's law and Kirchhoff's current law, the output current value on each source line SL is the value of the corresponding element I1, I2, ..., In in the output vector I. As mentioned earlier, this method of mapping matrix elements to memristor resistance values ​​results in significant power consumption during parallel processing due to limitations in computing principles.

[0103] In response, at least one embodiment of this disclosure provides a computing device that utilizes multiple delay buffer units to construct a computing array. When performing matrix multiplication and addition operations (e.g., neural network forward computation) using this computing array, the matrix elements (computation weights) are mapped to the delays of multiple delay buffer units respectively. The accumulated delay is obtained from the output of multiple delay buffer units as the output result of matrix-vector multiplication. This enables the multiplication and addition operation result to be converted into a uniform linear accumulation time of multiple delay buffer units (computation units) in the time domain. Furthermore, there is no static current during the computation process, only dynamic switching power consumption. At the same time, there is no need to use active operational amplifiers or other circuits in the peripheral circuits (e.g., quantization circuits) of the computing array, thereby enabling high-precision, low-power, and high-efficiency large-scale matrix operations.

[0104] like Figure 3 As shown, multiple delay buffer units 10 are cascaded to form a delay chain 20. An input signal KEEP is received from the input terminal INT of the first delay buffer unit 10 in the delay chain 20. This input signal KEEP can be, for example, a rising edge trigger signal or a falling edge trigger signal. For ease of description, the following will use the following... Figure 1A The matrix-vector multiplication operation is illustrated using the delay buffer unit 10 shown as an example. During the calculation, the input signal KEEP is a rising edge trigger signal, and the control switch NM1 and the memristor RRAM in the delay adjustment subunit 11 of the delay buffer unit 10 are both grounded.

[0105] For example, each delay buffer unit 10 performs a multiplication operation as a computing unit, and the cumulative delay of multiple delay buffer units 10 is output from the output end of the delay chain 20 as the result of the multiplication-addition operation.

[0106] For example, before performing calculations, the elements of matrix G (or the computational weights in the neural network) need to be mapped to the delay of delay buffer unit 10. This delay can be obtained, for example, by adjusting the resistance value of the memristor in delay buffer unit 10. For example, a column of elements G11, G21, ..., Gm1 of matrix G can be mapped to the delay W of m delay buffer units 10, which are controlled by memristors. <0> W <1> ..., W <m-1>.

[0107] Then, during the calculation, the elements of the input vector V are mapped to the first control signal of the delay buffer unit 10. For example, the input element V1 of the input vector V is used as the first control signal IN of the cascaded delay buffer units 10. <0> IN <1> IN <m-1>Multiple first control signals IN <0> IN <1> IN <m-1>For example, input can be parallelized to improve computational efficiency. The first control signal IN corresponds to input element V1. <0> IN <1> IN <m-1>Multiple delay Ws controlled by memristors in multiple delay buffer units 10 <0> W <1> ..., W <m-1>Whether it is serially inserted into delay chain 20. The cumulative delay IN at the output of delay chain 20. <m-1:0> ·W <m-1:0>This is the result of the vector inner product operation (multiplication and accumulation operation).

[0108] For example, for each delay buffer unit 10, when the first control signal is low (corresponding to input element V1 being 1), the memristor RRAM is connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the delay t of the delay buffer unit is the delay after the resistance value of the memristor is adjusted, that is, the delay controlled by the memristor is serially inserted into the delay chain. When the first control signal is high (corresponding to input element V1 being 0), the memristor RRAM is bypassed, and the memristor RRAM is not connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the delay t of the delay buffer unit is the intrinsic delay, that is, only the intrinsic delay is serially inserted into the delay chain.

[0109] Through the above calculation operations, a vector inner product operation (multiplication and accumulation operation) of one (e.g., 1 bit) input data and m weight elements can be realized. However, the embodiments of this disclosure are not limited to this. For example, a vector inner product operation of multiple (e.g., 8 bits) input data and m weight elements can also be realized. For example, the vector inner product operation of multiple input data can be realized by multiple time-division multiplexing or by arranging multiple identical delay chains.

[0110] At least one embodiment of this disclosure provides a computing device that can be used for matrix multiplication operations, such as for forward computation of a neural network.

[0111] like Figure 4 As shown, the computing device includes a delay computing array 100, which includes delay buffer units 10 with 2M rows and N columns (only 4 rows and 2 columns are shown in the figure).

[0112] For example, N delay buffer units 10 in each row are connected in series to form a delay chain 20, and each pair of adjacent delay chains 20 constitutes a delay processing combination 30. The difference in delay between two delay buffer units 10 in the same column of each delay processing combination 30 can correspond to a signed weight element. For example, by configuring the resistance values ​​of the memristors in the two delay buffer units 10, the difference in delay between the two delay buffer units 10 can represent a positive, negative, or zero weight element. That is, two delay buffer units 10 in the same column of each delay processing combination 30 can be used as a difference unit, and the delay of each difference unit can be used to represent a positive, negative, or zero weight element.

[0113] For example, the two delay chains 20 in each delay processing combination 30 receive the same input signal KEEP, for example, by receiving the input signal KEEP through the input terminal INT of the first delay buffer unit 10 in each of the two delay chains 20. The input signal KEEP can be used to control the operating mode of the delay calculation array 100. For example, the input signal KEEP can control whether the delay calculation array 100 is in a first operating mode or a second operating mode. When the input signal KEEP is kept at a constant low level (or a constant high level), the delay calculation array 100 is in the first operating mode; when the input signal KEEP is a rising edge trigger signal (or a falling edge trigger signal), the delay calculation array 100 is in the second operating mode.

[0114] In the first operating mode, the input signal KEEP is, for example, low, thereby controlling the delay adjustment subunit 11 in the delay buffer unit 10 to disconnect from the first-stage inverter P1. At this time, the first processing operation described above can be performed on the memristor RRAM, such as setting or resetting the memristor RRAM. In the second operating mode, the input signal KEEP is an edge signal, thereby controlling the delay adjustment subunit 11 in the delay buffer unit 10 to connect to the first-stage inverter P2. At this time, calculation operations or calibration read operations can be performed on the delay calculation array 100, for example, obtaining the delay calculation result or delay read result from the output of the delay chain.

[0115] For example, the outputs of the two delay chains 20 in each delay processing combination 30 output the cumulative delay of the multiple delay buffer units 10 in two rows, respectively. For example, as Figure 4 As shown, the first delay chain 20 in the first delay processing combination 30 starts from the output DLP. <0> Output the cumulative delay t_DLP of the N delay buffer units 10 in the first line. <0> The second line of delay chain 20 starts from the output DLN. <0> Output the cumulative delay t_DLN of the N delay buffer units 10 on the second line. <0> .

[0116] For example, in one instance, when a computation operation is performed on the delay computation array 100, the cumulative delay difference ΔT between the two delay chains in the delay processing combination 30 is t_DLP. <0> -t_DLN <0> It can represent the result of the vector dot product of the input data and the signed weight elements.

[0117] For example, in another example, when a calibration read operation is performed on the delay calculation array 100, the delay of a differential unit in the delay processing combination 30 (the delay difference between the two delay buffer units 10) can be read based on the cumulative delay difference ΔT between the two delay chains in the delay processing combination 30. By reading the delay of this differential unit, the differential unit can be calibrated; that is, by reading the delay of the differential unit, it can be determined whether the differential unit has been programmed to the expected weight. If the delay of the differential unit does not reach the expected value, the resistance value of the memristor can be adjusted again until the delay of the differential unit reaches the expected delay, thereby ensuring the accuracy of the calculation.

[0118] For example, in another example, if the intrinsic delays of the two delay chains do not match due to process limitations, another calibration read operation can be performed on the delay calculation array 100. That is, the intrinsic delay difference of the two delay chains can be read based on the cumulative delay difference ΔT of the two delay chains in the delay processing combination 30. After reading the intrinsic delay difference of the two delay chains, the intrinsic delays of the two delay chains can be calibrated to match, thereby reducing the calculation error caused by process limitations. For example, the delay calculation array 100 also includes 2N word lines and N bit lines corresponding to N column delay buffer units 10, and 2M source lines corresponding to 2M row delay buffer units. It should be noted that in the embodiments of this disclosure, the direction of the rows and columns is not limited to the situation shown in the figure, but can be determined as needed, and the embodiments of this disclosure do not limit this.

[0119] For example, in each delay processing combination 30, two delay buffer units 10 located in the same column are respectively connected to two word lines corresponding to the same column. For example, as Figure 4 As shown, in the first row of the delay processing combination 30, two adjacent delay buffer units 10 on the first column are respectively connected to the word line WLP. <0> and WLN <0> connect.

[0120] For example, in each delay processing combination 30, two delay buffer units 10 on the same column are connected to the corresponding bit lines in the same column. For example, as Figure 4 As shown, in the first row of the delay processing combination 30, the two adjacent delay buffer units 10 on the first column are both connected to the bit line BL. <0> connect.

[0121] For example, in each delay processing assembly 30, N delay buffer units 10 located in the same row are connected to the source line of that same row. For example, in the first row of the delay processing assembly 30, the N delay buffer units 10 located in the first row are all connected to the source line SLP. <0> The connections, located in the second row, are all N delay buffer units 10 connected to the source line SLN. <0> connect.

[0122] For example, in the delay buffer unit 10 of the delay calculation array 100, the delay adjustment subunit 11 of the delay buffer unit 10 is connected to the first terminal (e.g., the source terminal) of the first stage inverter. The delay adjustment subunit 11 is connected through the source line corresponding to the row, the bit line corresponding to the column, and the word line corresponding to the column, so as to be connected to different operating voltage terminals, such as the first operating voltage terminal or the second operating voltage terminal, through the source line, bit line, and word line.

[0123] For example, such as Figure 4 As shown, in the delay buffer unit 10 in the first row and first column, the control pole of the control switch NM1 in the delay adjustment subunit 11 is connected to the word line WLP. <0> The first terminal of control switch NM1 is connected to the first terminal of the first-stage inverter P1 and the first terminal of the memristor RRAM. The second terminal of control switch NM1 is connected to the source line SLP. <0> Connect the second terminal of the memristor to the bit line BL. <0> Connections. The connection methods of the delay buffer units 10 on other rows and columns to the word lines, bit lines and source lines are similar and will not be described in detail here.

[0124] The operation method of the computing device is explained below.

[0125] In at least one embodiment of this disclosure, the operation method of the computing device includes: controlling at least one delay processing combination in a delay computing array via 2N word lines according to a combination of control signals, the combination of control signals including 2N first control signals respectively applied to the 2N word lines; applying corresponding input signals to the input terminals of the at least one delay processing combination; and receiving output signals after delay processing of the corresponding input signals at the output terminal of the at least one delay processing combination.

[0126] For example, the operation method further includes: for each delay buffer unit in the delay processing combination, selecting an operation mode according to the corresponding input signal, and performing an operation corresponding to the operation mode according to the control signal combination.

[0127] As described above, the input signal KEEP can control whether the delay calculation array 100 is in the first operating mode or the second operating mode.

[0128] In the first operating mode, the bit line of the column containing the delay buffer unit is connected to the first operating voltage terminal, the source line of the row containing the delay buffer unit is connected to the second operating voltage terminal, and a first processing operation is performed on the memristor in the delay buffer unit according to the first control signal corresponding to the delay buffer unit. The first operating voltage terminal may be, for example, a power supply terminal that provides the first processing operating voltage, and the second operating voltage terminal may be, for example, a ground terminal.

[0129] For example, when the input signal KEEP received by the input terminals of the two delay chains 20 of the delay processing combination 30 controls the delay adjustment subunit 11 in the delay buffer unit 10 to disconnect from the first-stage inverter P1, the memristor RRAM can be initialized, set, reset, and read, among other first processing operations. It should be noted that in the first operating mode, the input signal KEEP remains at a constant low or high level, without any edge-triggered signals (e.g., rising or falling edge trigger signals), therefore the inverter is not triggered to flip, and no delay is generated on the delay chain.

[0130] Figure 5A This is a schematic diagram illustrating a set or initialization operation on a delay computing array, provided by at least one embodiment of the present disclosure. The delay computing array is, for example, composed of... Figure 1A The delay buffer unit shown is configured as follows. For example, when performing a set or initialization operation on the delay calculation array 100, the input signal KEEP is kept low to disconnect the conductive path between the delay adjustment subunit and the first-stage inverter P1; a column in the delay calculation array is selected via word lines WLN and WLP, for example via word line WLN. <0> and WLP <0> Selecting the first column in the delay calculation array turns on the control switch NM1 of the N delay buffer units 10 in the first column, and causes the bit line BL of the selected first column to be... <0> Connect to the DAC power supply (the bit lines of other columns not selected are all grounded); select the target delay buffer unit via source lines SLP and SLN to set or initialize the memristor in the target delay buffer unit, for example, Figure 5A As shown, the circled delay buffer units are the target delay buffer units. That is, the first, third, and fourth delay buffer units in the first column are the target delay buffer units. The source lines SLP of the rows corresponding to these target delay buffer units are... <0> SLP <1> SLN <1> Ground the circuit and connect the source lines of the remaining rows to the power supply terminal DAC. This applies a set voltage (SET) or an initialization voltage (FORM) to the memristor in the target delay buffer unit, thereby reducing the resistance value of the memristor.

[0131] Figure 5B This diagram illustrates a reset operation for a delay calculation array, provided in at least one embodiment of the present disclosure. For example, during a reset operation of the delay calculation array 100, the input signal KEEP is kept low to disconnect the conductive path between the delay adjustment subunit and the first-stage inverter P1; a column in the delay calculation array is selected via word lines WLN and WLP, for example, via word line WLN. <0> and WLP <0> Selecting the first column in the delay calculation array turns on the control switch NM1 of the N delay buffer units 10 in the first column, and causes the bit line BL of the selected first column to be... <0> Ground (bit lines of other columns not selected are all connected to the power supply DAC); select the target delay buffer cell via source lines SLP and SLN to reset the memristor in the target delay buffer cell, for example, Figure 5B As shown, the circled delay buffer units are the target delay buffer units. That is, the first, third, and fourth delay buffer units in the first column are the target delay buffer units. The source lines SLP of the rows corresponding to these target delay buffer units are... <0> SLP <1> SLN <1> Connect the power supply DAC and ground the source lines of the remaining rows to apply a reset voltage RESET to the memristor in the target delay buffer unit, thereby increasing the resistance value of the memristor.

[0132] The process of reading from a memristor is similar to that described above and will not be repeated here. It should be noted that the initialization operation for a memristor only needs to be performed once, while the set or reset operations can be performed multiple times to adjust (program) the memristor's resistance value. For example, after setting or resetting the memristor, in traditional practice, a read operation can be performed to verify whether the memristor's resistance value has reached the expected value. If the memristor's resistance value has not reached the expected value, the set or reset operation can be performed again until the memristor's resistance value reaches the expected value.

[0133] In the second operating mode, the bit lines of the column containing the delay buffer unit and the source lines of the row containing the delay buffer unit are connected to the first operating voltage terminal, and a calculation operation or a calibration read operation is performed on at least one delay processing combination according to the control signal combination. The first operating voltage terminal may be, for example, a ground terminal.

[0134] For example, when the input signal received at the input terminals of the two delay chains 20 of the delay processing combination 30 is electrically connected to the delay adjustment subunit in the KEEP control delay buffer unit 10, a certain cumulative delay (e.g., t_DLP) relative to the input signal can be obtained from the output terminals of the two delay chains 20. <0> or t_DLN <0> The cumulative delay of the output signal can be, for example, a delay adjusted by a memristor, so that the difference ΔT between the cumulative delays of two adjacent delay chains 20 is equal to the difference between the memristor-adjusted delays of the two adjacent chains.

[0135] In the second operating mode, calculation operations or calibration read operations can be performed on the delay calculation array 100, thereby enabling the acquisition of delay calculation results or delay read results from the output of the delay chain. For example, for... Figure 4 The delay calculation array 100 shown can obtain differential delay calculation results or differential delay reading results from the output of the delay processing combination 30.

[0136] For example, in at least one example of the embodiments of this disclosure, a calculation operation is performed on at least one selected delay processing combination according to a combination of control signals. A specific example may include: applying 2N first control signals as calculation input signals to 2N delay buffer units in at least one delay processing combination through 2N word lines; and obtaining differential delay calculation results from the output of at least one delay processing combination.

[0137] For example, when performing calculations on the delay calculation array 100, an input signal KEEP, which is a rising edge trigger signal, is input to at least one delay processing combination 30 to conduct the conductive path between the delay adjustment subunit and the first-stage inverter P1; the N bit lines BL and 2N source lines SLP and SLN, where the 2N delay buffer units on the two rows of delay chains in the at least one delay processing combination 30 are located, are all grounded; and 2N first control signals are applied to the 2N delay buffer units on the two rows of delay chains in the at least one delay processing combination 30 as calculation input signals through the 2N word lines WLN and WLP.

[0138] When all the first control signals are low (corresponding to input element V1 being 1), the memristors RRAM in the 2N delay buffer units are connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the cumulative delay of the N delay buffer units in each delay chain is t1 + t2 + ... + tN (t1, t2, ..., tn are the delays of the N delay buffer units, respectively). For example, if the cumulative delay of the first delay chain in each delay processing combination is T1 and the cumulative delay of the second delay chain is T2, then the differential delay calculation result ΔT obtained from the output terminal of the delay processing combination 30 is ΔT = T1 - T2. When all the first control signals are high (corresponding to input element V1 being 0), the memristor RRAM is bypassed, and none of the memristors RRAM in the 2N delay buffer units are connected between the first-stage inverter P1 and the first operating voltage terminal 1. At this time, the cumulative delay of the N delay buffer units in each delay chain is the sum of the intrinsic delays of the N delay buffer units. When the intrinsic delays of two adjacent delay chains are equal, the differential delay calculation result ΔT obtained from the output terminal of the delay processing combination 30 is 0. In at least one example of the embodiments of this disclosure, calculation operations can be performed on multiple delay processing combinations simultaneously, thereby improving calculation efficiency while ensuring high accuracy. Furthermore, the IR voltage drop problem caused by line resistance is avoided during calculation, and the matrix operation scale can be scaled up on a large scale, thereby realizing large-scale high-precision matrix operations.

[0139] For example, in at least one example of the embodiments of this disclosure, a calibration read operation is performed on at least one selected delay processing combination according to a combination of control signals. A specific example may include: determining a target column in at least one delay processing combination for performing the calibration read operation; applying a first control signal for accessing a memristor and a first control signal for bypassing a memristor to two delay buffer units on the target column in at least one delay processing combination, respectively; applying a first control signal for bypassing a memristor to multiple columns in at least one delay processing combination other than the target column; and obtaining a differential delay read result from the output of at least one delay processing combination.

[0140] Figure 6 This is a schematic diagram illustrating a calibration read operation on a delay calculation array, provided in at least one embodiment of the present disclosure. The calibration read operation can be used to read the delay difference between two adjacent delay buffer units 10 (differential units) in the same column of the delay processing assembly 30, and to verify whether the signed weights represented by the delay difference between the two delay buffer units 10 (differential units) have been programmed to the expected weights.

[0141] like Figure 6 As shown, for example, taking the reading of the delay difference between two adjacent delay buffer cells representing a signed weight in the first column as an example, via the word line WLP <0> A low-level first control signal is applied to the odd-numbered row delay buffer cells in the first column, via word line WLN. <0> A high-level first control signal is applied to the even-numbered row delay buffer unit in the first column, and a high-level first control signal is applied to the word lines WLP and WLN of the remaining columns. In this way, the delay difference between the two delay buffer units in the first column of each delay processing combination 30 can be obtained from DLP and DLN at the output of each delay processing combination 30, that is, the differential delay read result, thereby realizing efficient parallel read verification operation.

[0142] For example, after reading the differential delay read results of two adjacent delay buffer units, it can be determined whether to perform a first processing operation on at least one memristor in the two delay buffer units on the target column based on the differential delay read results. For example, if the differential delay read result does not reach the expected weight value, the first processing operation can be performed again on at least one memristor in the two delay buffer units. For example, a set operation or reset operation can be performed on one of the memristors again to increase or decrease the resistance value of the memristor, thereby adjusting the delay of the delay buffer unit where the memristor is located, and thus adjusting the delay difference between the two delay buffer units to the corresponding expected weight value. Therefore, the verification read operation of the delay calculation array provided by at least one embodiment of this disclosure can enable the delay of the differential unit to accurately represent the expected weight value, thereby effectively improving the accuracy of the calculation.

[0143] For example, in at least one example of the embodiments of this disclosure, a calibration read operation is performed on at least one selected delay processing combination according to a combination of control signals. A specific example may include: determining at least one delay processing combination for performing the calibration read operation; applying a first control signal for bypassing the memristor to a plurality of delay buffer units in the at least one delay processing combination; and obtaining a differential delay read result from the output of the at least one delay processing combination.

[0144] After the delay calculation array 100 is fabricated, due to process limitations, the intrinsic delays of the two delay chains in each delay combination may have a large mismatch. When the mismatch between the intrinsic delays of the two delay chains is large, it will seriously affect the accuracy of the calculation. Therefore, at least one embodiment of this disclosure also provides a calibration read operation, which can read the difference (mismatch) between the intrinsic delays of the two delay chains in the delay processing combination, and then eliminate the mismatch through the intrinsic delay calibration module provided in this disclosure.

[0145] like Figure 6 As shown, for example, taking the reading of two lines of delay chain in the first delay processing combination as an example, via word line WLP <0> WLP <1> ... WLP <m>A high-level first control signal is applied to the m delay buffer units in the first line of the delay chain, via the word line WLN. <0> WLN <1> ..., WLN <m>A high-level first control signal is also applied to the m delay buffer units in the second delay chain, that is, the memristor in each delay buffer unit is bypassed, and the delay controlled by the memristor is not serially inserted into the delay chain. At this time, the cumulative delay output from the output of the two delay chains only includes the intrinsic delay of the inverter, and the differential delay read result obtained from the output of the delay processing combination is the deviation of the intrinsic delay of the two delay chains. Subsequent calibration operations based on this differential delay read result can make the intrinsic delay of the two delay chains equal, thereby helping to improve the accuracy of the calculation.

[0146] In the embodiments of this disclosure, the differential delay calculation result or differential delay read result obtained from the output of at least one delay processing combination is a calculation result in the time domain. Therefore, it is also necessary to convert the calculation result in the time domain into an analog signal (delayed charge conversion (TQC) process), and further convert the analog signal into a digital signal for subsequent data processing.

[0147] The computing device provided in at least one embodiment of this disclosure further includes at least one delayed charge conversion module and at least one analog-to-digital conversion module. The at least one delayed charge conversion module is connected to a delay processing assembly and configured to quantize the delay difference between the output signals of two delay chains in the delay processing assembly into a voltage output signal. The at least one analog-to-digital conversion module is connected to the delayed charge conversion module and configured to convert the voltage output signal from the delayed charge conversion module into a digital signal.

[0148] Since the time-delayed charge conversion (TQC) process is time-consuming, while the analog-to-digital conversion (ADC) process is shorter, multiple time-delayed charge conversion modules can share a single ADC module. For example, in at least one embodiment of this disclosure, the computing device may include multiple time-delayed charge conversion modules connected to a single ADC module to time-division multiplex the ADC module, thereby improving conversion efficiency.

[0149] For example, Figure 7 The computing device 200 shown includes a delay computing array 100, a delay charge conversion module 40, and an analog-to-digital conversion module 50. Three delay processing combinations 30_A, 30_B, and 30_C are shown in the figure as examples. Each delay charge conversion module 40 is connected to the output of one delay processing combination 30 of the delay computing array. For example, delay charge conversion module TQC_A is connected to delay processing combination 30_A, delay charge conversion module TQC_B is connected to delay processing combination 30_B, and delay charge conversion module TQC_B is connected to delay processing combination 30_B, thereby quantizing the delay difference of the output signals of the two rows of delay chains 20 in the corresponding delay processing combination 30 into voltage output signals.

[0150] For example, the delayed charge conversion module 40 includes a current mirror, current mirror control logic 41, a capacitive digital-to-analog converter (CDAC), and corresponding digital control switches.

[0151] For example, in the TQC process, the delayed charge conversion module 40 uses low-power current mirror control logic 41 to ensure the timely start of the current mirror, thereby controlling the CDAC to perform passive integration through the current mirror, and then quantifying the delay difference output by the delay processing combination 30.

[0152] Figure 8 This is a schematic diagram of the structure of an exemplary current mirror control unit provided in at least one embodiment of the present disclosure; Figure 9 This is a timing diagram illustrating a delayed charge conversion process provided for at least one embodiment of the present disclosure. The following is in conjunction with... Figure 8 and Figure 9 A brief explanation of the TQC process.

[0153] For example, KEEP represents a rising edge trigger signal provided at the input INT of the delay processing combination 30. After the rising edge trigger calculation operation of the KEEP signal, the first delay chain (positive differential chain) and the second delay chain (negative differential chain) in the delay processing combination 30 generate rising edge output signals PULSE_A and PULSE_B respectively after a certain time interval. For example, it is necessary to generate early rising edge signals PULSE_AE and PULSE_BE corresponding to the output signals PULSE_A and PULSE_B respectively before the PULSE_A and PULSE_B output signals, so as to be used for the subsequent generation of the current source early start control signals INPB and INNB. Figure 9 As shown, integration control signals INP and INN are generated during the interval between the rising edges of the output signals PULSE_A and PULSE_B. During this time period, Figure 8 Integration begins at the integration point Vx shown. Outside of this time period, the integration control signals INP and INN are not activated to avoid internal dissipation of the current mirror. For example, the INNB signal is generated during the interval between the output signal PULSE_B and the early rising edge signal PULSE_BE to start the pull-down current mirror in advance, thereby ensuring that the current is relatively accurate during actual integration.

[0154] For example, in at least one embodiment of this disclosure, in order to avoid mismatch between positive and negative current mirrors, a self-zeroing process of the current can be added. This process can be performed once every few KEEP cycles, for example, during the low level of KEEP, thereby avoiding additional time overhead.

[0155] Figure 10 A schematic diagram of an exemplary quantization circuit provided for at least one embodiment of this disclosure; Figure 11 A timing diagram illustrating a forward computation process provided in at least one embodiment of this disclosure; the following is in conjunction with... Figure 10 and Figure 11 A brief explanation of the sampling and quantization process of the two-line delay chain in the delay processing combination.

[0156] For example, such as Figure 10 As shown, the rising edge output signals of two adjacent delay chains (e.g., positive difference chain and negative difference chain) in a delay processing combination 30 are respectively connected to the control switches SP / SN of the current source / current sink. The delay difference between the rising edge output signals of two adjacent delay chains determines the integration time on the CDAC. That is, within one KEEP cycle, channel CH1 is in the sampling state, the top plate of the capacitor of channel CH1 is integrated by current (CH1=1), the bottom plate is connected to VCM (SAMP_1=1), and TQC is in a fully parallel state. After the TQC quantization process is completed, the integrated voltage on the capacitor (the voltage output signal in this embodiment of the disclosure) is ADC quantized in the next cycle of the KEEP cycle signal to obtain the digital output. Figure 11 As shown, in the next KEEP cycle, the integrated voltage of channel CH1 is sequentially quantized across multiple differential rows by the ADC (CONV_1 = 1), while channel CH2 is in a fully parallel sampling state. This alternating sampling and quantization process improves the system throughput.

[0157] It should be noted that, because there are multiple inverters in a single delay chain, and due to factors such as process variations, the intrinsic delays of two delay chains within the same delay processing combination may differ significantly. This difference in intrinsic delay introduces a substantial offset. For example... Figure 12 The simulation results show that when 128 delay buffer units are connected in series, the standard deviation of the intrinsic delay difference distribution of the delay chain reaches ~3n, which is comparable to the quantization range of the subsequent delay charge conversion process (TQC) and analog-to-digital conversion process (ADC). This will seriously consume the dynamic range of the ADC.

[0158] Therefore, the computing device provided in at least one embodiment of this disclosure may further include an intrinsic delay calibration module, which is connected to the delay processing assembly 30 and configured to calibrate the intrinsic delays of the two delay chains 20 so that the intrinsic delays of the two delay chains match. Figure 13 As shown, the intrinsic delay calibration module may include multiple delay calibration units (CBs). For example, before calculation, by applying a first control signal corresponding to a high level of input 0 to all delay buffer units in the delay calculation array, the total delay of one delay chain is read. At this point, the total delay consists only of the intrinsic delay and does not include the delay adjusted by the memristor. Based on the comparison result of the total intrinsic delay of the two delayed chains, the additional delay calibration units (CBs) are selectively connected or bypassed, thereby adjusting the intrinsic delay of the two delayed chains to the same duration to avoid the erosion of the ADC's dynamic range by process variations.

[0159] For example, a simulation is performed using a single ADC as an example of a combination of eight 128-length (the number of delay buffer units in a single delay chain) delay processing units sharing one ADC, to calculate the system's power consumption, energy efficiency, and computing power.

[0160] For example, if the cycle of a KEEP is 250n, then the power consumption of the delay calculation array is 0.5C*V2*#=0.5*2f*0.452*8*128*2 / 250n (VDD is set to 0.45 to avoid interference during forward calculation). The delay calculation array consumes approximately 1 / 4 of the total system power consumption (system circuit-level simulation results). For example, when completing 128*8 1b_in-signed3b_weight-8b_out operations within one KEEP cycle, the system's energy efficiency is 128*8 / 250n / (0.5*2f*0.452*8*128*2*4 / 250n)≈1230TOPS / W (accuracy premise 1-s_3-8, 128 accumulation). For example, the computing power achieved by the aforementioned set of units (8 delay processing combinations with a length of 128) is 128*8 / 250n to 4.1 GOPS (8*128*2=2k), and this value increases proportionally as the array size increases. Compared to ISSCC in recent years, the computing device provided in this disclosure embodiment can achieve higher computing power with the same unit capacity.

[0161] The simulation results above demonstrate that the computing device and its operation method provided in at least one embodiment of this disclosure can achieve high-precision, low-energy-consumption large-scale matrix operations and improve the computational efficiency of matrix-vector multiplication operations.

[0162] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0163] The following points should be noted regarding this disclosure:

[0164] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0165] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0166] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0167] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.< / m> < / m> < / m-1:0>

Claims

1. A delay buffer unit, comprising: First-stage inverter, second-stage inverter, and delay adjustment subunit; The input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit; The input terminal of the second-stage inverter is connected to the output terminal of the first-stage inverter, and the output terminal of the second-stage inverter serves as the output terminal of the delay buffer unit. The delay adjustment subunit is connected between a first terminal and a first operating voltage terminal of the first-stage inverter, and the delay adjustment subunit includes a memristor and is configured to adjust the propagation delay of the first-stage inverter using the memristor according to a first control signal. The delay adjustment subunit further includes a control switch. The control switch includes a first pole, a second pole, and a control pole. The control pole receives the first control signal to turn the first pole and the second pole on or off according to the first control signal. The first pole of the control switch is electrically connected to the first terminal of the first-stage inverter. The first terminal of the memristor is electrically connected to the first pole of the control switch and the first terminal of the first-stage inverter, and the second terminal of the memristor is electrically connected to the first operating voltage terminal.

2. The delay buffer unit according to claim 1, wherein, The second pole of the control switch is electrically connected to the first operating voltage terminal, or electrically connected to a second operating voltage terminal that is different from the first operating voltage terminal.

3. A method for operating the delay buffer unit as described in claim 1, comprising: The input signal of the delay buffer unit is received at the input terminal of the first-stage inverter, and the output signal of the delay buffer unit is output at the output terminal of the second-stage inverter. The delay adjustment subunit receives the first control signal and controls the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal. The delay adjustment subunit further includes a control switch, which comprises a first terminal, a second terminal, and a control terminal. The first terminal of the memristor is electrically connected to the first terminal of the control switch. The delay adjustment subunit receives the first control signal and controls the memristor to adjust the transmission delay of the first-stage inverter according to the first control signal, including: The control switch controls whether the memristor is connected between the first terminal of the first stage inverter and the first operating voltage terminal according to the first control signal; The memristor is used to change the source degenerate resistance of the first-stage inverter according to the input signal, so as to adjust the propagation delay of the first-stage inverter.

4. The operating method according to claim 3, wherein, When the memristor is connected between the first terminal of the first stage inverter and the first operating voltage terminal according to the first control signal, the propagation delay of the first stage inverter is the propagation delay adjusted by the memristor. When the memristor is bypassed between the first terminal and the first operating voltage terminal of the first-stage inverter according to the first control signal, the propagation delay of the first-stage inverter is the intrinsic delay of the first-stage inverter.

5. The operating method according to claim 3 further includes: Disconnect the conductive path between the delay adjustment subunit and the first-stage inverter according to the input signal; The delay adjustment subunit is connected to a first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal.

6. The operating method according to claim 5, wherein, Connect the delay adjustment subunit to a first operating voltage terminal and a second operating voltage terminal to perform a first processing operation on the memristor according to the first control signal, including: Connect the second terminal of the control switch to the first operating voltage terminal, and connect the second terminal of the memristor to the second operating voltage terminal; The control switch is turned on according to the first control signal, so as to adjust the resistance value of the memristor by the first processing operation voltage between the first operating voltage terminal and the second operating voltage terminal.

7. The operating method according to claim 5, wherein, The first processing operation includes a set operation, a reset operation, a read operation, or an initialization operation.

8. A computing device, comprising: The delay calculation array includes 2M rows and N columns of delay buffer units, 2N word lines corresponding to the N columns, N bit lines corresponding to the N columns, and 2M source lines corresponding to the 2M rows. The N delay buffer units in each row are connected in series to form a delay chain. Each pair of adjacent delay chains constitutes a delay processing combination. The two delay chains in each delay processing combination receive the same input signal. In each delay processing combination, the two delay buffer units located in the same column are respectively connected to the two word lines corresponding to the same column; Each delay buffer unit includes a first-stage inverter, a second-stage inverter, and a delay adjustment subunit. The input terminal of the first-stage inverter serves as the input terminal of the delay buffer unit. The input of the second-stage inverter is connected to the output of the first-stage inverter, and the output of the second-stage inverter serves as the output of the delay buffer unit. The delay adjustment subunit is connected to the first terminal of the first-stage inverter, and is also connected to the source line corresponding to the row, the bit line corresponding to the column, and the word line corresponding to the column. The delay adjustment subunit includes a memristor and is configured to control the adjustment of the transmission delay of the first-stage inverter using the memristor according to a first control signal provided by the corresponding word line. The delay adjustment subunit further includes a control switch, which comprises a first pole, a second pole, and a control pole. The control electrode of the control switch is connected to the word line corresponding to the column where the delay adjustment subunit is located; the first electrode of the control switch is connected to the first terminal of the first-stage inverter and the first terminal of the memristor; and the second electrode of the control switch is connected to the source line corresponding to the row where the delay adjustment subunit is located. The second terminal of the memristor is connected to the bit line corresponding to the column where the delay adjustment subunit is located.

9. The computing device according to claim 8, further comprising: At least one delayed charge conversion module is connected to the delayed processing assembly and configured to quantize the delay difference of the output signals of the two delayed chains in the delayed processing assembly into a voltage output signal; At least one analog-to-digital converter module is connected to the delayed charge conversion module and configured to convert the voltage output signal output from the delayed charge conversion module into a digital signal.

10. The computing device according to claim 9, wherein, The computing device includes multiple time-delayed charge conversion modules. The plurality of delayed charge conversion modules are connected to one of the analog-to-digital conversion modules to time-division multiplex the analog-to-digital conversion module.

11. The computing device according to claim 8, further comprising: The intrinsic delay calibration module is connected to the delay processing module and configured to calibrate the intrinsic delay of the two delay chains so that the intrinsic delay of the two delay chains matches.

12. A method of operating a computing device as claimed in claim 8, comprising: At least one delay processing combination in the delay calculation array is controlled via the 2N word lines according to a combination of control signals, wherein the combination of control signals includes 2N first control signals respectively applied to the 2N word lines; A corresponding input signal is applied to the input terminal of the at least one delay processing combination, and an output signal after delay processing of the corresponding input signal is received at the output terminal of the at least one delay processing combination. For each delay buffer unit in the delay processing combination, an operation mode is selected according to the corresponding input signal, and an operation corresponding to the operation mode is executed according to the control signal combination.

13. The operating method according to claim 12, wherein, The operation mode includes a first operation mode and a second operation mode, and the operation method further includes: In the first operating mode, the bit line of the column where the delay buffer unit is located is connected to the first operating voltage terminal, the source line of the row where the delay buffer unit is located is connected to the second operating voltage terminal, and the first processing operation is performed on the memristor in the delay buffer unit according to the first control signal corresponding to the delay buffer unit. In the second operating mode, the bit line of the column where the delay buffer unit is located and the source line of the row where it is located are connected to the first operating voltage terminal, and a calculation operation or a calibration read operation is performed on the at least one delay processing combination according to the control signal combination.

14. The operating method according to claim 13, wherein, Perform a calculation operation on at least one selected delay processing combination based on a combination of control signals, including: 2N first control signals are applied as calculation input signals to 2N delay buffer units in the at least one delay processing combination through the 2N word lines; Obtain the differential delay calculation result from the output of the at least one delay processing combination.

15. The operating method according to claim 13, wherein, Perform a calibration read operation on at least one selected delay processing combination based on a combination of control signals, including: Determine the target column in the at least one delay processing combination for performing a calibration read operation; A first control signal for accessing the memristor and a first control signal for bypassing the memristor are respectively applied to two delay buffer units on the target column in the at least one delay processing combination. A first control signal for bypassing the memristor is applied to multiple columns in the at least one delay processing combination other than the target column; Obtain the differential delay read result from the output of the at least one delay processing combination.

16. The operating method according to claim 15, further comprising: Based on the differential delay read result, determine whether to perform the first processing operation on at least one memristor in one of the two delay buffer units on the target column; If the differential delay read result does not reach the expected weight value, the first processing operation is performed again on the at least one memristor.

17. The operating method according to any one of claims 13-15, wherein, The first processing operation includes a set operation, a reset operation, a read operation, or an initialization operation.

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