Semiconductor Structure and Method for Forming the Same

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor channel extending along a first direction, and the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence along the first direction; a bit line structure extending along a second direction, and the bit line structure is in contact connection with an end of the first doped region away from the channel region; a gate structure extending along a third direction, and the gate structure penetrates the semiconductor channel of the channel region along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; a first support layer extending along the third direction, and the first support layer penetrates the semiconductor channel of the first doped region along the third direction; a second support layer extending along the third direction, and the second support layer penetrates the semiconductor channel of the second doped region along the third direction. The embodiments of the present disclosure are at least beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] As the integration density of dynamic memories develops towards a higher level, higher requirements are imposed on the arrangement of transistors and the size of transistors in a dynamic memory array structure. However, due to limitations in manufacturing factors such as lithography machines, there is a limit to the reduction of their critical dimensions. Therefore, how to fabricate chips with a higher storage density on a single wafer is the research direction of many scientific researchers and semiconductor practitioners.

[0003] Currently, the morphology of the gate structure and the spacing between gate structures in a dynamic memory depend on the process conditions for forming the gate structure. However, the process conditions for forming the gate structure cannot precisely control the morphology of the gate structure, which may result in different morphologies of different gate structures and affect the performance of the dynamic memory. In addition, the structural stability of the stacked transistors in the dynamic memory also needs to be improved. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] On the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a semiconductor channel extending in a first direction, and the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence along the first direction; a bit line structure extending in a second direction, and the bit line structure is in contact connection with an end of the first doped region away from the channel region; a gate structure extending in a third direction, and the gate structure penetrates the semiconductor channel of the channel region along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; a first support layer extending in the third direction, and the first support layer penetrates the semiconductor channel of the first doped region along the third direction; a second support layer extending in the third direction, and the second support layer penetrates the semiconductor channel of the second doped region along the third direction.

[0006] In some embodiments, a part of the gate structure surrounded by the semiconductor channel has opposite first and second ends in the first direction, the first end is in contact with the semiconductor channel of the first doped region, and the second end is in contact with the semiconductor channel of the second doped region.

[0007] In some embodiments, a part of the gate structure surrounded by the semiconductor channel has opposite first and second ends in the first direction, the first end is in contact with the semiconductor channel of the channel region adjacent to the first doped region, and the second end is in contact with the semiconductor channel of the channel region adjacent to the second doped region.

[0008] In some embodiments, the gate structure includes a gate dielectric layer and a gate conductive layer. The gate conductive layer extends in a third direction and penetrates the semiconductor channel of the channel region in the third direction. The gate dielectric layer is located between the gate conductive layer and the semiconductor channel.

[0009] In some embodiments, the first doped region includes a first region and a second region arranged in sequence along a first direction. Among them, the first region is far from the channel region, the second region is adjacent to the channel region, and the semiconductor channel of the first region includes a first metal-semiconductor compound layer in contact with the bit line structure; the first support layer penetrates the first metal-semiconductor compound layer of the first region.

[0010] In some embodiments, on a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel of the first doped region surrounding the first support layer is annular.

[0011] In some embodiments, the semiconductor structure further includes: a lower electrode layer in contact connection with one end of the second doped region far from the channel region; a capacitor dielectric layer covering the surface of the lower electrode layer not in contact with the semiconductor channel; and an upper electrode layer covering the surface of the capacitor dielectric layer far from the lower electrode layer.

[0012] In some embodiments, the second doped region includes a third region and a fourth region arranged in sequence along a first direction. Among them, the fourth region is far from the channel region, the third region is adjacent to the channel region, and the semiconductor channel of the fourth region includes a second metal-semiconductor compound layer in contact with the lower electrode layer; the second support layer penetrates the second metal-semiconductor compound layer of the fourth region.

[0013] In some embodiments, on a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel of the second doped region surrounding the second support layer is annular.

[0014] In some embodiments, the material of the semiconductor channel of the first doped region includes silicon, and the material of the semiconductor channel of the second doped region includes silicon; the material of the semiconductor channel of the channel region includes silicon, or the material of the semiconductor channel of the channel region includes silicon germanide.

[0015] In some embodiments, along the second direction, the ratio of the width of the first support layer to the width of the semiconductor channel of the first doped region is 1 / 3 to 2 / 3.

[0016] In some embodiments, along the second direction, the ratio of the width of the second support layer to the width of the semiconductor channel of the second doped region is 1 / 3 to 2 / 3.

[0017] Another aspect of the embodiments of the present disclosure further provides a method for forming a semiconductor structure, including: forming a semiconductor channel extending along a first direction, and the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence along the first direction; forming a bit line structure extending along a second direction, and the bit line structure is in contact connection with one end of the first doped region away from the channel region; forming a gate structure extending along a third direction, and the gate structure penetrates the semiconductor channel of the channel region along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; forming a first support layer extending along the third direction, and the first support layer penetrates the semiconductor channel of the first doped region along the third direction; forming a second support layer extending along the third direction, and the second support layer penetrates the semiconductor channel of the second doped region along the third direction.

[0018] In some embodiments, the step of forming the semiconductor channel includes: providing a substrate; forming a first stacked structure on the substrate, which is arranged at intervals along the second direction and extends along the first direction. In the third direction, the first stacked structure includes a semiconductor layer arranged at intervals and a first isolation layer between the semiconductor layers. The first stacked structure includes a first part, a second part, and a third part arranged in sequence along the first direction; performing patterning on the first stacked structure to form an initial first opening penetrating the first part along the third direction, an initial second opening penetrating the second part along the third direction, and an initial third opening penetrating the third part along the third direction; forming a semiconductor channel based on the remaining semiconductor layer.

[0019] In some embodiments, forming the semiconductor channel based on the remaining semiconductor layer includes: forming an epitaxial layer on the sidewall of the semiconductor layer exposed by the initial second opening, and the epitaxial layer encloses the second opening, and the epitaxial layer serves as the semiconductor channel of the channel region.

[0020] In some embodiments, forming the semiconductor channel based on the remaining semiconductor layer includes: forming a first metal semiconductor compound layer on the sidewall of the semiconductor layer exposed by the initial first opening, and the first metal semiconductor compound layer encloses the first opening, and the first metal semiconductor compound layer and the semiconductor layer between the first metal semiconductor compound layer and the channel region serve as the first doped region.

[0021] In some embodiments, forming the semiconductor channel based on the remaining semiconductor layer includes: forming a second metal semiconductor compound layer on the sidewall of the semiconductor layer exposed by the initial third opening, and the second metal semiconductor compound layer encloses the third opening, and the second metal compound semiconductor layer and the semiconductor layer between the second metal compound semiconductor layer and the channel region serve as the second doped region.

[0022] In some embodiments, forming the gate structure includes: forming a gate dielectric layer on the semiconductor channel surface of the channel region exposed in the initial second opening surrounded by the second opening and the first isolation layer; filling a gate conductive layer in the second opening outside the gate dielectric layer and in the initial second opening surrounded by the first isolation layer outside the gate dielectric layer, and the gate conductive layer and the gate dielectric layer constitute the gate structure.

[0023] In some embodiments, forming the first support layer includes: filling a support material in the first opening and in the initial first opening surrounded by the first isolation layer to form the first support layer.

[0024] In some embodiments, forming the second support layer includes: filling a support material in the third opening and in the initial third opening surrounded by the first isolation layer to form the second support layer.

[0025] In some embodiments, along the second direction, the ratio of the width of the initial second opening to the width of the semiconductor layer is 2 / 5 to 4 / 5.

[0026] In some embodiments, the forming method further includes: forming a second stacked structure extending along the second direction on the substrate, the second stacked structure is in contact with one side of the first part away from the second part, along the third direction, the second stacked structure includes sacrificial layers arranged at intervals and a second isolation layer between the sacrificial layers, the sacrificial layer is in contact with the semiconductor layer of the first part, and the second isolation layer is in contact with the first isolation layer of the first part; removing the sacrificial layers; forming a bit line structure between adjacent second isolation layers.

[0027] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0028] In the above technical solution, the semiconductor channels of the first doping region and the second doping region are respectively used as the source and drain of the transistor, and the semiconductor channel of the channel region is used as the channel of the transistor. The gate structure extending along the third direction penetrates the semiconductor channel of the channel region, and the morphology of the gate structure is restricted by the semiconductor channel of the channel region, so as to accurately control the performance of the transistor. In addition, the first support layer penetrates the semiconductor channel of the first doping region along the third direction, and the second support layer penetrates the semiconductor channel of the second doping region along the third direction, so that the semiconductor channels arranged in the third direction are supported by the first support layer and the second support layer, and have better structural stability, which is beneficial to improving the reliability of the memory in practical applications. Description of the Drawings

[0029] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 It is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 2 It is a schematic cross-sectional structure diagram of a semiconductor channel in a semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction;

[0032] Figure 3 It is a schematic cross-sectional structure diagram of a semiconductor channel in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction;

[0033] Figure 4 It is a schematic cross-sectional structure diagram of a semiconductor channel in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction;

[0034] Figure 5 It is a schematic cross-sectional structure diagram of a semiconductor channel in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction;

[0035] Figures 6 to 35 It is a schematic diagram of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0036] As can be seen from the background art, at present, the morphology of the gate structure in the memory structure needs to be improved, and the structural stability of the stacked transistors in the memory structure is poor.

[0037] Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. In the semiconductor structure, the semiconductor channels of the first doped region and the second doped region are respectively used as the source and drain of a transistor, the semiconductor channel of the channel region is used as the channel of the transistor, and the gate structure extending in the third direction penetrates the semiconductor channel of the channel region. The morphology of the gate structure is restricted by the semiconductor channel of the channel region, thereby accurately controlling the performance of the transistor. In addition, the first support layer penetrates the semiconductor channel of the first doped region in the third direction, and the second support layer penetrates the semiconductor channel of the second doped region in the third direction, so that the semiconductor channels arranged in the third direction are supported by the first support layer and the second support layer, having better structural stability, and further improving the structural stability of the stacked transistors in the semiconductor structure.

[0038] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help the reader better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be implemented.

[0039] Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is a schematic cross-sectional structure diagram of semiconductor channels in a semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction; Figure 3 is a schematic cross-sectional structure diagram of semiconductor channels in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction; Figure 4 is a schematic cross-sectional structure diagram of semiconductor channels in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction; Figure 5 is a schematic cross-sectional structure diagram of semiconductor channels in another semiconductor structure provided by an embodiment of the present disclosure in a plane perpendicular to the third direction.

[0040] Refer to Figures 1 to 5, the semiconductor structure includes: a semiconductor channel 100 extending along a first direction X, and the semiconductor channel 100 includes a first doped region I, a channel region II, and a second doped region III arranged in sequence along the first direction X; a bit line structure 110 extending along a second direction Y, and the bit line structure 110 is in contact connection with one end of the first doped region I away from the channel region II; a gate structure 120 extending along a third direction Z, and the gate structure 120 penetrates the semiconductor channel 100 of the channel region II along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect pairwise; a first support layer 130 extending along the third direction Z, and the first support layer 130 penetrates the semiconductor channel 100 of the first doped region I along the third direction Z; a second support layer 140 extending along the third direction Z, and the second support layer 140 penetrates the semiconductor channel 100 of the second doped region III along the third direction Z.

[0041] Reference Figure 1 , a plurality of semiconductor channels 100 can be arranged in an array along the second direction Y and the third direction Z. Among them, the semiconductor channels 100 of the first doped region I and the semiconductor channels 100 of the second doped region III are used as the source and drain of the transistor, and the semiconductor channels 100 of the channel region II are used as the channel of the transistor. The gate structure 120 extending along the third direction Z penetrates the semiconductor channels 100 of the channel region II, and the semiconductor channels 100 of the channel region II are used to limit the topography of the gate structure 120, so as to ensure that the gate structure 120 has a better topography, and further improve the performance of the semiconductor structure. In addition, the gate structure 120 also provides support for the semiconductor channel 100, which is beneficial to improving the structural stability of the semiconductor structure.

[0042] In some embodiments, reference Figure 1 or Figure 4 , on a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 100 of the channel region II surrounding the gate structure 120 is annular, that is, the semiconductor channels 100 of the channel region II form a four-sided gate-all-around structure. In other embodiments, reference Figure 2 , on a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel 100 of the channel region II surrounding the gate structure 120 is U-shaped, that is, the semiconductor channels 100 of the channel region II form a three-sided gate-all-around structure.

[0043] The first support layer 130 penetrates the semiconductor channel 100 of the first doping region I along the third direction Z, and the second support layer 140 penetrates the semiconductor channel 100 of the second doping region III along the third direction Z, so that the semiconductor channels 100 arranged in the third direction Z have better structural stability under the support of the first support layer 130 and the second support layer 140, thereby improving the structural stability of the transistors stacked in the semiconductor structure. Among them, the materials of the first support layer 130 and the second support layer 140 can be insulating materials. In some embodiments, the materials of the first support layer 130 and the second support layer 140 can be the same insulating material. In this way, the first support layer 130 and the second support layer 140 can be formed simultaneously in the same manufacturing step, which is beneficial to reducing the manufacturing difficulty of the first support layer 130 and the second support layer 140. In one example, the materials of the first support layer 130 and the second support layer 140 are both silicon nitride with better supportability. In some other embodiments, the first support layer 130 and the second support layer 140 can also be different insulating materials.

[0044] The first doping region I and the second doping region III are doping regions. In some embodiments, the type of doping ions in the doping region can be different from the type of doping ions in the channel region II. Specifically, in one example, the doping ions in the doping region can be N-type ions, and the doping ions in the channel region II can be P-type ions. The P-type ions can be at least one of boron ions, indium ions, or gallium ions, and the N-type ions can be at least one of arsenic ions, phosphorus ions, or antimony ions. In another example, the doping ions in the doping region can be P-type ions, and the doping ions in the channel region II can be N-type ions. In some other embodiments, the type of doping ions in the doping region can also be the same as the type of doping ions in the channel region II, that is, the semiconductor channel 100 is used to form a junctionless field-effect transistor.

[0045] In some embodiments, the material of the semiconductor channel 100 in the first doping region I includes silicon, the material of the semiconductor channel 100 in the second doping region III includes silicon, and the material of the semiconductor channel 100 in the channel region II includes silicon. That is, the materials of the semiconductor channels 100 in the first doping region I, the second doping region III, and the channel region II are the same. In this way, it is beneficial to form an integrally formed semiconductor channel 100 in the same step, thereby facilitating the reduction of the preparation difficulty of the semiconductor channel 100. Moreover, silicon is a relatively common semiconductor material, and using silicon as the semiconductor channel 100 is also beneficial to reducing the preparation difficulty of the semiconductor channel 100.

[0046] In some embodiments, the material of the semiconductor channel 100 in the first doped region I includes silicon, the material of the semiconductor channel 100 in the second doped region III includes silicon, and the material of the semiconductor channel 100 in the channel region II includes silicon germanide. Silicon germanide has a high carrier mobility. Using silicon germanide as the semiconductor channel 100 in the channel region II is beneficial to improving the electrical performance of the transistor.

[0047] In some embodiments, the semiconductor structure may further include: a substrate (not shown), and the semiconductor channel 100, the bit line structure 110, the gate structure 120, the first support layer 130, and the second support layer 140 are all located on one side of the substrate. Among them, the material of the substrate may be a semiconductor material. In some embodiments, the material of the substrate is silicon. In other embodiments, the substrate may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0048] Continue to refer to Figure 1 , two semiconductor channels 100 arranged at intervals along the second direction Y correspond to the same bit line structure 110, and two semiconductor channels 100 arranged at intervals along the third direction Z correspond to the same gate structure 120. In practical applications, the number of semiconductor channels 100 corresponding to the same bit line structure 110 along the second direction Y is not limited, and the number of semiconductor channels 100 corresponding to the same gate structure 120 along the third direction Z is also not limited.

[0049] The gate structure 120 is used to turn on the channel region II based on a control signal to realize the transmission of carriers between the source and the drain. In some embodiments, the gate structure 120 includes a gate dielectric layer 121 and a gate conductive layer 122. The gate conductive layer 122 extends along the third direction Z, and the gate conductive layer 122 penetrates the semiconductor channel 100 of the channel region II along the third direction Z. The gate dielectric layer 121 is located between the gate conductive layer 122 and the semiconductor channel 100. The material of the gate conductive layer 122 is a conductive material. In some examples, the material of the gate conductive layer 122 may include at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium. In some embodiments, the material of the gate dielectric layer 121 may be silicon oxide. The process of forming silicon oxide on the semiconductor channel 100 of the channel region II with a material of silicon or silicon germanide by a thermal oxidation process is mature, which is beneficial to reducing the preparation difficulty of the gate dielectric layer 121. In other embodiments, the material of the gate dielectric layer 121 may also be silicon nitride or silicon oxynitride.

[0050] Refer to Figure 3, in some embodiments, the partial gate structure 120 surrounded by the semiconductor channel 100 has opposite first and second ends 1201 and 1202 in the first direction X. The first end 1201 is in contact with the semiconductor channel 100 of the first doped region I, and the second end 1202 is in contact with the semiconductor channel 100 of the second doped region III. That is, in the first direction X, the gate structure 120 penetrates the semiconductor channel 100 of the channel region II. Among them, the gate structure 120 in contact with the semiconductor channel 100 of the first doped region I is the gate dielectric layer 121, and the gate structure 120 in contact with the semiconductor channel 100 of the second doped region III is also the gate dielectric layer 121. Thus, it is beneficial to reduce the difficulty of forming a depletion layer in the semiconductor channel 100 of the channel region II by the gate structure 120, and further beneficial to improving the electrical performance of the semiconductor structure.

[0051] Reference Figure 4 , in some embodiments, the partial gate structure 120 surrounded by the semiconductor channel 100 has opposite first and second ends 1201 and 1202 in the first direction X. The first end 1201 is in contact with the semiconductor channel 100 of the channel region II adjacent to the first doped region I, and the second end 1202 is in contact with the semiconductor channel 100 of the channel region II adjacent to the second doped region III. That is, in the first direction X, there is the semiconductor channel 100 of the channel region II between the gate structure 120 and the semiconductor channel 100 of the first doped region I, and there is also the semiconductor channel 100 of the channel region II between the gate structure 120 and the semiconductor channel 100 of the second doped region III. It should be noted that in the first direction X, the thickness of the channel region II between the gate structure 120 and the first doped region I needs to be set within a certain range, and the thickness of the channel region II between the gate structure 120 and the second doped region III also needs to be set within a certain preset range. Thus, it is beneficial to ensure that the source and drain of the transistor form a conduction state by using the depletion layer formed by the gate structure 120 in the channel region II.

[0052] Reference Figures 1 to 5, in some embodiments, the first doped region I includes a first region 11 and a second region 12 arranged in sequence along the first direction X. Among them, the first region 11 is far from the channel region II, the second region 12 is adjacent to the channel region II, and the semiconductor channel 100 of the first region 11 includes a first metal-semiconductor compound layer 150 in contact with the bit line structure 110; the first support layer 130 penetrates through the first metal-semiconductor compound layer 150 of the first region 11. Among them, the material of the first metal-semiconductor compound layer 150 is a metal-semiconductor compound. The first metal-semiconductor compound layer 150 not only helps to reduce the contact resistance between the semiconductor channel 100 and the bit line structure 110, but also helps to reduce the on-resistance of the semiconductor channel 100 of the first doped region I, and thus helps to improve the electrical performance of the semiconductor structure. It can be understood that, in some other embodiments, the first support layer 130 can also penetrate through the semiconductor channel 100 of the second region 12, and the specific position of the first support layer 130 can be adjusted according to actual needs.

[0053] In some embodiments, along the second direction Y, the ratio of the width of the first support layer 130 to the width of the semiconductor channel 100 of the first doped region I is 1 / 3 to 2 / 3, for example, it can be 1 / 3, 2 / 5, 1 / 2 or 3 / 5. Making the ratio of the width of the first support layer 130 to the width of the semiconductor channel 100 of the first doped region I greater than 1 / 3 is beneficial to ensuring that the first support layer 130 has sufficient support strength; making the ratio of the width of the first support layer 130 to the width of the semiconductor channel 100 of the first doped region I less than 2 / 3 is beneficial to ensuring that the first metal-semiconductor compound layer 150 or the semiconductor channel 100 of the first doped region I has sufficient width, which is beneficial to reducing the on-resistance of the first metal-semiconductor compound layer or the semiconductor channel 100 of the first doped region I, and thus beneficial to improving the electrical performance of the semiconductor structure.

[0054] Reference Figures 1 to 4 , in some embodiments, on a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 100 of the first doped region I surrounding the first support layer 130 is annular. In this way, it is possible to avoid the first support layer 130 from contacting the bit line structure 110, ensure that one side of the bit line structure 110 facing the semiconductor channel 100 is in contact with the semiconductor channel 100, which is beneficial to ensuring that the semiconductor channel 100 and the bit line structure 110 have a large contact area, and thus beneficial to reducing the contact resistance between the bit line structure 110 and the semiconductor channel 100. It can be understood that, reference Figure 5, in some other embodiments, on a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 100 around the first doped region I of the first support layer 130 may also be U-shaped, that is, the side of the first support layer 130 away from the channel region II is also in contact with the bit line structure 110. In this way, in addition to providing support for the semiconductor channel 100 of the first doped region I, the first support layer 130 also provides support for the bit line structure 110, which is beneficial to ensuring the structural stability of the transistor structure while improving the structural stability of the bit line structure 110.

[0055] In some embodiments, referring to Figure 1 , the semiconductor structure further includes: a lower electrode layer 170, which is in contact connection with one end of the second doped region III away from the channel region II; a capacitive dielectric layer 180, which covers the surface of the lower electrode layer 170 not in contact with the semiconductor channel 100; and an upper electrode layer 190, which covers the surface of the capacitive dielectric layer 180 away from the lower electrode layer 170. The lower electrode layer 170, the capacitive dielectric layer 180, and the upper electrode layer 190 together form a capacitive structure. The material of the lower electrode layer 170 and the material of the upper electrode layer 190 may be conductive materials. In one example, the materials of the lower electrode layer 170 and the upper electrode layer 190 may both be titanium nitride. In some other examples, the materials of the lower electrode layer 170 and the upper electrode layer 190 may also be at least one of conductive materials such as platinum nickel, titanium, tantalum, cobalt, copper, tungsten, tantalum nitride, etc. The material of the capacitive dielectric layer 180 is an insulating material. For example, the material of the capacitive dielectric layer 180 may be at least one of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0056] In some embodiments, referring to Figures 1 to 5 , the second doped region III includes a third region 13 and a fourth region 14 arranged in sequence along the first direction X. Among them, the fourth region 14 is away from the channel region II, the third region 13 is adjacent to the channel region II, and the semiconductor channel 100 of the fourth region 14 includes a second metal semiconductor compound layer 160 in contact with the lower electrode layer 170; the second support layer 140 penetrates the second metal semiconductor compound layer 160 of the fourth region 14. Among them, the material of the second metal semiconductor compound layer 160 is a metal semiconductor compound, and the second metal semiconductor compound layer 160 and the lower electrode layer 170 form an ohmic contact, avoiding the formation of a Schottky barrier contact due to the direct contact between the lower electrode layer 170 and the semiconductor material. The ohmic contact is beneficial to reducing the contact resistance between the semiconductor channel 100 of the second doped region III and the lower electrode layer 170, thereby reducing the energy consumption during the operation of the semiconductor structure, being beneficial to improving the RC delay effect, and further being beneficial to improving the electrical performance of the semiconductor structure.

[0057] In some embodiments, along the second direction Y, the ratio of the width of the second support layer 140 to the width of the semiconductor channel 100 of the second doped region III is 1 / 3 to 2 / 3. For example, it can be 1 / 3, 2 / 5, 1 / 2, or 3 / 5. Making the ratio of the width of the second support layer 140 to the width of the semiconductor channel 100 of the second doped region III greater than 1 / 3 is beneficial to ensuring that the second support layer 140 has sufficient support strength; making the ratio of the width of the second support layer 140 to the width of the semiconductor channel 100 of the second doped region III less than 2 / 3 is beneficial to ensuring that the second metal-semiconductor compound layer or the semiconductor channel 100 of the second doped region III has sufficient width, which is beneficial to reducing the on-resistance of the second metal-semiconductor compound layer or the semiconductor channel 100 of the second doped region III, and thus is beneficial to improving the electrical performance of the semiconductor structure.

[0058] In some embodiments, on a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 100 of the second doped region III surrounding the second support layer 140 is annular. In this way, it is possible to avoid the second support layer 140 from contacting the lower electrode layer 170, ensure that one side of the lower electrode layer 170 facing the semiconductor channel 100 is in contact with the semiconductor channel 100, which is beneficial to ensuring that the semiconductor channel 100 and the lower electrode layer 170 have a large contact area, and thus is beneficial to reducing the contact resistance between the lower electrode layer 170 and the semiconductor channel 100. It can be understood that, referring to Figure 5 , in some other embodiments, on a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 100 of the second doped region III surrounding the second support layer 140 can also be U-shaped, that is, the side of the second support layer 140 away from the channel region II is also in contact with the lower electrode layer 170. In this way, in addition to providing support for the semiconductor channel 100 of the second doped region III, the second support layer 140 also provides support for the capacitor structure, which is beneficial to improving the structural stability of the capacitor structure while ensuring the structural stability of the transistor structure.

[0059] In the semiconductor structure provided by the above embodiments, the gate structure 120 extending along the third direction Z penetrates the semiconductor channel 100 of the channel region II, and the morphology of the gate structure 120 is restricted by the semiconductor channel 100 of the channel region II, so as to control the performance of the transistor. The first support layer 130 penetrates the semiconductor channel 100 of the first doped region I along the third direction Z, and the second support layer 140 penetrates the semiconductor channel 100 of the second doped region III along the third direction Z, so that the semiconductor channels 100 arranged in the third direction Z have better structural stability under the support of the first support layer 130 and the second support layer 140, thereby improving the structural stability of the semiconductor structure.

[0060] Another aspect of the embodiments of the present disclosure further provides a method for forming a semiconductor structure. The method for forming the semiconductor structure is used to form the semiconductor structure in the above embodiments. The method for forming the semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated below.

[0061] Figures 6 to 35 Schematic diagrams of the steps of a method for forming a semiconductor structure provided by the embodiments of the present disclosure.

[0062] Referring to Figures 6 to 35 , the method for forming the semiconductor structure includes: forming a semiconductor channel extending along a first direction X, and the semiconductor channel includes a first doped region I, a channel region II, and a second doped region III arranged in sequence along the first direction X. Among them, the semiconductor channels of the first doped region I and the second doped region III are respectively used as the source and drain of the transistor, and the semiconductor channel of the channel region II is used as the channel of the transistor.

[0063] In some embodiments, the specific steps of forming the semiconductor channel may include: providing a substrate (not shown); referring to Figures 6 to 7 , forming a first stacked structure 310 on the substrate, which is arranged at intervals along a second direction Y and extends along the first direction X. In the third direction Z, the first stacked structure 310 includes semiconductor layers 301 arranged at intervals and a first isolation layer 303 between the semiconductor layers 301. The first stacked structure 310 includes a first part 21, a second part 22, and a third part 23 arranged in sequence along the first direction X. Among them, the first isolation layer 303 is used to support and isolate the semiconductor layers 301 arranged in the third direction Z. The material of the first isolation layer 303 may be an insulating material, for example, silicon oxide.

[0064] In some embodiments, the method for forming the first stacked structure 310 may include: forming the Figure 6 shown stacked structure 200 on the substrate. In the third direction Z, the stacked structure 200 includes initial semiconductor layers 201 arranged at intervals and an isolation layer 202 between the initial semiconductor layers 201. Among them, the material of the isolation layer 202 may be the material of the first isolation layer 303 to be formed later; performing a patterning process on the stacked structure 200 to form the Figure 7 shown first stacked structure 310.

[0065] In some embodiments, the method of forming the first stacked structure 310 may also include: forming a stacked structure on a substrate, in a third direction, the stacked structure includes spaced-apart initial semiconductor layers and isolation layers between the initial semiconductor layers, wherein the material of the isolation layer may be a material that is relatively easy to form on a semiconductor material by epitaxy, for example, silicon germanide, thus facilitating the reduction of the difficulty in forming the first stacked structure; patterning the stacked structure to form Figure 8 the initial first stacked structure 300 as shown, in the third direction Z, the initial first stacked structure 300 includes semiconductor layers 301 and initial first isolation layers 302 between the semiconductor layers 301; referring to Figure 9 , forming a mask layer 220, the mask layer 220 covers the initial first stacked structure 300 and fills the regions between adjacent initial first stacked structures 300; referring to Figure 10 , patterning the initial first stacked structure 300 to form first through holes 221, second through holes 222, and third through holes 223 that penetrate the initial first stacked structure 300 in the third direction Z. It should be noted that the first through holes 221, second through holes 222, and third through holes 223 are used to form subsequent initial first openings, initial second openings, and initial third openings; referring to Figure 11 , forming a support layer 230 in the first through holes 221, second through holes 222, and third through holes 223, the support layer 230 is used to support the semiconductor layers 301 after removing the initial first isolation layer 302; referring to Figure 12 , removing the initial first isolation layer 302. It should be noted that since the material of the initial first isolation layer 302 is close to the material of the semiconductor layer 301, in order to prevent the initial first isolation layer 302 from affecting the subsequent formation method, therefore, other insulating materials need to be used to replace the initial first isolation layer 302 as the first isolation layer; referring to Figure 13 , forming a first isolation layer 303 in the voids formed after removing the initial first isolation layer 302, the first isolation layer 303 and the semiconductor layers 301 together constitute the first stacked structure 310.

[0066] It should be noted that for Figures 9 to 13 the formation method of the first stacked structure 310 as shown, while forming the first isolation layer 303 between adjacent semiconductor layers 301, a first isolation layer 303 is also formed between adjacent first stacked structures 310. The first isolation layer 303 located between adjacent first stacked structures 310 is beneficial to prevent materials formed by subsequent deposition and other methods from entering between adjacent first stacked structures 310 and increasing the difficulty of forming the semiconductor structure. Similarly, for Figures 6 to 7The method for forming the first stacked structure 310 shown further includes: forming a first isolation layer 303 between adjacent first stacked structures 310.

[0067] For Figures 6 to 7 the method for forming the first stacked structure 310 shown, forming a semiconductor channel further includes: referring to Figure 13 , patterning the first stacked structure 310 to form an initial first opening 241 penetrating the first part 21 along the third direction Z, an initial second opening 242 penetrating the second part 22 along the third direction Z, and an initial third opening 243 penetrating the third part 23 along the third direction Z, and forming a semiconductor channel based on the remaining semiconductor layer 301. Among them, the initial first opening 241, the initial second opening 242, and the initial third opening 243 respectively define the morphology of the semiconductor channel in the first doped region, the morphology of the semiconductor channel in the channel region, and the morphology of the semiconductor channel in the second doped region, and further respectively define the morphology of the subsequent formed first support layer, the morphology of the gate structure, and the morphology of the second support layer. Therefore, by controlling the morphology of the initial second opening 242, the morphology of the gate structure can be controlled, which is beneficial to forming a gate structure with a uniformly controllable morphology, and further beneficial to improving the performance of the semiconductor structure.

[0068] Referring to Figure 13 , after forming the initial first opening 241, the initial second opening 242, and the initial third opening 243, it further includes forming a support layer 230 in the initial first opening 241, the initial second opening 242, and the initial third opening 243. The support layer 230 is beneficial to realizing selective processing of the initial first opening 241, the initial second opening 242, or the initial third opening 243. For example, the support layer 230 in the initial second opening 242 can be removed only, and a processing step can be performed on the initial second opening 242. Or, the support layer 230 in the initial first opening 241 and the initial third opening 243 can be removed, and a processing step can be performed on the initial first opening 241 and the initial third opening 243 simultaneously. It can be understood that for Figures 9 to 13 the forming method shown, the support layer 230 has been formed before forming the first isolation layer 303. After forming the first isolation layer 303, the initial first opening 241, the initial second opening 242, and the initial third opening 243 filled with the isolation layer 202 shown in Figure 13 can be obtained.

[0069] In some embodiments, forming a semiconductor channel based on the remaining semiconductor layer 301 includes: referring to Figure 14 , removing the support layer 230 in the initial second opening 242, and forming an epitaxial layer 304 on the sidewalls of the semiconductor layer 301 exposed in the initial second opening 242. Specifically, referring to Figures 15 to 17 , it should be noted that referring toFigures 15 to 17 On the plane perpendicular to the first direction X Figure 14 is a schematic cross-sectional structure diagram at the A-A1 marked in Figure 15 is a cross-sectional view without removing the support layer 230 in the initial second opening 242. Refer to Figures 15 to 16 , remove the support layer 230 in the initial second opening 242, refer to Figure 17 , an epitaxial layer 304 is formed on the sidewall of the semiconductor layer 301 exposed in the initial second opening 242 through selective epitaxy process, and the epitaxial layer 304 encloses the second opening 252. The epitaxial layer 304 is used as the semiconductor channel of the channel region. Wherein, the material of the epitaxial layer 304 can be a semiconductor material with a higher carrier mobility, for example, silicon germanide. By forming the semiconductor channel of the channel region through the selective epitaxy process using the initial second opening 242, it is not only beneficial to form a channel region with a different material from the doping region, but also beneficial to reduce the formation difficulty of the channel region, and use the initial second opening 242 to control the morphology of the channel region, thereby being beneficial to improving the performance of the semiconductor structure.

[0070] It should be noted that, in some embodiments, refer to Figure 26 , on the plane perpendicular to the third direction Z, the cross-sectional shape of the epitaxial layer 304 is annular, that is, the semiconductor channel of the channel region constitutes a four-sided gate-all-around structure. In other embodiments, the semiconductor layer exposed by the initial second opening is in a state of surrounding the initial second opening on three sides. Therefore, refer to Figure 27 , on the plane perpendicular to the third direction Z, the cross-sectional shape of the epitaxial layer 304 formed using the sidewall of the semiconductor layer exposed by the initial second opening is U-shaped, that is, the semiconductor channel of the channel region constitutes a three-sided gate-all-around structure.

[0071] Refer to Figure 1 and Figures 18 to 20 , a gate structure 120 extending along the third direction Z is formed, and the gate structure 120 penetrates through the semiconductor channel of the channel region II along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect pairwise. In some embodiments, forming the gate structure 120 includes: refer to Figure 18 , a gate dielectric layer 121 is formed on the surface of the semiconductor channel of the channel region exposed by the initial second opening surrounded by the second opening 252 and the first isolation layer 303, that is, a gate dielectric layer 121 is formed on the surface of the epitaxial layer 304 exposed by the initial second opening surrounded by the second opening 252 and the first isolation layer 303; refer to Figure 19, within the second opening 252 outside the gate dielectric layer 121 and within the initial second opening 242 surrounded by the first isolation layer 303 outside the gate dielectric layer 121, a gate conductive layer 122 is filled. The gate conductive layer 122 and the gate dielectric layer 121 constitute the gate structure 120. Thus, by using the initial second opening 242 and the second opening 252, the morphology of the formed gate structure 120 can be controlled, which is beneficial to reducing the difficulty of forming the gate structure 120 with controllable morphology.

[0072] In some embodiments, the steps of forming the semiconductor channel of the channel region and the gate structure may also be as follows: after removing the support layer within the initial second opening, the semiconductor layer surrounding the initial second opening is directly used as the semiconductor channel of the channel region. Forming the gate structure includes: forming a gate dielectric layer on the semiconductor layer exposed by the initial second opening. After forming the gate dielectric layer, a gate conductive layer is formed within the remaining initial second opening. The gate conductive layer and the gate dielectric layer constitute the gate structure. Thus, by using the second initial opening, the morphology of the formed gate structure can be controlled, which is beneficial to reducing the difficulty of forming the gate structure with controllable morphology.

[0073] In some embodiments, referring to Figure 16 , along the second direction Y, the ratio of the width of the initial second opening 242 to the width of the semiconductor layer 301 is 2 / 5 to 4 / 5, and for example, it can be 2 / 5, 1 / 2, or 3 / 5. Making the ratio of the width of the initial second opening 242 to the width of the semiconductor layer 301 greater than 2 / 5 is beneficial to forming the gate structure by deposition within the initial second opening 242, reducing the difficulty of forming the gate structure, and ensuring that the gate structure has a good supporting effect on the semiconductor channel. Making the ratio of the width of the initial second opening 242 to the width of the semiconductor layer 301 less than 4 / 5 is beneficial to ensuring that a sufficient thickness of the semiconductor layer 301 is retained, preventing the semiconductor layer 301 from breaking due to stress during the growth of the epitaxial layer.

[0074] In some embodiments, referring to Figures 21 to 26 , it should be noted that Figures 21 to 23 and Figure 25 is a schematic cross-sectional structure diagram at the B - B1 position marked in Figure 20 on the plane perpendicular to the first direction X. Forming the semiconductor channel based on the remaining semiconductor layer 301 includes: referring to Figures 21 to 22 , removing the support layer 230 within the initial first opening 241; referring to Figures 23 to 26 , forming a first metal-semiconductor compound layer 150 based on the sidewalls of the semiconductor layer 301 exposed by the initial first opening 241. Specifically, referring to Figure 23 and Figure 24, a metal layer 250 can be formed within the initial first opening 241, and a metal-semiconductor compound can be formed as the first metal-semiconductor compound layer 150 on the sidewalls of the semiconductor layer 301 exposed within the initial first opening 241 through an annealing process. In this way, the metal-semiconductor compound used to reduce the conduction resistance between the first doped region and the bit line structure can be formed by utilizing the initial first opening 241. While enhancing the performance of the semiconductor structure, it is conducive to reducing the difficulty of forming the metal-semiconductor compound.

[0075] Reference Figure 25 and Figure 26 , the remaining metal layer 250 is removed, and the first metal-semiconductor compound layer 150 encloses the first opening 251. The semiconductor layer 301 between the first metal-semiconductor compound layer 150 and the first metal-semiconductor compound layer 150 and the channel region serves as the first doped region.

[0076] After forming the first metal-semiconductor compound layer, it further includes: forming a first support layer extending along the third direction, and the first support layer penetrates the semiconductor channel of the first doped region along the third direction. Reference Figures 25 to 28 , in some embodiments, forming the first support layer 130 includes: filling a support material within the first opening 251 and within the initial first opening 241 enclosed by the first isolation layer 303 to form the first support layer 130. In this way, the first support layer 130 used to provide support for the first doped region can be formed by utilizing the initial first opening 241 and the first opening 251. While improving the stability of the semiconductor structure, it is conducive to reducing the difficulty of forming the first support layer 130.

[0077] In some embodiments, the steps of forming the semiconductor channel of the first doped region and forming the first support layer can also be as follows: after removing the support layer within the initial first opening, the semiconductor layer surrounding the initial first opening can be directly used as the semiconductor channel of the first doped region, and a support material is filled within the initial first opening to form the first support layer. In this way, the first support layer used to provide support for the first doped region can be formed by utilizing the initial first opening. While improving the stability of the semiconductor structure, it is conducive to reducing the difficulty of forming the first support layer.

[0078] The method of forming the semiconductor channel of the second doped region is similar to the method of forming the semiconductor channel of the first doped region. In some embodiments, forming the semiconductor channel of the second doped region may include: while removing the support layer within the initial first opening, also removing the support layer within the initial third opening to expose the semiconductor layer, and forming a second metal-semiconductor compound layer based on the sidewalls of the semiconductor layer exposed by the initial third opening. Specifically, reference Figure 24 , a metal layer 250 can be formed within the initial first opening while a metal layer 250 is formed within the initial third opening; reference Figure 26, a metal-semiconductor compound is formed as the second metal-semiconductor compound layer 160 on the sidewalls of the semiconductor layer exposed through the annealing process in the initial third opening. In this way, the metal-semiconductor compound for reducing the on-resistance of the second doped region can be formed by using the initial third opening, which improves the performance of the semiconductor structure and is conducive to reducing the difficulty of forming the metal-semiconductor compound.

[0079] After forming the second metal-semiconductor compound layer, it further includes: removing the remaining metal layer in the initial third opening, referring to Figure 26 , the second metal-semiconductor compound layer 160 encloses the third opening 253, and the semiconductor layer 301 between the second metal-semiconductor compound layer 160, the second metal-semiconductor compound layer 160 and the channel region II serves as the second doped region III.

[0080] Referring to Figures 29 to 30 , a second support layer 140 extending along the third direction Z is formed, and the second support layer 140 penetrates the semiconductor channel of the second doped region along the third direction Z. In some embodiments, forming the second support layer includes: filling a support material in the third opening and the initial third opening surrounded by the first isolation layer to form the second support layer. In this way, the second support layer 140 for providing support to the second doped region can be formed by using the initial third opening and the third opening, which improves the stability of the semiconductor structure and is conducive to reducing the difficulty of forming the second support layer 140.

[0081] In some embodiments, the semiconductor layer surrounding the initial third opening can also be directly used as the semiconductor channel of the second doped region, and forming the second support layer includes: filling a support material in the initial third opening to form the second support layer. In this way, the second support layer for providing support to the second doped region can be formed by using the initial third opening, which improves the stability of the semiconductor structure and is conducive to reducing the difficulty of forming the second support layer.

[0082] In some embodiments, referring to Figure 31 , the method for forming the semiconductor structure further includes: removing the semiconductor layer 301 on the sidewalls of the epitaxial layer 304 extending along the first direction X, and using the epitaxial layer 304 as the semiconductor channel of the channel region II.

[0083] The method for forming the semiconductor structure further includes: referring to Figure 1 and Figures 32 to 33 , a bit line structure 110 extending along the second direction Y is formed, wherein the bit line structure 110 is in contact connection with one end of the first doped region I far from the channel region II. In some embodiments, forming the bit line structure 110 includes: referring to Figure 7, while forming the first stacked structure 310, a second stacked structure 400 extending along the second direction Y is formed on the substrate. The second stacked structure 400 is in contact with a side away from the second part 22 and towards the first part 21. Along the third direction Z, the second stacked structure 400 includes sacrificial layers 401 arranged at intervals and second isolation layers 402 between the sacrificial layers 401. The sacrificial layer 401 is in contact with the semiconductor layer 301 of the first part 21, and the second isolation layer 402 is in contact with the first isolation layer 303 of the first part 21; reference Figures 32 to 33 , the sacrificial layers 401 are removed; a bit line structure 110 is formed between adjacent second isolation layers 402.

[0084] In some embodiments, the method for forming a semiconductor structure further includes: forming a lower electrode layer in contact connection with one end of a semiconductor channel of a second doped region away from the channel region; forming a capacitive dielectric layer covering a surface of the lower electrode layer not in contact with the semiconductor channel; forming an upper electrode layer covering a surface of the capacitive dielectric layer away from the lower electrode layer. Specifically, reference Figure 7 , the first stacked structure 310 further includes a fourth part 24. The fourth part 24 and the second part 22 are located on opposite sides of the third part 23 along the first direction X, reference Figure 34 , the first isolation layer of the fourth part is removed to expose the semiconductor layer 301 of the fourth part, reference Figure 35 , a lower electrode layer, a capacitive dielectric layer, and an upper electrode layer 190 are sequentially formed on the semiconductor layer of the fourth part.

[0085] In the method for forming a semiconductor structure provided in the above embodiments, the topography of the gate structure is restricted by the semiconductor channel in the channel region, and the gate structure provides support for the semiconductor channel, improving the structural stability of the semiconductor structure. In addition, by forming a first support layer penetrating the semiconductor channel of the first doped region along the third direction and a second support layer penetrating the semiconductor channel of the second doped region along the third direction, the first support layer and the second support layer provide support for the semiconductor channels arranged in the third direction, thereby improving the structural stability of the semiconductor structure. Additionally, the topography of the formed gate structure is controlled by using the initial second opening, enhancing the performance of the semiconductor structure. A metal-semiconductor compound for reducing the on-resistance of the first doped region is formed by using the initial first opening, and a metal-semiconductor compound for reducing the on-resistance of the second doped region is formed by using the initial third opening. While enhancing the performance of the semiconductor structure, it is beneficial to reduce the difficulty of forming the metal-semiconductor compound. Moreover, by using the initial first opening and the first opening to form a first support layer for providing support to the first doped region, it is beneficial to reduce the difficulty of forming the first support layer. By using the initial third opening and the third opening to form a second support layer for providing support to the second doped region, it is beneficial to reduce the difficulty of forming the second support layer.

[0086] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, it includes: a semiconductor channel extending in a first direction, and the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence along the first direction; a bit line structure extending in a second direction, and the bit line structure is in contact connection with one end of the first doped region away from the channel region; a gate structure extending in a third direction, and the gate structure penetrates the semiconductor channel of the channel region along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; a first support layer extending in the third direction, and the first support layer penetrates the semiconductor channel of the first doped region along the third direction; a second support layer extending in the third direction, and the second support layer penetrates the semiconductor channel of the second doped region along the third direction.

2. The semiconductor structure according to claim 1, characterized in that, a part of the gate structure surrounded by the semiconductor channel has opposite first and second ends in the first direction, the first end is in contact with the semiconductor channel of the first doped region, and the second end is in contact with the semiconductor channel of the second doped region.

3. The semiconductor structure according to claim 1, characterized in that, a part of the gate structure surrounded by the semiconductor channel has opposite first and second ends in the first direction, the first end is in contact with the semiconductor channel of the channel region adjacent to the first doped region, and the second end is in contact with the semiconductor channel of the channel region adjacent to the second doped region.

4. The semiconductor structure according to claim 1, characterized in that, the gate structure includes a gate dielectric layer and a gate conductive layer, the gate conductive layer extends in the third direction, and the gate conductive layer penetrates the semiconductor channel of the channel region along the third direction, and the gate dielectric layer is located between the gate conductive layer and the semiconductor channel.

5. The semiconductor structure according to claim 1, characterized in that, the first doped region includes a first region and a second region arranged in sequence along the first direction, wherein the first region is away from the channel region, the second region is adjacent to the channel region, and the semiconductor channel of the first region includes a first metal semiconductor compound layer in contact with the bit line structure; the first support layer penetrates the first metal semiconductor compound layer of the first region.

6. The semiconductor structure according to claim 1 or 5, characterized in that, on a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel of the first doped region surrounding the first support layer is annular.

7. The semiconductor structure according to claim 1 or 5, characterized in that, in the second direction, the ratio of the width of the first support layer to the width of the semiconductor channel of the first doped region is 1 / 3 to 2 / 3.

8. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further includes: A lower electrode layer, wherein the lower electrode layer is in contact connection with one end of the second doped region away from the channel region; A capacitive dielectric layer, wherein the capacitive dielectric layer covers the surface of the lower electrode layer that is not in contact with the semiconductor channel; An upper electrode layer, wherein the upper electrode layer covers the surface of the capacitive dielectric layer away from the lower electrode layer.

9. The semiconductor structure according to claim 8, wherein, the second doped region includes a third region and a fourth region arranged in sequence along the first direction, wherein the fourth region is away from the channel region, the third region is adjacent to the channel region, and the semiconductor channel of the fourth region includes a second metal-semiconductor compound layer in contact with the lower electrode layer; The second support layer penetrates through the second metal-semiconductor compound layer of the fourth region.

10. The semiconductor structure according to claim 1 or 9, wherein, On a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel of the second doped region surrounding the second support layer is annular.

11. The semiconductor structure according to claim 1 or 9, wherein, Along the second direction, the ratio of the width of the second support layer to the width of the semiconductor channel of the second doped region is 1 / 3 to 2 / 3.

12. The semiconductor structure according to claim 1, wherein, The material of the semiconductor channel of the first doped region includes silicon, and the material of the semiconductor channel of the second doped region includes silicon; The material of the semiconductor channel of the channel region includes silicon, or the material of the semiconductor channel of the channel region includes silicon germanide.

13. A method for forming a semiconductor structure, wherein, comprises: Forming a semiconductor channel extending along a first direction, and the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence along the first direction; Forming a bit line structure extending along a second direction, and the bit line structure is in contact connection with one end of the first doped region away from the channel region; Forming a gate structure extending along a third direction, and the gate structure penetrates through the semiconductor channel of the channel region along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; Forming a first support layer extending along the third direction, and the first support layer penetrates through the semiconductor channel of the first doped region along the third direction; Forming a second support layer extending along the third direction, and the second support layer penetrates through the semiconductor channel of the second doped region along the third direction.

14. The method for forming a semiconductor structure according to claim 13, wherein, The step of forming the semiconductor channel includes: Providing a substrate; Forming a first stacked structure on the substrate, the first stacked structure being arranged at intervals along the second direction and extending along the first direction. Along the third direction, the first stacked structure includes a semiconductor layer arranged at intervals and a first isolation layer between the semiconductor layers. The first stacked structure includes a first part, a second part, and a third part arranged in sequence along the first direction; Pattern the first stacked structure to form an initial first opening that penetrates the first portion in the third direction, an initial second opening that penetrates the second portion in the third direction, and an initial third opening that penetrates the third portion in the third direction; Form the semiconductor channel based on the remaining semiconductor layer.

15. The method for forming a semiconductor structure according to claim 14, wherein, forming the semiconductor channel based on the remaining semiconductor layer includes: Form an epitaxial layer on the sidewalls of the semiconductor layer exposed in the initial second opening, the epitaxial layer enclosing the second opening, and the epitaxial layer serves as the semiconductor channel of the channel region.

16. The method for forming a semiconductor structure according to claim 15, wherein, forming the semiconductor channel based on the remaining semiconductor layer includes: Form a first metal semiconductor compound layer on the sidewalls of the semiconductor layer exposed in the initial first opening, the first metal semiconductor compound layer enclosing the first opening, and the first metal semiconductor compound layer and the semiconductor layer between the first metal semiconductor compound layer and the channel region serve as the first doped region.

17. The method for forming a semiconductor structure according to claim 15, wherein, forming the semiconductor channel based on the remaining semiconductor layer includes: Form a second metal semiconductor compound layer on the sidewalls of the semiconductor layer exposed in the initial third opening, the second metal semiconductor compound layer enclosing the third opening, and the second metal semiconductor compound layer and the semiconductor layer between the second metal semiconductor compound layer and the channel region serve as the second doped region.

18. The method for forming a semiconductor structure according to claim 15, wherein, forming the gate structure includes: Form a gate dielectric layer on the surface of the semiconductor channel of the channel region exposed in the second opening and the initial second opening enclosed by the first isolation layer; Fill a gate conductive layer in the second opening outside the gate dielectric layer and in the initial second opening enclosed by the first isolation layer outside the gate dielectric layer, and the gate conductive layer and the gate dielectric layer constitute the gate structure.

19. The method for forming a semiconductor structure according to claim 16, wherein, forming the first support layer includes: filling a support material in the first opening and the initial first opening enclosed by the first isolation layer to form the first support layer.

20. The method for forming a semiconductor structure according to claim 17, wherein, forming the second support layer includes: filling a support material in the third opening and the initial third opening enclosed by the first isolation layer to form the second support layer.

21. The method for forming a semiconductor structure according to claim 14, wherein, In the second direction, the ratio of the width of the initial second opening to the width of the semiconductor layer is 2 / 5 to 4 / 5.

22. The method for forming a semiconductor structure according to claim 14, wherein, The forming method further includes: forming a second stacked structure extending along the second direction on the substrate, the second stacked structure being in contact with a side of the first portion away from the second portion, in the third direction, the second stacked structure includes sacrificial layers arranged at intervals and a second isolation layer between the sacrificial layers, the sacrificial layer being in contact with the semiconductor layer of the first portion, and the second isolation layer being in contact with the first isolation layer of the first portion; removing the sacrificial layer; forming the bit line structure between adjacent second isolation layers.

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