Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

A semiconductor memory device and a method of manufacturing a semiconductor memory device are provided. The semiconductor memory device includes a gate stack including a plurality of first interlayer insulation patterns and a plurality of conductive patterns alternately stacked, a dummy stack including a plurality of second interlayer insulation patterns and a plurality of sacrificial insulation layers, a plurality of stepped recesses defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap fill insulation pattern filling the plurality of stepped recesses, a second gap fill insulation pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap fill insulation pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap fill insulation pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device and a method for manufacturing the three-dimensional semiconductor memory device. Background Technology

[0002] A semiconductor memory device includes a memory cell array and peripheral circuitry connected to the memory cell array. The memory cell array includes multiple memory cells capable of storing data. The peripheral circuitry can provide various operating voltages to the memory cells and can control various operations of the memory cells. For this purpose, the peripheral circuitry can be electrically connected to the memory cell array. Additionally, lines for transmitting electrical signals from or to the peripheral circuitry can be connected to the peripheral circuitry. Summary of the Invention

[0003] According to embodiments of the present disclosure, a semiconductor memory device may include: a gate stack including a cell array region and a gate contact region, and including a plurality of alternating first interlayer insulating patterns and a plurality of conductive patterns; a dummy stack including a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers alternatingly stacked along a direction in which the plurality of first interlayer insulating patterns and the plurality of conductive patterns are alternately stacked; a plurality of stepped grooves spaced apart from each other in the gate contact region of the gate stack and defined at different depths in the gate stack; a plurality of openings passing through the dummy stack and spaced apart from each other; a first gap-filling insulating pattern filling the plurality of stepped grooves; a second gap-filling insulating pattern filling the plurality of openings; a plurality of conductive gate contacts passing through the first gap-filling insulating pattern and connected to the plurality of conductive patterns; and a plurality of conductive peripheral circuit contacts passing through the second gap-filling insulating pattern.

[0004] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include: forming a stack by alternately stacking a plurality of first material layers and a plurality of second material layers; forming a plurality of preliminary stepped grooves at a first depth in a gate contact region of the stack; forming a plurality of stepped grooves of different depths by etching a portion of the plurality of preliminary stepped grooves; and forming a plurality of spaced-apart openings in the peripheral circuit contact region of the stack by etching a peripheral circuit contact region of the stack while etching the plurality of preliminary stepped grooves. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0006] Figure 2This is a plan view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 3A , Figure 3B and Figure 3C yes Figure 2 The diagram shows a cross-sectional view of a semiconductor memory device.

[0008] Figure 4A and Figure 4B This is an example Figure 2 A perspective view of a portion of the semiconductor memory device shown.

[0009] Figure 5A and Figure 5B This is a cross-sectional view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 6 This is a cross-sectional view illustrating an embodiment of the contact structure between the doped semiconductor layer and the channel layer.

[0011] Figure 7A and Figure 7B This is a cross-sectional view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 8 This is a cross-sectional view illustrating an embodiment of the contact structure between the doped semiconductor layer and the channel layer.

[0013] Figure 9A , Figure 9B and Figure 9C This is a cross-sectional view illustrating the process of forming the unit plug.

[0014] Figure 10A , Figure 10B and Figure 10C This is a cross-sectional view illustrating the process of forming stepped sidewalls.

[0015] Figure 11A and Figure 11B This is a diagram illustrating the first stepped groove and a plurality of first preliminary stepped grooves.

[0016] Figure 12A and Figure 12B This diagram illustrates the process of forming a second stepped groove and multiple second preliminary stepped grooves.

[0017] Figure 13A and Figure 13B This is a diagram illustrating the vertical etching process.

[0018] Figure 14A and Figure 14BThe diagram illustrates the process of forming a gap-filling insulating layer, the process of forming a first slit, the process of forming a slit insulating layer, and the process of forming a second slit.

[0019] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B and Figure 16C This diagram illustrates the process of forming multiple conductive patterns.

[0020] Figure 17 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0021] Figure 18 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0023] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another, not to imply the number or order of elements.

[0024] Embodiments of this disclosure provide a semiconductor memory device that simplifies the manufacturing process and a method for manufacturing the semiconductor memory device.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The semiconductor memory device 50 may include a peripheral circuit structure 40 and a memory cell array 10.

[0027] The peripheral circuit structure 40 can be configured to perform programming operations for storing data in the memory cell array 10, reading operations for outputting data stored in the memory cell array 10, and erasing operations for erasing data stored in the memory cell array 10. As an embodiment, the peripheral circuit structure 40 may include an input / output circuit 21, a control circuit 23, a voltage generation circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0028] The memory cell array 10 may include multiple memory cells in which data is stored. The memory cells may be arranged in three dimensions. The memory cell array 10 may be connected to a drain select line DSL, multiple word lines WL, a source select line SSL, multiple bit lines BL, and a common source line CSL.

[0029] Input / output circuit 21 can send commands CMD and addresses ADD received from an external device (e.g., a memory controller) of semiconductor memory device 50 to control circuit 23. Input / output circuit 21 can exchange data DATA with external devices and column decoder 35.

[0030] Control circuit 23 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0031] The voltage generation circuit 31 can generate various operating voltages Vop for programming, reading and erasing operations in response to the operation signal OP_S.

[0032] The line decoder 33 can send the operating voltage Vop to the drain select line DSL, word line WL, and source select line SSL in response to the line address RADD.

[0033] The column decoder 35 can send data DATA input from the input / output circuit 21 to the page buffer 37 or send data DATA stored in the page buffer 37 to the input / output circuit 21 in response to the column address CADD. The column decoder 35 can exchange data DATA with the input / output circuit 21 via the column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 via the data line DL.

[0034] Page buffer 37 can temporarily store data DATA received via bit line BL in response to page buffer control signal PB_S. Page buffer 37 can sense the voltage or current of bit line BL during read operations.

[0035] The source line driver 39 can control the voltage applied to the common source line CSL in response to the source line control signal SL_S.

[0036] To improve the integration of semiconductor memory devices, in some embodiments, the memory cell array 10 may be configured to overlap with a portion of the peripheral circuit structure 40.

[0037] Figure 2 This is a plan view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0038] Reference Figure 2 The semiconductor memory device may include a memory cell array 10 and a dummy stack DMST. The memory cell array 10 may include a plurality of gate stacks GST, a plurality of channel structures CH through the plurality of gate stacks GST, and a memory layer 121 surrounding each channel structure CH.

[0039] Multiple gate stacks (GSTs) can be spaced apart from dummy stacks (DMSTs) via a first slit (SI1). The first slit (SI1) can be disposed between the multiple gate stacks (GSTs) and the dummy stacks (DMSTs).

[0040] A plurality of gate stacks (GSTs) may include a first gate stack (GST1) and a second gate stack (GST2) spaced apart from each other. A first slit (SI1) may extend in a direction intersecting the first gate stack (GST1) and the second gate stack (GST2). The first gate stack (GST1) may be spaced apart from the second gate stack (GST2) by a second slit (SI2). The second slit (SI2) may be disposed between the first gate stack (GST1) and the second gate stack (GST2) and may be connected to the first slit (SI1).

[0041] The first gate stack GST1 and the second gate stack GST2 can be structurally separated from each other and electrically separated from each other through the connection structure of the first slit SI and the second slit SI2. Each of the first gate stack GST1 and the second gate stack GST2 may include a plurality of first horizontal patterns. The plurality of first horizontal patterns may include, for example, Figure 3A and Figure 3B The diagram shows multiple conductive patterns 153 and multiple first interlayer insulating patterns 113A. Each first horizontal pattern may extend in a first direction D1 and a second direction D2, and the multiple first horizontal patterns may be stacked in a third direction D3. The first direction D1, the second direction D2, and the third direction D3 may be defined as the directions facing each other by axes that intersect each other. As an embodiment, the first direction D1, the second direction D2, and the third direction D3 may be defined as the directions facing the X-axis, Y-axis, and Z-axis of the XYZ coordinate system, respectively.

[0042] Each of the first gate stack GST1 and the second gate stack GST2 may include a cell array region CAR and a gate contact region GCTR extending from the cell array region CAR to the first slit SI1. Each channel structure CH may extend in the third direction D3 to pass through the cell array region CAR. The memory layer 121 may be disposed between its corresponding channel structure CH and its corresponding gate stack GST1 or GST2. A plurality of stepped grooves G1 to Gn (n is a natural number equal to or greater than 2) may be defined in the gate contact region GCTR.

[0043] Multiple stepped grooves G1 to Gn may be spaced apart from each other. Multiple stepped grooves G1 to Gn may provide contact areas for contacting multiple conductive gate contacts GCT. Multiple conductive gate contacts GCT may extend to different depths. Multiple stepped grooves G1 to Gn may be defined at different depths in their corresponding gate stacks GST1 or GST2. Multiple stepped grooves G1 to Gn may include a first stepped groove G1 located at the highest height in the third direction D3 and an nth stepped groove Gn located at the lowest height in the third direction D3. Embodiments of this disclosure are not limited thereto, and multiple stepped grooves G1 to Gn may also include at least one stepped groove deeper than the first stepped groove G1 and located at a height higher than the nth stepped groove Gn in the third direction, as well as a first stepped groove G1 and an nth stepped groove Gn. For example, the plurality of stepped grooves G1 to Gn may include not only the first stepped groove G1 and the nth stepped groove Gn, but also the second stepped groove G2 and the third stepped groove G3 disposed at different heights on the third direction D3. The second stepped groove G2 and the third stepped groove G3 may be located at a deeper depth than the first stepped groove G1, and may be disposed at a higher height on the third direction D3 than the nth stepped groove Gn.

[0044] Each of the second to nth stepped grooves G2 can be adjacent to a plurality of protruding stepped structures PSS, and can be formed to be deeper than the plurality of protruding stepped structures PSS. The plurality of protruding stepped structures PSS can be positioned at the same height as the first stepped groove G1 in the third direction D3. Each protruding stepped structure PSS can have the same cross-sectional structure as the first stepped groove G1. Among the plurality of first horizontal patterns, the first horizontal pattern overlapping the plurality of protruding stepped structures PSS in the third direction D3 is continuous without interruption from the cell array region CAR toward the first slit SI1. Therefore, the first stepped groove G1 and the plurality of protruding stepped structures PSS can be arranged in a row from the cell array region CAR toward the first slit SI1.

[0045] A dummy stack-up (DMST) can be disposed in the peripheral circuit contact region (PCTR) of a semiconductor memory device. The PCTR can be configured as an area for a plurality of conductive peripheral circuit contacts (PCTs) extending in a third direction D3. The plurality of conductive peripheral circuit contacts (PCTs) can be spaced apart from each other in a first direction D1 and a second direction D2. The plurality of conductive peripheral circuit contacts (PCTs) can connect signal transmission lines (e.g., Figure 5B The TL shown is electrically connected to Figure 1The peripheral circuit structure 40 shown. The signal transmission line can be used as at least one of a power line and a ground line, or it can be used as a line connected to the memory cell array 10.

[0046] A dummy stack (DMST) may include multiple second-level patterns. These multiple second-level patterns may include... Figure 3C The diagram shows multiple sacrificial insulating layers 111 and multiple second interlayer insulating patterns 113B. Each second horizontal pattern may extend in a first direction D1 and a second direction D2. The multiple second horizontal patterns may be stacked in a third direction D3.

[0047] Multiple conductive peripheral circuit contacts (PCTs) can be disposed within multiple openings (OPs) spaced apart from each other. The multiple openings (OPs) can pass through a dummy stack (DMST). The arrangement of the multiple openings (OPs) can be designed considering the arrangement of the multiple conductive peripheral circuit contacts (PCTs). For example, the multiple conductive peripheral circuit contacts (PCTs) can include two or more first peripheral circuit contacts (PCT1s) clustered in a portion of the peripheral circuit contact area (PCTR) and second peripheral circuit contacts (PCT2s) clustered in another region, the number of second peripheral circuit contacts (PCT2s) being less than the number of first peripheral circuit contacts (PCT1s). The multiple openings (OPs) can include first openings (OP1) and second openings (OP2). First peripheral circuit contacts (PCT1s) can be disposed within first openings (OP1), while second peripheral circuit contacts (PCT2s) can be disposed within second openings (OP2). The cross-sectional area of ​​the second opening (OP2) for having a relatively smaller number of second peripheral circuit contacts (PCT2s) than the number of first peripheral circuit contacts (PCT1s) can be defined as narrower than the cross-sectional area of ​​the first opening (OP1) for the first peripheral circuit contacts (PCT1s).

[0048] As described above, considering the arrangement of multiple conductive peripheral circuit contacts (PCTs), embodiments of this disclosure provide multiple openings (OPs) spaced apart from each other in a dummy stack (DMST). According to embodiments of this disclosure, considering the entire area where multiple conductive peripheral circuit contacts (PCTs) are provided, structural stability can be improved compared to the case where only one opening is provided inside the dummy stack (DMST). For example, the multiple openings (OPs) and the multiple stepped grooves (G1 to Gn) can be filled with a gap-filling insulating layer. In some embodiments, the surface flatness of the gap-filling insulating layer can be improved as the difference between the area of ​​each opening (OP) and the area of ​​each stepped groove (G1 to Gn) decreases. When the surface flatness of the gap-filling insulating layer is improved in some embodiments, the structural stability of the semiconductor memory device can be improved. According to embodiments of this disclosure, by controlling the area of ​​each opening (OP) considering the aggregation aspect of the multiple conductive peripheral circuit contacts (PCTs), the difference between the area of ​​each opening (OP) and the area of ​​each stepped groove (G1 to Gn) can be reduced.

[0049] Figure 3A , Figure 3B and Figure 3C yes Figure 2 The diagram shows a cross-sectional view of a semiconductor memory device. Figure 3A This is an example of along Figure 2 The cross-sectional view of the cell array region CAR of the gate stack GST, taken by line II′, is shown. Figure 3B This is an example of along Figure 2 The diagram shows a cross-sectional view of the gate contact region GCTR of the gate stack GST, taken by line II-II′. Figure 3C This is an example of along Figure 2 The diagram shows a cross-sectional view of the PCTR, the peripheral circuit contact area of ​​a semiconductor memory device, taken by line III-III′.

[0050] Reference Figure 3A and Figure 3B The gate stack GST may include a plurality of conductive patterns 153 and a plurality of first interlayer insulating patterns 113A alternately disposed on a third-direction D3. The plurality of conductive patterns 153 and the plurality of first interlayer insulating patterns 113A may be configured on a plurality of layers L1 to Lk (k is a natural number greater than n) stacked on the third-direction D3. Each of the plurality of layers L1 to Lk may include a pair of patterns, each pair including a conductive pattern 153 and a corresponding first interlayer insulating pattern 113A. The plurality of layers L1 to Lk may be stacked from the lowest first layer L1 to the highest [k]th layer Lk. The plurality of layers L1 to Lk may be configured... Figure 2 The stepped sidewalls SW of each of the multiple protruding stepped structures PSS and multiple stepped grooves G1 to Gn shown.

[0051] The gate stack (GST) can be penetrated by the channel structure (CH) and memory layer 121. The channel structure (CH) may include a channel layer 123. In one embodiment, the channel layer 123 may be formed in a tubular shape. In this case, the channel structure (CH) may also include a core insulating layer 125 filling the central region of the channel layer 123 and a capping pattern 127. The channel layer 123 and the capping pattern 127 may be formed of a semiconductor material such as silicon. The portion of the capping pattern 127 and the channel layer 123 in contact with the capping pattern 127 may be configured with a channel doped region including a conductive dopant. In one embodiment, the channel doped region may include an n-type impurity. The channel structure (CH) may protrude more than the gate stack (GST) on the third-direction D3.

[0052] Memory layer 121 may be disposed between gate stack GST and channel structure CH. Memory layer 121 may be formed of various data storage materials such as charge trapping layer, ferroelectric layer, phase change material layer, ferromagnetic material layer, and nanodots. As an embodiment, memory layer 121 may include a tunnel insulating layer between gate stack GST and channel structure CH, a data storage layer between tunnel insulating layer and gate stack GST, and a barrier insulating layer between data storage layer and gate stack GST. The data storage layer may be formed of silicon nitride for trapping charge, and the tunnel insulating layer may be formed of silicon oxide capable of charge tunneling. The barrier insulating layer may be formed of an insulating material for blocking charge. As an embodiment, the barrier insulating layer may include at least one of silicon oxide and metal oxide.

[0053] A first gap-fill insulating pattern 143A, which can be used as part of a gap-fill insulating layer 143, covers the gate stack GST. The first gap-fill insulating pattern 143A can fill... Figure 2 The diagram shows multiple stepped grooves G1 to Gn and multiple protruding stepped structures PSS. The first gap is filled with an insulating pattern 143A that can cover the upper end of the channel structure CH.

[0054] The second slit SI2 can extend in the third direction D3 to pass through the first gap and fill the insulating pattern 143A. The second slit SI2 can be filled with a vertical structure VP formed of various materials. As an embodiment, the vertical structure VP can be formed from the insulating material filling the second slit SI2.

[0055] Multiple conductive gate contacts (GCTs) can be set in Figure 2The plurality of stepped grooves G1 to Gn are shown inside. A plurality of conductive gate contacts GCT can contact a plurality of conductive patterns 153 respectively through the plurality of stepped grooves G1 to Gn. For this purpose, the plurality of conductive gate contacts GCT can pass through the first gap filling insulating pattern 143A and can pass through a plurality of first interlayer insulating patterns 113A respectively. For example, the first stepped groove G1 may include a bottom surface defined by the [k-4]th layer Lk-4 and stepped sidewalls SW defined by the [k-3]th layer Lk-3, the [k-2]th layer Lk-2, the [k-1]th layer Lk-1, and the [k]th layer Lk. As described above, the conductive pattern 153 of the [k-4]th layer Lk-4 overlapping the bottom surface of the first stepped groove G1, and the conductive patterns 153 of the [k-3]th layer Lk-3, the [k-2]th layer Lk-2, and the [k-1]th layer Lk-1 overlapping the stepped sidewalls SW of the first stepped groove G1, can contact their corresponding conductive gate contacts GCT. The conductive gate contacts GCT can extend in the third direction D3 to penetrate their corresponding first interlayer insulation pattern 113A and first gap-filling insulation pattern 143A.

[0056] Reference Figure 3C The dummy laminate DMST may include multiple sacrificial insulating layers 111 and multiple second interlayer insulating patterns 113B alternately disposed on a third-direction D3. The multiple sacrificial insulating layers 111 may be respectively disposed on... Figure 3A and Figure 3B The multiple conductive patterns 153 shown are at approximately the same height. Multiple second-layer interlayer insulating patterns 113B can be respectively set at the same height as... Figure 3A and Figure 3B The multiple first interlayer insulation patterns 113A shown are at substantially the same height. The multiple second interlayer insulation patterns 113B can be formed by... Figure 3A and Figure 3B The plurality of first interlayer insulating patterns 113A shown are formed of the same material. The plurality of sacrificial insulating layers 111 may be formed of a material having etch selectivity relative to the plurality of second interlayer insulating patterns 113B. As an embodiment, the plurality of second interlayer insulating patterns 113B may be formed of silicon oxide, and the plurality of sacrificial insulating layers 111 may be formed of silicon nitride.

[0057] Multiple sacrificial insulation layers 111 and multiple second interlayer insulation patterns 113B can be Figure 2 The multiple openings OP shown are continuous. Each opening OP can be filled with a second gap-filling insulating pattern 143B, which is another part of the gap-filling insulating layer 143. The second gap-filling insulating pattern 143B can be extended to cover the dummy laminate DMST.

[0058] Multiple conductive peripheral circuit contacts (PCTs) can be set in Figure 2 The multiple openings (OPs) shown are shown inside. Multiple conductive peripheral circuit contacts (PCTs) can pass through the second gap and fill the insulating pattern 143B. The conductive peripheral circuit contacts (PCTs) disposed in each opening (OP) and adjacent to each other can be insulated from each other by filling the second gap with the insulating pattern 143B.

[0059] Each opening OP can include flatness higher than Figure 3B The stepped sidewall SW shown is flattened by the sidewall OP_SW. As an embodiment, the opening OP may include a cylindrical sidewall.

[0060] Reference Figure 3A , Figure 3B and Figure 3C The semiconductor memory device may include an etch stop layer 101 and a gate-source insulating layer 103. A gate stack (GST) and a dummy stack (DMST) may overlap each of the etch stop layer 101 and the gate-source insulating layer 103. The gate-source insulating layer 103 may be disposed between each of the gate stack (GST) and the dummy stack (DMST) and the etch stop layer 101. The gate-source insulating layer 103 may be formed of the same material as the first interlayer insulating pattern 113A and the second interlayer insulating pattern 113B. The etch stop layer 101 may be formed of a material different from that of the gap-filling insulating layer 143 for selective etching of the gap-filling insulating layer 143. In other words, the gap-filling insulating layer 143 may have etch selectivity relative to the etch stop layer 101. As an embodiment, the gap-filling insulating layer 143 may be formed of silicon oxide, and the etch stop layer 101 may be formed of at least one of silicon nitride, silicon, and silicon carbide (e.g., SiCO and CN). When the gap-filling insulating layer 143 is etched, the etch stop layer 101 can be etch-resistant. Figures 3A to 3C The example shown is where the etch stop layer 101 is formed of an insulating material such as silicon nitride or silicon carbide.

[0061] The gate-source insulating layer 103 can be penetrated by the second slit SI2, the vertical structure VP, and the opening OP. The etch stop layer 101 can define the bottom surface of the opening OP, and the etch stop layer 101 may include a portion contacting the second gap-filling insulating pattern 143B. The etch stop layer 101 can be penetrated by a plurality of conductive contact plugs 100, each contacting a plurality of conductive peripheral circuit contacts PCT. The etch stop layer 101 can be penetrated by the channel structure CH and the memory layer 121. The second slit SI2 and the vertical structure VP can be formed to a depth penetrating the etch stop layer 101, or can be as follows: Figure 3A The diagram shows the bottom surface that is in contact with the etch stop layer 101.

[0062] Figure 4A and Figure 4B This is an example Figure 2 A perspective view of a portion of the semiconductor memory device shown. Figure 4A Examples include the gate contact region GCTR of a gate stack GST and a portion of a dummy stack DMST adjacent to the gate contact region GCTR. Figure 4B Another part of the dummy stack DMST is shown.

[0063] Reference Figure 4A and Figure 4B The gap-filling insulating layer 143 can be used to fill multiple stepped grooves G1 to Gn inside the gate stack GST and multiple openings OP inside the dummy stack DMST. The gap-filling insulating layer 143 can be divided into a first gap-filling insulating pattern 143A and a second gap-filling insulating pattern 143B by a first slit SI1. The first slit SI1 can be filled with a slit insulating layer 145.

[0064] The second slit SI2 and the vertical structure VP can extend along the gate stack GST. Multiple layers L1 to Lk of the gate stack GST can define multiple stepped grooves G1 to Gn with stepped sidewalls SW. The multiple stepped grooves G1 to Gn can be disposed at different depths. The first stepped groove G1 of the multiple stepped grooves G1 to Gn can be disposed at the highest height in the third direction D3. For example, the first stepped groove G1 can have a sidewall SW defined by layer [k-3] Lk-3, layer [k-2] Lk-2, layer [k-1] Lk-1, and layer [k] Lk. The nth stepped groove Gn can be disposed at the lowest height in the third direction D3. For example, the nth stepped groove Gn can have a stepped sidewall SW defined by layer L1, layer L2, layer L3, and layer L4.

[0065] Multiple conductive gate contacts GCT can overlap with the ends of multiple layers L1 to Lk configured with stepped sidewalls SW on a third direction D3, and can fill the insulating pattern 143A through the first gap.

[0066] Multiple conductive peripheral circuit contacts (PCTs) can pass through the second gap to fill the insulating pattern 143B.

[0067] Reference Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The described configuration may overlap with the external circuit structure. (See reference...) Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4BThe described gate stack (GST) can be disposed between the bit line and the peripheral circuit structure, or between the peripheral circuit structure and the doped semiconductor layer. The doped semiconductor layer can be connected to... Figure 1 The layer of the common source line controlled by the source line driver 39 shown.

[0068] Figure 5A and Figure 5B This is a cross-sectional view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure. Figure 5A and Figure 5B An embodiment of a semiconductor memory device including a gate stack GST disposed between a bit line BL and a peripheral circuit structure is illustrated. Figure 5A An example is shown of the cell array region CAR of the gate stack GST, while Figure 5B An example of the PCTR (Peripheral Circuit Contact Area) of a semiconductor memory device is shown. In the following text, details related to... Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The configuration shown is a repeated description of the same configuration.

[0069] Reference Figure 5A and Figure 5B , Figure 1 The peripheral circuit structure 40 shown may include a plurality of transistors TR. Each transistor TR may include a gate insulating layer 213, a gate electrode 215, and a junction 201J. The gate insulating layer 213 and the gate electrode 215 may be stacked on the active region of the semiconductor substrate 201. The active region of the semiconductor substrate 201 may be separated by an isolation layer 205 buried in the semiconductor substrate 201. The junction 201J may be defined as a region in the active region of the semiconductor substrate 201 located on both sides of the gate electrode 215, wherein at least one of an n-type impurity and a p-type impurity is implanted. The junction 201J may be configured as the source and drain regions of its corresponding transistor TR.

[0070] The semiconductor substrate 201 may include a region overlapping with the gate stack (GST) and the peripheral circuit contact region (PCTR). The PCTR of the semiconductor substrate 201 may overlap with a dummy stack (DMST). A plurality of transistors (TRs) may include transistors overlapping with the gate stack (GST) and transistors disposed within the PCTR. The plurality of transistors (TRs) may be connected to a plurality of interconnect ICs disposed on the semiconductor substrate 201. Each interconnect IC may include conductive patterns disposed on two or more layers and interconnected with each other.

[0071] The semiconductor substrate 201 and multiple transistors TR can be covered by the lower insulating structure 221. Multiple interconnect ICs can be embedded in the lower insulating structure 221. The lower insulating structure 221 may include two or more insulating layers.

[0072] A first doped semiconductor layer 231 may be disposed on the lower insulating structure 221, and a second doped semiconductor layer 233 may be disposed on the first doped semiconductor layer 231. Each of the first doped semiconductor layer 231 and the second doped semiconductor layer 233 may include at least one of n-type impurities and p-type impurities. In one embodiment, each of the first doped semiconductor layer 231 and the second doped semiconductor layer 233 may include an n-type impurity. The first doped semiconductor layer 231 and the second doped semiconductor layer 233 may be disposed between the gate stack GST and the lower insulating structure 221. The first doped semiconductor layer 231 and the second doped semiconductor layer 233 may be penetrated by the source insulating layer 241. The source insulating layer 241 may overlap with the peripheral circuit contact region PCTR of the semiconductor substrate 201.

[0073] Reference Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The described structure can be disposed on the second doped semiconductor layer 233 and the source insulating layer 241. For example, an etch stop layer 101' and a gate-source insulating layer 103 can be stacked on the second doped semiconductor layer 233. The etch stop layer 101' and the gate-source insulating layer 103 can extend to overlap with the source insulating layer 241. The gate stack GST and the dummy stack DMST can overlap with the plurality of transistors TR, and the etch stop layer 101' is interposed between the gate stack GST and the dummy stack DMST and the plurality of transistors TR. Figure 5A and Figure 5B An example is illustrated where the etch stop layer 101' is formed of a conductive material such as silicon. The etch stop layer 101' formed of a conductive material can be separated into multiple patterns by the insulating layer 243. As an embodiment, the etch stop layer 101' can be separated into a source pattern 101S overlapping with the gate stack GST, a dummy pattern 101D overlapping with the dummy stack DMST, and a contact pattern 101C overlapping with the conductive peripheral circuit contact PCT.

[0074] The source insulating layer 241, which overlaps with the peripheral circuit contact area PCTR of the semiconductor substrate 201, can be penetrated by a plurality of conductive contact plugs 100A. Each of the plurality of conductive contact plugs 100A can be connected to its corresponding interconnect IC. Each conductive contact plug 100A can be connected to its corresponding conductive peripheral circuit contact PCT via its corresponding contact pattern 101C.

[0075] The channel structure CH and memory layer 121 can pass through multiple conductive patterns 153 and multiple first interlayer insulating patterns 113A of the gate stack GST, and can pass through the source pattern 101S of the gate-source insulating layer 103 and the etch stop layer 101′.

[0076] The channel layer 123 and core insulating layer 125 of the channel structure CH can penetrate through the second doped semiconductor layer 233 and extend into the first doped semiconductor layer 231. The channel layer 123 of the channel structure CH can have sidewalls SS that contact the second doped semiconductor layer 233. The second doped semiconductor layer 233 can surround the sidewalls SS of the channel layer 123.

[0077] The memory layer 121 can be separated into a first memory pattern 121A and a second memory pattern 121B by the second doped semiconductor layer 233. The first memory pattern 121A can be defined as a portion of the memory layer 121 extending along the sidewalls of the gate stack GST, the sidewalls of the gate-source insulating layer 103, and the sidewalls of the source pattern 101S. The second memory pattern 121B can be defined as a portion of the memory layer 121 disposed between the channel structure CH and the first doped semiconductor layer 231.

[0078] The plurality of conductive patterns 153 of the gate stack GST can be used as the source select line SSL, the word line WL, and the drain select line DSL. As an implementation, the source select line SSL can be formed by the conductive pattern of the plurality of conductive patterns 153 closest to the first doped semiconductor layer 231, and the drain select line DSL can be formed by the conductive pattern of the plurality of conductive patterns 153 furthest from the first doped semiconductor layer 231. Each of the remaining conductive patterns of the plurality of conductive patterns 153 between the conductive pattern used as the source select line SSL and the conductive pattern used as the drain select line DSL can be used as the word line WL.

[0079] like Figure 4A As shown, the gate stack GST can be spaced apart from the dummy stack DMST through the first slit SI1. Figure 5A As shown, the second slit SI2 may include a gate-through portion SI2A and an extension portion SI2B. The gate-through portion SI2A may pass through the first gap-filling insulating pattern 143A, the gate stack GST, and the gate-source insulating layer 103. The extension portion SI2B may pass through the etch stop layer 101′.

[0080] The vertical structure VP may include a conductive vertical contact structure 159 and a spacer insulating layer 155 located between the conductive vertical contact structure 159 and the gate stack GST. The spacer insulating layer 155 may extend along the gate of the second slit SI2 through a portion of the sidewall of SI2A. The conductive vertical contact structure 159 may be insulated from a plurality of conductive patterns 153 by the spacer insulating layer 155. The conductive vertical contact structure 159 may extend along the extension direction of the spacer insulating layer 155 and may pass through the etch stop layer 101'. The conductive vertical contact structure 159 may contact the second doped semiconductor layer 233.

[0081] The second doped semiconductor layer 233 can be electrically connected to via the conductive vertical contact structure 159. Figure 1 The source line driver 39 of the peripheral circuit structure 40 shown.

[0082] The second gap-filling insulating pattern 143B can pass through the multiple sacrificial insulating layers 111 and multiple second interlayer insulating patterns 113B of the dummy stack DMST, and can also pass through the gate-source insulating layer 103. A portion of the second gap-filling insulating pattern 143B can contact the contact pattern 101C of the etch stop layer 101'.

[0083] Multiple conductive peripheral circuit contacts (PCTs) can be filled through the second gap using an insulating pattern 143B. Each conductive peripheral circuit contact (PCT) can be electrically connected to its corresponding conductive contact plug 100A via its corresponding contact pattern 101C. Alternatively, when the etch stop layer 101' is formed of an insulating material, the multiple conductive peripheral circuit contacts (PCTs) can contact the multiple conductive contact plugs 100A extending through the etch stop layer 101'.

[0084] The first gap-filling insulating pattern 143A and the second gap-filling insulating pattern 143B may be covered by a first insulating layer 181. The first insulating layer 181 may be penetrated by a plurality of conductive contacts 183A and 183B. The plurality of conductive contacts 183A may include a first contact 183A connected to the capping pattern 127 of the channel structure CH and a second contact 183B connected to the conductive peripheral circuit contact PCT.

[0085] The first insulating layer 181 may be covered by the second insulating layer 191. The second insulating layer 191 may be penetrated by the bit line BL and the signal transmission line TL. The bit line BL may be connected to the first contact 183A, and the signal transmission line TL may be connected to the second contact 183B. The bit line BL may be electrically connected to the channel structure CH via the first contact 183A. The signal transmission line TL may be electrically connected to the transistor TR of the peripheral circuit structure via the second contact 183B, the conductive peripheral circuit contact PCT, the conductive contact plug 100A, and the interconnect IC.

[0086] The structure of the doped semiconductor layer in contact with the channel layer 123 can be designed in various ways.

[0087] Figure 6 This is a cross-sectional view illustrating an embodiment of the contact structure between the doped semiconductor layer and the channel layer. In the following text, details related to... Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The configuration shown is a repeated description of the same configuration.

[0088] Reference Figure 6 The etch stop layer 101, the gate-source insulating layer 103, the conductive pattern 153, and the first interlayer insulating pattern 113A can be disposed on the doped semiconductor layer 233', as described above. Figure 5A As described. The doped semiconductor layer 233' may include conductive impurities. As an embodiment, the doped semiconductor layer 233' may include n-type impurities. The doped semiconductor layer 233' may be composed of... Figure 1 The source line driver 39 shown is controlled.

[0089] The memory layer 121, the channel layer 123, and the core insulating layer 125 can penetrate the etch stop layer 101. The channel layer 123 may include a bottom surface BTS in contact with the doped semiconductor layer 233'.

[0090] Figure 7A and Figure 7B This is a cross-sectional view illustrating a portion of a semiconductor memory device according to an embodiment of the present disclosure. Figure 7A and Figure 7B An embodiment of a semiconductor memory device including a bonding structure is illustrated. Figure 7A and Figure 7B An embodiment of a semiconductor memory device including a gate stack GST disposed between a peripheral circuit structure and a doped semiconductor layer 351 is illustrated. Figure 7A An example is shown of the cell array region CAR of the gate stack GST, while Figure 7B An example of the PCTR (Peripheral Circuit Contact Area) of a semiconductor memory device is shown. In the following text, details related to... Figure 2 , Figures 3A to 3C , Figure 4A , Figure 4B , Figure 5A and Figure 5B The configuration shown is a repeated description of the same configuration.

[0091] Reference Figure 7A and Figure 7B The peripheral circuit structure may include, as shown in the reference... Figure 5A and Figure 5BThe description includes multiple transistors TR. Additionally, as referenced... Figure 5A and Figure 5B As described, each transistor TR can be disposed in the active region of the semiconductor substrate 201 separated by the isolation layer 205. (See reference...) Figure 5A and Figure 5B As described, each transistor TR may include a gate insulating layer 213, a gate electrode 215, and a junction 201J.

[0092] Multiple interconnect ICs connected to multiple transistors TR can be connected to multiple first conductive bonding pads 311. Multiple first conductive bonding pads 311 can be disposed on a lower insulating structure 221. The lower insulating structure 221 can be covered by a first bonding insulating layer 301. Multiple first conductive bonding pads 311 can extend through the first bonding insulating layer 301.

[0093] The first bonding insulating layer 301 may cover the second bonding insulating layer 303. The second bonding insulating layer 303 may be bonded to the first bonding insulating layer 301. Each of the first bonding insulating layer 301 and the second bonding insulating layer 303 may include silicon oxide, silicon oxynitride, silicon carbonitride, etc.

[0094] The second bonding insulating layer 303 may be penetrated by a plurality of second conductive bonding pads 313. The plurality of second conductive bonding pads 313 may be bonded to a plurality of first conductive bonding pads 311. The plurality of first conductive bonding pads 311 and the plurality of second conductive bonding pads 313 may comprise copper, copper alloys, or metals of the same type.

[0095] like Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The gate stack (GST) and dummy stack (DMST) shown can be disposed in a vertically inverted structure on the second conductive bonding pad 313 and the second bonding insulating layer 303. For example, the direction of the second bonding insulating layer 303 facing the semiconductor substrate 201 can be defined as... Figure 2 , Figures 3A to 3C , Figure 4A and Figure 4B The third party D3 is shown.

[0096] A first gap-filling insulating pattern 143A may be disposed between the second bonding insulating layer 303 and the gate stack GST. A second gap-filling insulating pattern 143B may be disposed between the second bonding insulating layer 303 and the dummy stack DMST. A first insulating layer 181 and a second insulating layer 191 may be disposed between the first gap-filling insulating pattern 143A and the second bonding insulating layer 303, and between the second gap-filling insulating pattern 143B and the second bonding insulating layer 303. The first insulating layer 181 may be penetrated by the first contact 183A and the second contact 183B, and the second insulating layer 191 may be penetrated by the bit line BL and the signal transmission line TL. Figure 5A and Figure 5B Compared to the same configuration shown, the first insulating layer 181, the second insulating layer 191, the first contact 183A, the second contact 183B, the bit line BL, and the signal transmission line TL can be arranged in a vertically inverted structure on the second bonding insulating layer 303.

[0097] The plurality of conductive patterns 153 of the gate stack GST can be used as the source select line SSL, the word line WL, and the drain select line DSL. As an implementation, the source select line SSL can be formed by the conductive pattern of the plurality of conductive patterns 153 furthest from the bit line BL, and the drain select line DSL can be formed by the conductive pattern closest to the bit line BL. Each of the remaining conductive patterns of the plurality of conductive patterns 153 between the conductive pattern used as the source select line SSL and the conductive pattern used as the drain select line DSL can be used as the word line WL.

[0098] The channel structure CH and memory layer 121 can pass through multiple conductive patterns 153 and multiple first interlayer insulating patterns 113A of the gate stack GST, and can also pass through the gate-source insulating layer 103 and the etch stop layer 101. The channel structure CH can have a tapered shape that narrows with increasing distance from the bit line BL. The second gap-fill insulating pattern 143B can pass through the gate-source insulating layer 103. The second gap-fill insulating pattern 143B can contact the surface of the etch stop layer 101 facing the second bonding insulating layer 303.

[0099] The vertical structure VP can be formed by a vertical insulating layer 157. The vertical insulating layer 157 can extend along the sidewalls of the gate stack GST and can pass through the gate-source insulating layer 103. In one embodiment, the vertical insulating layer 157 can contact the third-direction D3 surface of the etch stop layer 101. In another embodiment, the vertical insulating layer 157 can pass through the etch stop layer 101 and can contact the doped semiconductor layer 351. The vertical insulating layer 157 can have a tapered shape that narrows with increasing distance from the bit line BL.

[0100] The conductive peripheral circuit contact PCT can fill the insulating pattern 143B through the second gap. The conductive peripheral circuit contact PCT can have a tapered shape that narrows as the distance from the second conductive bonding pad 313 increases.

[0101] The etch stop layer 101 can be covered by the doped semiconductor layer 351 and the upper insulating layer 353.

[0102] The doped semiconductor layer 351 may contact the channel layer 123 of the channel structure CH. The channel layer 123 and the core insulating layer 125 of the channel structure CH may protrude further toward the doped semiconductor layer 351 than the memory layer 121. The channel layer 123 may extend along the surface of the core insulating layer 125 facing the doped semiconductor layer 351 to block contact between the core insulating layer 125 and the doped semiconductor layer 351. The doped semiconductor layer 351 may include conductive impurities. The doped semiconductor layer 351 may include at least one of n-type impurities and p-type impurities. As an embodiment, the doped semiconductor layer 351 may be divided into a layer including n-type impurities and a layer including p-type impurities.

[0103] The upper insulating layer 353 can be disposed at approximately the same height as the doped semiconductor layer 351. The upper insulating layer 353 can be penetrated by the conductive contact plug 100B. The conductive contact plug 100B can be connected to its corresponding conductive peripheral circuit contact PCT.

[0104] The processes for forming a first circuit structure including a first bonding insulating layer 301, a first conductive bonding pad 311, and a configuration disposed thereunder, and for forming a second circuit structure including a second bonding insulating layer 303, a second conductive bonding pad 313, and a configuration disposed thereon, can be performed separately. Therefore, in this embodiment, the degradation of the characteristics of the transistor TR in the first circuit structure due to heat generated during the formation of the second circuit structure can be mitigated.

[0105] After the first and second circuit structures are formed separately, a bonding process can be performed to bond the first bonding insulating layer 301 to the second bonding insulating layer 303 and the first conductive bonding pad 311 to the second conductive bonding pad 313, so as to electrically connect and structurally connect the memory cell array and the peripheral circuit structure. For example, the channel structure CH can be connected to its corresponding transistor TR via the cap pattern 127, the first contact 183A, the bit line BL, the second conductive bonding pad 313, the first conductive bonding pad 311, and the interconnect IC. In addition, the conductive contact plug 100B can be connected to its corresponding transistor TR via the conductive peripheral circuit contact PCT, the second contact 183B, the signal transmission line TL, the second conductive bonding pad 313, the first conductive bonding pad 311, and the interconnect IC.

[0106] The contact structure between the channel layer 123 and the doped semiconductor layer 351 is not limited to the above-described embodiments.

[0107] Figure 7A and Figure 7B An example is illustrated where the etch stop layer 101 is formed of an insulating material, but the embodiments disclosed herein are not limited thereto. As another embodiment, such as... Figure 5A and Figure 5B As shown, the semiconductor memory device may include an etch stop layer 101' formed of a conductive material.

[0108] Figure 8 This is a cross-sectional view illustrating an embodiment of the contact structure between the doped semiconductor layer and the channel layer. In the following text, [the following is omitted as it is not part of the original text]. Figure 7A The description shown is a duplicate of the same configuration.

[0109] Reference Figure 8 As mentioned above Figure 7A As described, the memory layer 121, channel layer 123, and core insulating layer 125 can pass through the conductive pattern 153 and the first interlayer insulating pattern 113A and can extend through the etch stop layer 101 and the gate-source insulating layer 103. Before forming the doped semiconductor layer 351 on the etch stop layer 101, the surfaces of the memory layer 121, channel layer 123, and core insulating layer 125 can be planarized. In this case, the core insulating layer 125 can have a surface in contact with the doped semiconductor layer 351. The channel layer 123 can contact the doped semiconductor layer 351 between the core insulating layer 125 and the memory layer 121.

[0110] In the following text, based on Figure 7A and Figure 7B The method of manufacturing a semiconductor memory device according to embodiments of the present disclosure is described as part of the manufacturing process of the semiconductor memory device shown.

[0111] Figure 9A , Figure 9B and Figure 9C This is a cross-sectional view illustrating the process of forming the unit plug.

[0112] Reference Figures 9A to 9C A gate-source insulating layer 103 can be formed on the etch stop layer 101. Although not shown in the figures, the etch stop layer 101 can be formed on the lower structure. The lower structure may include a sacrificial substrate. Embodiments of this disclosure are not limited thereto. For example, the lower structure may include... Figure 5A and Figure 5B The semiconductor substrate 201, multiple transistors TR, multiple interconnect ICs, lower insulating structure 221, first doped semiconductor layer 231 and source insulating layer 241 are shown.

[0113] After forming the gate-source insulating layer 103, a stack ST can be formed on the gate-source insulating layer 103. The stack ST may include a plurality of first material layers (e.g., 111) and a plurality of second material layers 113 alternately disposed on a third direction D3. (See reference...) Figure 3A and Figure 3B As described, the etch stop layer 101 can be formed of at least one of silicon nitride, silicon, and silicon carbide (e.g., SiCO and SiCN). In the following description, the case where the etch stop layer 101 is formed of an insulating material such as silicon nitride or silicon carbide is used as an example to illustrate subsequent processes.

[0114] The plurality of first material layers can be formed of a material having etch selectivity relative to the gate-source insulating layer 103 and the plurality of second material layers 113. The plurality of first material layers can be a reference. Figure 3C The sacrificial insulating layer 111 is described. For example, the gate-source insulating layer 103 and the plurality of second material layers 113 may comprise silicon oxide, and the plurality of first material layers configuring the plurality of sacrificial insulating layers 111 may comprise silicon nitride. Hereinafter, the plurality of first material layers are referred to as the plurality of sacrificial insulating layers 111.

[0115] The stacked structure ST may include a cell array region (CAR), a gate contact region (GCTR), and a peripheral circuit contact region (PCTR). The cell array region (CAR), the gate contact region (GCTR), and the peripheral circuit contact region (PCTR) may correspond to a reference. Figure 2 The cell array region CAR, gate contact region GCTR, and peripheral circuit contact region PCTR are described.

[0116] Multiple sacrificial insulating layers 111 and multiple second material layers 113 can be configured on multiple layers 110[1] to 110[k] (k is a natural number greater than 2) stacked on a third direction D3. Each of the multiple layers 110[1] to 110[k] may include a pair of layers, each pair of layers including a sacrificial insulating layer 111 and a corresponding second material layer 113. For example, layer 110[1] may include a sacrificial insulating layer 111 and a second material layer 113. The multiple layers 110[1] to 110[k] may be stacked from the first layer 110[1] disposed at the lowest layer toward the [k]th layer 110[k] disposed at the highest layer.

[0117] Subsequently, a first mask layer 401 can be formed on multiple layers 110[1] to 110[k]. The first mask layer 401 can be penetrated by multiple holes corresponding to multiple channel holes H. The cell array region CAR of the stack ST can be etched through the multiple holes defined in the first mask layer 401. Thus, multiple channel holes H can be defined. The multiple channel holes H can extend to penetrate the gate-source insulating layer 103 and the etch stop layer 101.

[0118] Subsequently, a memory layer 121 can be formed on the sidewall of each channel hole H. (See reference...) Figure 3A As described, memory layer 121 may include a barrier insulating layer, a data storage layer, and a tunnel insulating layer. Subsequently, the central region of the via H can be filled with a channel structure CH. As an embodiment, the step of forming the channel structure CH may include: forming a channel layer 123 on memory layer 121; filling a portion of the central region of the via H opened by channel layer 123 with a core insulating layer 125; and filling another portion of the central region of the via H with a capping pattern 127. Channel layer 123 may be formed of a semiconductor material such as silicon, and capping pattern 127 may be formed of a doped semiconductor material such as n-type doped silicon. Impurities within capping pattern 127 may diffuse into the portion of channel layer 123 that contacts capping pattern 127.

[0119] Figure 10A , Figure 10B and Figure 10C This is a cross-sectional view illustrating the process of forming the stepped sidewall SW.

[0120] Reference Figures 10A to 10C It can remove Figures 9A to 9C The first mask layer 401 is shown. At this time, a portion of the memory layer 121 can be removed. With the removal of the first mask layer 401, the end of the channel structure CH that protrudes more in the third direction D3 than the stack ST can be exposed.

[0121] Subsequently, a second mask layer 403 can be formed on the stack ST to cover the channel structure CH. The second mask layer 403 can be etched using a photolithography process to expose the gate contact region GCTR of the stack ST. Thereafter, the [k]th layer 110[k] of the multiple layers 110[1] to 110[k] of the stack ST can be etched using an etching process that uses the second mask layer 403 as an etch stop. Subsequently, by reducing the size of the second mask layer 403, the [k]th layer 110[k] and the [k-1]th layer 110[k-1] can be exposed. Thereafter, the exposed areas of the [k]th layer 110[k] and the [k-1]th layer 110[k-1] can be etched using an etching process that uses the reduced-size second mask layer 403 as an etch stop. The process of reducing the size of the second mask layer 403 and the etching process of the stack ST can be repeated before exposing the target layer. As an implementation, before exposing the [k-4]th layer 100[k-4] of the laminate ST, the process of reducing the size of the second mask layer 403 and the etching process of the laminate ST can be repeated. Therefore, a first stepped groove G1 with stepped sidewalls SW can be formed.

[0122] Figure 11A and Figure 11B The diagram illustrates the first stepped groove G1 and a plurality of first preliminary stepped grooves PG1.

[0123] After forming the first stepped groove G1 as the target, it is possible to remove, such as Figures 10A to 10C The second mask layer 403 is shown. While forming the first stepped groove G1, a plurality of first preliminary stepped grooves PG1 can be formed in the gate contact region GCTR of the laminate ST. The plurality of first preliminary stepped grooves PG1 can be formed at the same first depth as the first stepped groove G1. As an embodiment, each of the first stepped groove G1 and the plurality of first preliminary stepped grooves PG1 can have a bottom surface defined by the [k-4]th layer 110[k-4] and a stepped sidewall SW defined by the [k-3]th layer 110[k-3], the [k-2]th layer 110[k-2], the [k-1]th layer 110[k-1], and the [k]th layer 110[k]. The first stepped groove G1 and the plurality of first preliminary stepped grooves PG1 can be spaced apart from each other.

[0124] During the etching process used to form the first stepped groove G1 and multiple first preliminary stepped grooves PG1, the peripheral circuit contact area PCTR of the laminate ST can be... Figures 10A to 10C The second mask layer 403 shown provides protection.

[0125] Figure 12A and Figure 12B This is a diagram illustrating the process of forming the second stepped groove G2 and multiple second preliminary stepped grooves PG2.

[0126] Reference Figure 12A and Figure 12B After forming the third mask layer (not shown), etching can be performed using an etching process that uses the third mask layer as an etching barrier. Figure 11A The multiple frame regions B of the multiple first preliminary stepped grooves PG1 shown. Therefore, Figure 11A The multiple frame regions B of the plurality of first preliminary stepped grooves PG1 shown can be moved to a second depth greater than the first depth. Therefore, a plurality of second preliminary stepped grooves PG2 and second stepped grooves G2 having a second depth can be formed. As an embodiment, each of the second stepped groove G2 and the plurality of second preliminary stepped grooves PG2 can have a bottom surface defined by the [k-9]th layer 110[k-9] and stepped sidewalls defined by the [k-8]th layer 110[k-8], the [k-7]th layer 110[k-7], the [k-6]th layer 110[k-6], and the [k-5]th layer 110[k-5].

[0127] A portion of the multiple first preliminary stepped grooves PG1, protected by the third mask layer, can be retained as multiple protruding stepped structures PSS. During the etching process used to form the second stepped grooves G2 and the multiple second preliminary stepped grooves PG2, the peripheral circuit contact area PCTR of the laminate ST can be protected by the third mask layer. After forming the second stepped grooves G2 and the multiple second preliminary stepped grooves PG2, the third mask layer can be removed.

[0128] Subsequently, a vertical etching process can be performed to move the second preliminary stepped groove PG2 to a depth greater than the second depth. The second preliminary stepped groove PG2 can be moved to different target depths via the vertical etching process.

[0129] Figure 13A and Figure 13B This is a diagram illustrating the vertical etching process. Figure 13A and Figure 13B Examples are shown for forming Figure 2 The vertical etching process of the deepest nth stepped groove Gn among the multiple stepped grooves G1 to Gn shown.

[0130] Reference Figure 13A and Figure 13B By using a vertical etching process with a fourth mask layer (not shown) as an etching barrier, at least one of the second preliminary stepped grooves PG2 can be moved to the depth set by the first layer 110[1] located at the bottommost layer. Thus, the nth stepped groove Gn can be formed.

[0131] According to the above process, with Figure 11A At least one of the multiple box regions B shown is moved to the depth set by the first layer 110[1], which can define the nth step groove Gn.

[0132] During the vertical etching process used to form the nth stepped groove Gn, the peripheral circuit contact area PCTR of the stack ST can be etched, thereby defining multiple openings OP. A fourth mask layer can be formed to open a portion of the peripheral circuit contact area PCTR. The vertical etching process can be performed such that the first layer 110[1] is penetrated through the peripheral circuit contact area PCTR. In order to form multiple openings OP using the vertical etching process used to form the nth stepped groove Gn, a fourth mask layer can be defined to partially open the peripheral circuit contact area PCTR of the stack ST.

[0133] After forming the nth stepped groove Gn and multiple openings OP, the fourth mask layer can be removed. During the vertical etching process used to form the nth stepped groove Gn and multiple openings OP, etching can be performed. Figures 10A to 10C The gate-source insulating layer 103 is shown. Figures 10A to 10C The etch stop layer 101 shown may not be penetrated by the nth stepped groove Gn and the plurality of openings OP, but may be retained to define the bottom surface of each of the nth stepped groove Gn and the plurality of openings OP.

[0134] Figure 14A and Figure 14B The diagram illustrates the processes for forming the gap-filling insulating layer 143, forming the first slit SI1, forming the slit insulating layer 145, and forming the second slit SI2.

[0135] Reference Figure 14A and Figure 14B The gap can be filled with insulating layer 143. Figure 13A and Figure 13B The diagram shows multiple stepped grooves G1 to Gn and multiple openings OP. These can be covered by a gap-filling insulating layer 143. Figure 13A and Figure 13B The diagram shows several prominent stepped structures called PSS.

[0136] According to embodiments of this disclosure, such as Figure 13A and Figure 13B As shown, by setting multiple openings OP in the dummy laminate DMST to be spaced apart from each other, the surface flatness of the gap-filling insulating layer 143 can be improved, as referenced above. Figure 2 As described.

[0137] Subsequently, a first slit SI1 can be formed through the gap-filling insulating layer 143 and the stack ST. The first slit SI1 can pass through the stack ST between the stepped contact region GCTR and the peripheral circuit contact region PCTR. The gap-filling insulating layer 143 can be separated by the first slit SI1 into a first gap-filling insulating pattern 143A and a second gap-filling insulating pattern 143B. The first gap-filling insulating pattern 143A can overlap with the gate contact region GCTR of the stack ST, and the second gap-filling insulating pattern 143B can overlap with the peripheral circuit contact region PCTR of the stack ST. A plurality of second material layers can be separated by the first slit SI1 into... Figures 15A to 15C The diagram shows a plurality of first interlayer insulating patterns 113A and a plurality of second interlayer insulating patterns 113B. The plurality of first interlayer insulating patterns 113A can be disposed in the cell array region CAR and gate contact region GCTR of the laminate ST, while the plurality of second interlayer insulating patterns 113B can be disposed in the peripheral circuit contact region PCTR of the laminate ST.

[0138] Subsequently, the first slit SI1 can be filled with the slit insulation layer 145.

[0139] Subsequently, a second slit SI2 can be formed through the cell array region CAR of the laminate ST. The second slit SI2 can extend toward the slit insulating layer 145 and expose the sidewalls of the slit insulating layer 145. The second slit SI2 can be connected with... Figure 13A and Figure 13B The multiple protruding, stepped structures shown intersect in the PSS.

[0140] Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B and Figure 16C This is a diagram illustrating the process of forming multiple conductive patterns.

[0141] Reference Figures 15A to 15C You can refer to Figure 14A and Figure 14B The second slit SI2 removal described Figure 10A and Figure 10B The plurality of sacrificial insulating layers 111 are shown. At this time, the slit insulating layer 145 can protect the plurality of sacrificial insulating layers 111 formed in... Figure 14A and Figure 14B The portion of the peripheral circuit contact region PCTR of the stack ST is shown. Therefore, portions of the multiple sacrificial insulating layers 111 formed in the peripheral circuit contact region PCTR of the stack ST can be retained to form a dummy stack DMST. Another portion of the multiple sacrificial insulating layers 111 formed in the gate contact region GCTR and cell array region CAR of the stack ST can be removed. Therefore, multiple horizontal spaces 151 can be opened. The multiple horizontal spaces 151 can be defined between the first interlayer insulating patterns 113A adjacent along the third direction D3, and between the gate-source insulating layer 103 and the first interlayer insulating pattern 113A adjacent along the third direction D3.

[0142] Reference Figures 16A to 16C Multiple conductive patterns 153 can be used to fill the gaps. Figure 15A and Figure 15B The plurality of horizontal spaces 151 shown are thus formed. A gate stack GST can therefore be formed. According to embodiments of this disclosure, although a portion of the plurality of sacrificial insulating layers 111 is replaced by a plurality of conductive patterns 153 in the cell array region CAR and the gate contact region GCTR, a portion of the plurality of sacrificial insulating layers 111 can be retained in the peripheral circuit contact region PCTR to form a dummy stack DMST.

[0143] After forming multiple conductive patterns 153, the second slit SI2 can be filled with an insulating material. Therefore, a vertical structure VP including a vertical insulating layer 157 can be formed. The process for forming the vertical structure VP is not limited to this. For example, in order to form... Figure 5AThe vertical structure VP shown can perform the following processes.

[0144] Reference Figure 5A ,form Figure 5A The illustrated vertical structure VP may include: forming a spacer insulating layer 155 on the sidewall of the gate-through portion SI2A of the second slit SI2, forming an extension portion SI2B of the second slit SI2 through the etch stop layer 101', and forming a vertical contact structure 159. The vertical contact structure 159 may be formed to fill the extension portion SI2B of the second slit SI2 and extend along the surface of the spacer insulating layer 155. Before forming the conductive vertical contact structure 159, a second doped semiconductor layer 233 may be formed that contacts the channel layer 123 through the second slit SI2.

[0145] As described above, after forming the vertical structure VP according to the various embodiments, such as Figure 2 and Figure 3B As shown, multiple conductive gate contacts GCTs can be formed in multiple stepped grooves G1 to Gn. The multiple conductive gate contacts GCTs can fill the insulating pattern 143A through the first gap. Additionally, as... Figure 2 and Figure 3C As shown, multiple conductive peripheral circuit contacts (PCTs) can be formed in multiple open OPs. The multiple conductive peripheral circuit contacts (PCTs) can pass through the second gap to fill the insulating pattern 143B.

[0146] Multiple conductive gate contacts (GCTs) and multiple conductive peripheral circuit contacts (PCTs) can be formed using the same masking process. As an implementation, see [reference needed]. Figure 2 , Figure 3B and Figure 3C A mask layer (not shown) with multiple openings can be formed on the first gap-filling insulating pattern 143A and the second gap-filling insulating pattern 143B. Subsequently, multiple contact holes passing through the first gap-filling insulating pattern 143A and the second gap-filling insulating pattern 143B can be formed by etching the gap-filling insulating layer 143 in an etching process using the mask layer as an etching stop. The multiple contact holes may include multiple first contact holes disposed in the cell array region CAR and multiple second contact holes disposed in the peripheral circuit contact region PCTR. Each first contact hole can pass through its corresponding first interlayer insulating pattern 113A. Because the etch stop layer 101 is etch-resistant to the etch material of the gap-filling insulating layer 143, the etch stop layer 101 can be prevented from being penetrated by the second contact holes and can define the bottom surface of the second contact holes. Subsequently, conductive material can be formed in each of the multiple first contact holes and the multiple second contact holes, and the mask layer can be removed. Therefore, multiple conductive gate contacts GCT and multiple conductive peripheral circuit contacts PCT can be formed.

[0147] Figure 17 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0148] Reference Figure 17 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0149] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. The memory device 1120 may include a gate stack, a dummy stack, multiple stepped grooves defined at different depths in the gate contact region of the gate stack, multiple openings passing through the dummy stack and spaced apart from each other, a gap-filling insulating layer filling the multiple stepped grooves and multiple openings, multiple conductive gate contacts passing through the gap-filling insulating layer and connected to multiple conductive patterns, and multiple conductive peripheral circuit contacts passing through the gap-filling insulating layer.

[0150] Memory controller 1110 can be configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 serves as operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. Error correction block 1114 detects errors contained in data read from memory device 1120 and corrects the detected errors. Memory interface 1115 performs interface connections with memory device 1120. Memory controller 1110 may also include read-only memory (ROM) storing code data for connection to the host interface.

[0151] The aforementioned memory system 1100 may be a memory card or solid-state drive (SSD) that combines a memory device 1120 and a memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external source (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), PCI-E, Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0152] Figure 18 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0153] Reference Figure 18 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0154] The memory system 1210 may include a memory device 1212 and a memory controller 1211.

[0155] The memory device 1212 may include a gate stack, a dummy stack, a plurality of stepped grooves defined at different depths in the gate contact region of the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a gap-filling insulating layer filling the plurality of stepped grooves and the plurality of openings, a plurality of conductive gate contacts passing through the gap-filling insulating layer and connected to a plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the gap-filling insulating layer.

[0156] The memory controller 1211 can be configured to be related to a reference Figure 17 The memory controller 1110 described is the same.

[0157] According to this disclosure, in some embodiments, an etching process for defining a plurality of stepped grooves in a gate stack can be used to form a plurality of openings for a plurality of conductive peripheral circuit contacts. Therefore, in some embodiments, the manufacturing process of the semiconductor memory device can be simplified because a separate process for forming the plurality of openings can be omitted.

[0158] Cross-references to related applications

[0159] This application claims priority to Korean Patent Application No. 10-2021-0141663, filed on October 22, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate stack comprising a cell array region and a gate contact region, and comprising alternating layers of a plurality of first interlayer insulating patterns and a plurality of conductive patterns; A dummy stack comprising a plurality of second interlayer insulation patterns and a plurality of sacrificial insulation layers that are alternately stacked along the direction in which the plurality of first interlayer insulation patterns and the plurality of conductive patterns are alternately stacked. Multiple stepped grooves are spaced apart from each other in the gate contact region of the gate stack and defined at different depths in the gate stack. Multiple openings, which pass through the dummy stack and are spaced apart from each other; The first gap is filled with an insulating pattern, which fills the plurality of stepped grooves; A second gap is filled with an insulating pattern that fills the plurality of openings; A plurality of conductive gate contacts, wherein the plurality of conductive gate contacts pass through the first gap, are filled with an insulating pattern, and are connected to the plurality of conductive patterns; as well as Multiple conductive peripheral circuit contacts, which pass through the second gap and are filled with an insulating pattern. The number of conductive peripheral circuit contacts in at least one of the plurality of openings is different from the number of conductive peripheral circuit contacts in another opening, such that the areas of the plurality of openings are different from each other.

2. The semiconductor memory device according to claim 1, wherein, The plurality of openings includes a first opening and a second opening, wherein the second opening has a cross-sectional area narrower than that of the first opening.

3. The semiconductor memory device according to claim 2, wherein, The plurality of conductive peripheral circuit contacts include at least two first conductive peripheral circuit contacts that are insulated from each other by an insulating pattern filled in the first opening through the second gap.

4. The semiconductor memory device according to claim 3, in, The plurality of conductive peripheral circuit contacts include a second conductive peripheral circuit contact disposed in the second opening, and The number of the second conductive peripheral circuit contacts is less than the number of the first conductive peripheral circuit contacts.

5. The semiconductor memory device according to claim 1, wherein, Each of the plurality of stepped grooves includes a stepped sidewall, and The flatness of the sidewall of each of the plurality of openings is higher than the flatness of the stepped sidewall.

6. The semiconductor memory device according to claim 1, wherein, The gate stack and the dummy stack are formed on the etch stop layer.

7. The semiconductor memory device according to claim 6, wherein, A portion of the etch stop layer is in contact with the second gap-filling insulating pattern.

8. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A laminate is formed by alternately stacking multiple first material layers and multiple second material layers; Multiple preliminary stepped grooves are formed at a first depth in the gate contact region of the stacked material; Multiple stepped grooves of different depths are formed by etching a portion of the multiple initial stepped grooves; as well as By etching the peripheral circuit contact area of ​​the laminate simultaneously with etching the plurality of preliminary stepped grooves, a plurality of spaced-apart openings are formed in the peripheral circuit contact area of ​​the laminate. The method further includes the following steps: A gap-filling insulating layer is formed to fill the plurality of openings and the plurality of stepped grooves; Forming a plurality of conductive gate contacts that pass through the gap-filling insulating layer and extend into the plurality of stepped grooves; and While forming the plurality of conductive gate contacts, a plurality of conductive peripheral circuit contacts are also formed, passing through the gap-filling insulating layer and extending into the plurality of openings. The number of conductive peripheral circuit contacts in at least one of the plurality of openings is different from the number of conductive peripheral circuit contacts in another opening, such that the areas of the plurality of openings are different from each other.

9. The method according to claim 8, wherein, Each of the plurality of preliminary stepped grooves includes a plurality of frame regions, and The steps for forming the plurality of stepped grooves include the following steps: Etching the plurality of frame regions causes the plurality of frame regions of the plurality of initial stepped grooves to move to a second depth greater than the first depth; and A vertical etching process is performed on at least one of the plurality of frame regions that have moved to the second depth, such that the at least one frame region moves to the depth set by the lowest layer of the plurality of first material layers and the plurality of second material layers.

10. The method according to claim 9, wherein, The plurality of openings are formed by performing the vertical etching process.

11. The method of claim 8, further comprising the step of: A slit insulating layer is formed that passes through the gap-filling insulating layer and through the stack between the gate contact region and the peripheral circuit contact region; as well as A slit is formed that passes through the cell array region of the stack, through the gate contact region of the stack, and extends toward the slit insulating layer.

12. The method of claim 11, further comprising the step of: In the gate contact region and the cell array region of the stack, a portion of the plurality of first material layers is replaced by a plurality of conductive patterns through the slit.

13. The method according to claim 11, wherein, The laminate and the gap-filling insulating layer are formed on the etch stop layer.

14. The method according to claim 13, wherein, The gap-filling insulating layer is formed of a material that has etch selectivity relative to the etch-stopping layer.

15. The method according to claim 13, wherein, The plurality of openings include a bottom surface defined by the surface of the etch stop layer.

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