Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. A semiconductor device includes a first conductive line, a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line, and a selector layer disposed between the first conductive line and the second conductive line and including a dielectric material and a dopant doped with a uniform dopant distribution.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean Patent Application No. 10-2021-0144323, filed on October 27, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] This patent document relates to storage circuits or storage devices and their application in electronic devices or electronic systems. Background Technology

[0004] Recent trends in the electrical and electronics industry toward miniaturization, low power consumption, high performance, and versatility have prompted semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include memory devices capable of storing data by switching between different resistance states based on applied voltage or current. Semiconductor devices can include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse). Summary of the Invention

[0005] The technologies disclosed in this patent document include storage circuits or storage devices and their applications in electronic devices or electronic systems, as well as various embodiments of electronic devices, wherein semiconductor devices can improve cell-to-cell variation and reduce manufacturing costs by forming a doped selector layer with a uniform dopant distribution via a single patterning process.

[0006] On one hand, a semiconductor device may include: a first wire; a second wire disposed on top of the first wire and spaced apart from the first wire; and a selector layer disposed between the first wire and the second wire and comprising a dielectric material and dopant doped in a uniform dopant distribution.

[0007] On the other hand, a method of manufacturing a semiconductor device may include: forming a trench on a dielectric material formed on a substrate; forming a first conductive line in the trench such that the first conductive line and a first dielectric layer are disposed on the substrate; forming a separator layer on the first dielectric layer at a first center-to-center distance between adjacent first dielectric layers, wherein the first center-to-center distance may be twice the center-to-center distance between adjacent first conductive lines, and wherein the separator layer comprises a dielectric material; forming a dielectric material layer to be formed as a selector layer on the first conductive line, the first dielectric layer and the separator layer; and forming an initial selector layer by performing a first ion implantation of a dopant on the dielectric material layer at a first tilt angle and a second ion implantation of a dopant on the dielectric material layer at a second tilt angle, wherein the first tilt angle may be in a direction opposite to the second tilt angle relative to a line perpendicular to the surface of the layer, and the initial selector layer has a uniform dopant distribution. Attached Figure Description

[0008] Figure 1A and Figure 1B Semiconductor devices based on some embodiments of the technology disclosed herein are shown.

[0009] Figure 2 Examples of magnetic tunnel junction (MTJ) structures included in a variable resistance layer based on some embodiments of the present disclosure are shown.

[0010] Figures 3A to 3I This is a cross-sectional view illustrating an example method for manufacturing a semiconductor device based on some embodiments of the technology disclosed herein. Detailed Implementation

[0011] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0012] Figure 1A and Figure 1B Semiconductor devices based on some embodiments of the technology disclosed herein are shown. Figure 1A It's a floor plan. Figure 1B It is along Figure 1A A sectional view taken by the A-A' line.

[0013] refer to Figure 1A and Figure 1BThe semiconductor device may include a crossover structure, which includes a substrate 100, a first wire 110, a second wire 130, and a memory cell 120. The first wire 110 is formed on the substrate 100 and extends in a first direction. The second wire 130 is formed on the first wire 110, spaced apart from the first wire, and extends in a second direction intersecting the first direction. The memory cell 120 is disposed at the intersection of the first wire 110 and the second wire 130.

[0014] Substrate 100 may include a semiconductor material such as silicon. A desired underlying structure (not shown) may be formed in substrate 100. For example, substrate 100 may include drive circuitry (not shown) electrically connected to first wire 110 and / or second wire 130 to control the operation of memory cell 120. In this patent document, wires may indicate conductive structures that electrically connect two or more circuit elements in a semiconductor device. In some embodiments, wires include word lines and bit lines, where word lines are used in the memory device to control access to memory cells, and bit lines are used to read information stored in memory cells. In some embodiments, wires include interconnects that carry signals between different circuit elements in the semiconductor device.

[0015] The first wire 110 and the second wire 130 can be connected to the lower and upper ends of the memory cell 120, respectively, and can transmit voltage or current to the memory cell 120 to drive it. When the first wire 110 serves as a word line, the second wire 130 can serve as a bit line. Conversely, when the first wire 110 serves as a bit line, the second wire 130 can serve as a word line. The first wire 110 and the second wire 130 can include a single-layer or multi-layer structure having one or more of a variety of conductive materials. Examples of conductive materials include, but are not limited to, metals, metal nitrides, or conductive carbon materials or combinations thereof. For example, the first conductor 110 and the second conductor 130 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN) or combinations thereof.

[0016] The storage cells 120 can be arranged in a matrix of rows and columns along a first direction and a second direction, such that the intersection regions between the first conductor 110 and the second conductor 130 overlap. In one embodiment, the size of each of the storage cells 120 can be substantially equal to or smaller than the size of the intersection region between each pair of the first conductor 110 and the second conductor 130. In another embodiment, the size of each of the storage cells 120 can be larger than the size of the intersection region between each pair of the first conductor 110 and the second conductor 130.

[0017] The space between the first conductor 110, the second conductor 130, and the memory cell 120 may be filled by a dielectric layer. The dielectric layer may include a first interlayer dielectric layer 101, a second interlayer dielectric layer 102, a separator layer 103, a third interlayer dielectric layer 104, a fourth interlayer dielectric layer 105, a fifth interlayer dielectric layer 106, and a sixth interlayer dielectric layer 107. Each of dielectric layers 101 to 107 may include a dielectric material. Examples of dielectric materials may include oxides, nitrides, or combinations thereof. Each of dielectric layers 101 to 107 may include the same material or different materials from each other. In some embodiments, the semiconductor device may include a plurality of first conductors, a plurality of second conductors, and a plurality of selector layers. The plurality of first conductors are configured to electrically connect two or more circuit elements in the semiconductor device, the plurality of second conductors are configured to electrically connect two or more circuit elements in the semiconductor device and are disposed above the first conductors and spaced apart from them, and the plurality of selector layers are disposed between the first conductors and the second conductors. In one example, the selector layer includes a dielectric material and dopant distributed using a uniform dopant distribution. In some embodiments, the semiconductor device further includes: a first dielectric layer disposed in the space between the first conductors; a separator layer disposed in the first space between the selector layers and over the first dielectric layer; and a second dielectric layer disposed in a second space between the selector layers and over the first dielectric layer. Here, the first dielectric layer may include a first interlayer dielectric layer 101, and the second dielectric layer may include a fifth interlayer dielectric layer 106.

[0018] The storage cell 120 may include a stacked structure, which includes a lower electrode layer 121, a selector layer 122, an intermediate electrode layer 123, a variable resistor layer 124, and an upper electrode layer 125.

[0019] A lower electrode layer 121 may be inserted between the first conductor 110 and the selector layer 122 and is disposed at the bottom of each of the memory cells 120. The lower electrode layer 121 can serve as a circuit node carrying voltage or current between the corresponding one of the first conductors 110 and the remainder of each of the memory cells 120 (e.g., elements 122, 123, 124, and 125). An intermediate electrode layer 123 may be inserted between the selector layer 122 and the variable resistor layer 124. The intermediate electrode layer 123 can electrically connect the selector layer 122 and the variable resistor layer 124 to each other while physically isolating them from each other. An upper electrode layer 125 may be disposed at the top of the memory cell 120 and serves as a voltage or current transmission path between the remainder of the memory cell 120 and the corresponding one of the second conductors 130.

[0020] The lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 125 may each comprise a single-layer or multi-layer structure having a variety of conductive materials (such as metals, metal nitrides, conductive carbon materials, or combinations thereof). For example, the lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 125 may comprise tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN), or combinations thereof.

[0021] The lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 125 may be made of the same material or different materials.

[0022] The lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 125 may have the same thickness or different thicknesses.

[0023] Selector layer 122 can be used to control access to variable resistor layer 124. For this purpose, selector layer 122 can have the characteristic of adjusting current flow according to the magnitude of the applied voltage or current; that is, blocking or substantially limiting the current flowing through memory cell 120 when the applied voltage is less than a predetermined threshold, and allowing a sudden increase in the current flowing through memory cell 120 when the applied voltage is equal to or greater than the threshold. Selector layer 122 may include MIT (metal-insulator transition) materials (such as NbO2, TiO2, VO2, WO2, or others) and MIEC (mixed ionic-electronic conduction) materials (such as ZrO2 (Y2O3), Bi2O3-BaO, (La2O3)). x (CeO2) 1-x Alternatively, it may include OTS (bidirectional threshold switching) materials such as chalcogenide materials (e.g., Ge2Sb2Te5, As2Te3, As2, As2Se3, or others) or tunneling insulating materials such as silicon oxide, silicon nitride, metal oxide, or others. The thickness of the tunneling insulating layer is small enough to allow electron tunneling at a given voltage or current. Selector layer 122 may include a single-layer or multi-layer structure.

[0024] In one embodiment, selector layer 122 can be configured to perform a threshold switching operation. In this patent document, the term "threshold switching operation" can be used to indicate the operation of turning selector layer 122 on or off when an external voltage is applied to it. The absolute value of the external voltage can be controlled to gradually increase or decrease. When the absolute value of the external voltage applied to selector layer 122 increases, selector layer 122 can be turned on to conduct electricity to allow current to flow when the absolute value of the external voltage is greater than a first threshold voltage. Once selector layer 122 is turned on, the increase in external voltage will cause the operating current flowing through it to increase non-linearly. After selector layer 122 is turned on, when the absolute value of the external voltage applied to selector layer 122 decreases, the operating current flowing through selector layer 122 decreases non-linearly, and when the absolute value of the external voltage further decreases to a voltage value less than a second threshold voltage, the operating current is turned off. Therefore, selector layer 122 performing the threshold switching operation can have non-memory operating characteristics.

[0025] In some embodiments, the selector layer 122 can perform threshold switching operations via doped regions formed in the material layer used for the selector layer 122. Therefore, the size of the threshold switching operation region can be controlled by the distribution area of ​​the dopant. The dopant can form trap sites for charge carriers in the material layer used for the selector layer 122. The trap sites can capture charge carriers moving within the selector layer 122 between the intermediate electrode layer 123 and the lower electrode layer 121 based on an external voltage applied to the selector layer 122. Therefore, the trap sites provide threshold switching characteristics and are used to perform threshold switching operations.

[0026] In some embodiments, selector layer 122 may include a dielectric material with added dopants. Selector layer 122 may include oxides, nitrides, or oxide nitrides with dopants, or combinations thereof, such as silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon oxide nitride, titanium oxide nitride, aluminum oxide nitride, tungsten oxide nitride, hafnium oxide nitride, tantalum oxide nitride, or niobium oxide nitride, or combinations thereof. Dopants incorporated into selector layer 122 may include n-type or p-type dopants, and may be added, for example, by an ion implantation process. Examples of dopants may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge). For example, selector layer 122 may include arsenic (As) doped silicon oxide or germanium (Ge) doped silicon oxide.

[0027] In some implementations, the doped selector layer can be formed by depositing a dielectric material as a matrix for the selector layer and then adding dopants via an ion implantation process. In this case, because the ion implantation process is performed in the vertical direction, the dopant distribution can be non-uniform in the vertical direction. That is, due to matrix loss on the upper surface of the selector layer and dopant accumulation at the interface of the layer disposed below the selector layer, the dopant concentration can decrease upwards and downwards relative to Rp (projection distance), resulting in a non-uniform dopant distribution in the vertical direction for the selector layer. Since the non-uniform dopant distribution of the selector layer can lead to cell-to-cell distribution, cell array operation may deteriorate and may place a burden on the controller. In some implementations, spacer patterning (SPT) techniques may be needed to pattern the selector layer due to the need to reduce the spacing (e.g., the center-to-center distance between adjacent layers) for highly integrated semiconductor devices. SPT may include forming spacers and patterning the selector layer using spacers. However, with SPT, process efficiency may decrease and production costs and manufacturing difficulties may increase due to its additional fabrication steps.

[0028] However, in some embodiments of the disclosed technology, the dopant distribution of the selector layer 122 can be uniform. That is, the selector layer 122 may include a dielectric material and dopant doped using a dopant distribution uniformly distributed in both directions parallel to the surface of the layer and perpendicular to the surface of the layer. Therefore, since the selector layer 122 has a uniform dopant distribution, cell-to-cell distribution can be improved and cell array operation degradation and controller load can be prevented or reduced.

[0029] In some implementations, selector layer 122 may include a first portion 122-1 and a second portion 122-2.

[0030] The first portion 122-1 may be formed on the lower electrode layer 121. One sidewall of the first portion 122-1 may contact the separator layer 103, the upper portion of the other sidewall of the first portion 122-1 may contact the third interlayer dielectric layer 104, and the lower portion of the other sidewall of the first portion 122-1 may contact the second portion 122-2. In one example, the entire area of ​​the sidewall may contact the separator layer 103.

[0031] The second portion 122-2 may be formed between the second interlayer dielectric layer 102 and the third interlayer dielectric layer 104. The two sidewalls of the second portion 122-2 may contact the first portion 122-1, respectively. In one example, the entire area of ​​the two sidewalls of the second portion 122-2 may contact the first portion 122-1, respectively.

[0032] The following will be referenced Figures 3A to 3I The formation of selector layer 122 is described in detail.

[0033] The variable resistance layer 124 can be used to store data using different resistance states of the variable resistance layer 124 by setting the variable resistance layer 124 to a desired resistance state (e.g., using a high resistance state and a low resistance state to represent digital levels "1" and "0"), and to change the stored data bits by switching between different resistance states according to the applied voltage or current. The variable resistance layer 124 can have a single-layer structure or a multi-layer structure including at least one of the materials used in RRAM, PRAM, MRAM, FRAM, and others. For example, the variable resistance layer 124 can include metal oxides (e.g., transition metal oxides or perovskite-based oxides), phase change materials (e.g., chalcogenide-based materials for PRAM), ferromagnetic materials for MRAM, ferroelectric materials for FRAM, or others. However, the implementation is not limited to this, and the memory cell 120 can include other memory layers capable of storing data in a variety of ways instead of the variable resistance layer 124.

[0034] In some embodiments, the variable resistance layer 124 may include a magnetic tunnel junction (MTJ) structure. (Refer to...) Figure 2 This needs to be explained.

[0035] Figure 2 An example of a magnetic tunnel junction (MTJ) structure included in the variable resistance layer 124 is shown.

[0036] The variable resistance layer 124 may include an MTJ structure, which includes a free layer 13 with a variable magnetization direction, a fixed layer 15 with a fixed magnetization direction, and a tunnel barrier layer 14 inserted between the free layer 13 and the fixed layer 15.

[0037] In the MTJ structure, the free layer 13 can have one of different magnetization directions or one of different electron spin directions to switch the polarity of the free layer 13, resulting in a change in the resistance value. In some embodiments, the polarity of the free layer 13 is changed or flipped according to a voltage or current signal applied to the MTJ structure (e.g., a drive current exceeding a certain threshold). As the polarity of the free layer 13 changes, the free layer 13 and the fixed layer 15 have different magnetization directions or different electron spin directions, which allows the variable resistance layer 124 to store different data or represent different data bits. The free layer 13 can also be referred to as a storage layer. The magnetization direction of the free layer 13 can be substantially perpendicular to the surfaces of the free layer 13, the tunnel barrier layer 14, and the fixed layer 15. In other words, the magnetization direction of the free layer 13 can be substantially parallel to the stacking direction of the free layer 13, the tunnel barrier layer 14, and the fixed layer 15. Therefore, the magnetization direction of the free layer 13 can be changed between the downward and upward directions. The change in the magnetization direction of the free layer 13 can be caused by the spin-transfer torque generated by the applied current or voltage.

[0038] The free layer 13 may have a single-layer or multi-layer structure comprising ferromagnetic materials. For example, the free layer 13 may comprise an alloy based on Fe, Ni, or Co (e.g., Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Co-Fe alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, or Co-Fe-B alloy or others) or may comprise a metal stack (such as Co / Pt or Co / Pd or others).

[0039] In both data read and write operations, the tunnel barrier layer 14 allows electrons to tunnel through. In a write operation for storing new data, a high write current can be directed through the tunnel barrier layer 14 to change the magnetization direction of the free layer 13, and thus change the resistance state of the MTJ to write new data bits. In a read operation, a low read current can be directed through the tunnel barrier layer 14 without changing the magnetization direction of the free layer 13, thereby measuring the existing resistance state of the MTJ under the existing magnetization direction of the free layer 13 to read the data bits stored in the MTJ. The tunnel barrier layer 14 may comprise a dielectric oxide, such as MgO, CaO, SrO, TiO, VO, or NbO or others.

[0040] The fixed layer 15 may have a fixed magnetization direction that remains unchanged when the magnetization direction of the free layer 13 changes. The fixed layer 15 may be referred to as a reference layer. In some embodiments, the magnetization direction of the fixed layer 15 may be fixed in a downward direction. In some embodiments, the magnetization direction of the fixed layer 15 may be fixed in an upward direction.

[0041] The fixing layer 15 may have a single-layer or multi-layer structure comprising ferromagnetic materials. For example, the fixing layer 15 may comprise an alloy based on Fe, Ni, or Co (e.g., Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Co-Fe alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, or Co-Fe-B alloy), or may comprise a metal stack (e.g., Co / Pt or Co / Pd or others).

[0042] If a voltage or current is applied to the variable resistor layer 124, the magnetization direction of the free layer 13 can be changed by a spin-transfer torque. In some embodiments, when the magnetization directions of the free layer 13 and the fixed layer 15 are parallel to each other, the variable resistor layer 124 can be in a low-resistance state, which can indicate a digital data bit "0". Conversely, when the magnetization directions of the free layer 13 and the fixed layer 15 are antiparallel to each other, the variable resistor layer 124 can be in a high-resistance state, which can indicate a digital data bit "1". In some embodiments, the variable resistor layer 124 can be configured to store a data bit "1" when the magnetization directions of the free layer 13 and the fixed layer 15 are parallel to each other and to store a data bit "0" when the magnetization directions of the free layer 13 and the fixed layer 15 are antiparallel to each other.

[0043] In some embodiments, the variable resistance layer 124 may also include one or more layers that perform multiple functions to improve the characteristics of the MTJ structure. For example, the variable resistance layer 124 may also include at least one of a buffer layer 11, a lower layer 12, a spacer layer 16, a magnetic correction layer 17, and a cover layer 18.

[0044] The lower layer 12 can be disposed below the free layer 13 and is used to improve the vertical magnetocrystalline anisotropy of the free layer 13. The lower layer 12 can have a single-layer or multi-layer structure including metal, metal alloy, metal nitride or metal oxide or a combination thereof.

[0045] Buffer layer 11 can be disposed below lower layer 12 to promote crystal growth of lower layer 12, thereby improving the perpendicular magnetocrystalline anisotropy of free layer 13. Buffer layer 11 can have a single-layer or multi-layer structure comprising metal, metal alloy, metal nitride, or metal oxide, or combinations thereof. Furthermore, buffer layer 11 can be formed of or include a material having good compatibility with the bottom electrode (not shown) to resolve lattice constant mismatch between the bottom electrode and lower layer 12. For example, buffer layer 11 may include tantalum (Ta).

[0046] Spacer 16 can be inserted between magnetic correction layer 17 and fixing layer 15, and serves as a buffer between them. Spacer 16 can improve the characteristics of magnetic correction layer 17. Spacer 16 may include a noble metal such as ruthenium (Ru).

[0047] The magnetic correction layer 17 can be used to counteract the effects of stray magnetic fields caused by the fixed layer 15. In this case, the influence of the stray magnetic field of the fixed layer 15 can be reduced, and therefore the bias magnetic field in the free layer 13 can be reduced. The magnetic correction layer 17 can have a magnetization direction antiparallel to the magnetization direction of the fixed layer 15. In an embodiment, when the fixed layer 15 has a downward magnetization direction, the magnetic correction layer 17 can have an upward magnetization direction. Conversely, when the fixed layer 15 has an upward magnetization direction, the magnetic correction layer 17 can have a downward magnetization direction. The magnetic correction layer 17 can be exchange-coupled with the fixed layer 15 through the spacer layer 16 to form a synthetic antiferromagnetic (SAF) structure. The magnetic correction layer 17 can have a single-layer or multi-layer structure comprising ferromagnetic materials.

[0048] In this embodiment, the magnetic correction layer 17 is located above the fixed layer 15, but the magnetic correction layer 17 can be disposed in different locations. For example, when the magnetic correction layer 17 is patterned separately from the MTJ structure, the magnetic correction layer 17 can be located above, below, or adjacent to the MTJ structure.

[0049] The capping layer 18 can be used to protect the variable resistor layer 124 and / or serve as a hard mask for patterning the variable resistor layer 124. In some embodiments, the capping layer 18 may comprise a variety of conductive materials such as metals. In some embodiments, the capping layer 18 may comprise a metallic material having few or no pinholes and high tolerance to wet and / or dry etching. In some embodiments, the capping layer 18 may comprise metals, nitrides, or oxides, or combinations thereof. For example, the capping layer 18 may comprise a noble metal such as ruthenium (Ru).

[0050] The capping layer 18 may have a single-layer or multi-layer structure. In some embodiments, the capping layer 18 may have a multi-layer structure comprising oxides or metals or combinations thereof. For example, the capping layer 18 may have a multi-layer structure comprising an oxide layer, a first metal layer, and a second metal layer.

[0051] A material layer (not shown) for addressing the lattice structure differences and lattice constant mismatch between the fixed layer 15 and the magnetic correction layer 17 can be interposed between the fixed layer 15 and the magnetic correction layer 17. For example, such a material layer can be amorphous and can include metals, metal nitrides, or metal oxides.

[0052] In some embodiments, each of the memory cells 120 includes a lower electrode layer 121, a selector layer 122, an intermediate electrode layer 123, a variable resistor layer 124, and an upper electrode layer 125, which are stacked sequentially. However, the memory cells 120 may have different structures. In some embodiments, the selector layer 122 and the variable resistor layer 124 may be stacked in a different order. For example, the selector layer 122 and the variable resistor layer 124 may be stacked in a different order relative to each other. Figure 1B The layers are stacked in the reverse order of the orientations shown, so that the selector layer 122 can be disposed above the variable resistor layer 124. In some embodiments, at least one of the lower electrode layer 121, the intermediate electrode layer 123, and the upper electrode layer 125 may be omitted. In some embodiments, except... Figure 1B In addition to layers 121 to 125 shown, storage cell 120 may also include one or more layers (not shown) for improving the characteristics of storage cell 120 or improving the manufacturing process.

[0053] In some embodiments, adjacent memory cells of the plurality of memory cells 120 may be spaced apart from each other at a predetermined interval, and trenches may exist between the plurality of memory cells 120. The trenches between adjacent memory cells 120 may have a height-to-width ratio (i.e., aspect ratio) in the range of 1:1 to 40:1, 10:1 to 40:1, 10:1 to 20:1, 5:1 to 10:1, 10:1 to 15:1, 1:1 to 25:1, 1:1 to 30:1, 1:1 to 35:1, or 1:1 to 45:1.

[0054] In some embodiments, the trenches may have sidewalls that are substantially perpendicular to the upper surface of the substrate 100. In some embodiments, adjacent trenches may be spaced apart from each other at the same or similar distance.

[0055] In some embodiments, the semiconductor device may further include more layers in addition to the first conductor 110, the memory cell 120, and the second conductor 130. For example, a lower electrode contact may be formed between the first conductor 110 and the lower electrode layer 121, and an upper electrode contact may be formed between the second conductor 130 and the upper electrode layer 125.

[0056] Although one cross-point structure has been described, two or more cross-point structures can be stacked in a vertical direction perpendicular to the top surface of the substrate 100.

[0057] Reference Figures 3A to 3I This describes a method for manufacturing semiconductor devices.

[0058] refer to Figure 3AThe first conductive line 310 can be formed on a substrate 300 having a predetermined structure. The first conductive line 310 can be formed by: forming a first interlayer dielectric layer 301 on the substrate 300, the first interlayer dielectric layer 301 having trenches for forming the first conductive line 310; forming a conductive layer for the first conductive line 310; and etching the conductive layer using a linear mask pattern extending in a first direction.

[0059] The lower electrode layer 321 can be formed on the first conductor 310. The lower electrode layer 321 can be formed by: forming a second interlayer dielectric layer 302 with holes on the structure on which the first conductor is formed; forming a material layer for the lower electrode layer 321; and performing a planarization process such as chemical mechanical planarization (CMP).

[0060] The first interlayer dielectric layer 301 and the second interlayer dielectric layer 302 may include oxides, nitrides, or combinations thereof.

[0061] refer to Figure 3B , can Figure 3A A separation layer 303 is formed on top of the second interlayer dielectric layer 302 of the structure.

[0062] The spacing D2 between the separator layers 303 can be approximately twice the spacing D1 between the first conductors 310. In one example, spacing D2 can indicate the center-to-center distance between adjacent separator layers 303, and spacing D1 can indicate the center-to-center distance between adjacent first conductors 310.

[0063] The separator layer 303 may be formed of a dielectric material. For example, the separator layer 303 may include oxides, nitrides, or combinations thereof.

[0064] refer to Figure 3C , can Figure 3B The structure forms a selector layer (see Figure 3G The matrix layer 322A (reference numeral 322) is shown in the attached figure.

[0065] The matrix layer 322A may be the layer to be formed as the selector layer 322 by introducing dopants via a subsequent ion implantation process.

[0066] It is possible Figure 3B A matrix layer 322A is conformally formed on the structure. That is, a matrix layer 322A can be formed to cover the second interlayer dielectric layer 302, the lower electrode layer 321, and the separator layer 303.

[0067] The matrix layer 322A can be formed using common deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or other deposition methods.

[0068] The matrix layer 322A may include a dielectric material. For example, the matrix layer 322A may include oxides, nitrides, oxynitrides, or combinations thereof. For example, oxides, nitrides, oxynitrides, or combinations thereof may include silicon oxides, titanium oxides, aluminum oxides, tungsten oxides, hafnium oxides, tantalum oxides, niobium oxides, silicon nitrides, titanium nitrides, aluminum nitrides, tungsten nitrides, hafnium nitrides, tantalum nitrides, niobium nitrides, silicon oxynitrides, titanium oxynitrides, aluminum oxynitrides, tungsten oxynitrides, hafnium oxynitrides, tantalum oxynitrides, or niobium oxynitrides, or combinations thereof.

[0069] refer to Figure 3D , can be Figure 3C The structure is subjected to a first ion implantation process. Dopant can be added to the matrix layer 322A through the first ion implantation process to form the initial selector layer 322B.

[0070] The first ion implantation process can be achieved through tilted ion implantation.

[0071] In this implementation, selector layer 322 can perform two tilted ion implantations in two directions instead of vertical ion implantation (see [link]). Figure 3D and Figure 3E It has a uniform dopant distribution in the vertical direction. Tilted ion implantation can be performed at an angle relative to a line perpendicular to the surface of the layer.

[0072] In some implementations, tilted ion implantation can be performed using a tilt angle of about 45 to 85 degrees in order to prevent shadowing effects caused by adjacent patterns.

[0073] The dopants introduced by the first ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

[0074] refer to Figure 3E , can Figure 3D The second ion implantation process is performed on the structure.

[0075] A second ion implantation process can be performed using tilted ion implantation. Tilted ion implantation can be performed using a tilt angle of approximately 45 to 85 degrees to prevent shadowing effects caused by adjacent patterns.

[0076] The second ion implantation process can be performed in a direction opposite to the first ion implantation process, relative to a line perpendicular to the surface of the layer. That is, when the first ion implantation process is performed in a direction from the upper left to the lower right, the second ion implantation process can be performed in a direction from the upper right to the lower left. When the first ion implantation process is performed in a direction from the upper right to the lower left, the second ion implantation process can be performed in a direction from the upper left to the lower right.

[0077] The dopants introduced by the first ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

[0078] In some implementations, the dopant introduced by the first ion implantation process and the dopant introduced by the second ion implantation process may be the same as each other.

[0079] In some implementations, the dopant introduced by the first ion implantation process and the dopant introduced by the second ion implantation process may be different from each other.

[0080] In this way, an initial selector layer 322B comprising dielectric material and dopant can be formed by conformally forming a matrix layer 322A and performing a tilted ion implantation process twice in each direction. The initial selector layer 322B can have a uniform dopant distribution in both the direction parallel to and the direction perpendicular to the surface of the layer.

[0081] refer to Figure 3F , can Figure 3E A third interlayer dielectric layer 304 is formed on top of the structure.

[0082] The third interlayer dielectric layer 304 may include oxides, nitrides, or combinations thereof.

[0083] refer to Figure 3G A planarization process, such as CMP, can be performed to expose the separator layer 303.

[0084] The initial selector layer 322B can be separated by the separator layer 303 through a planarization process to form the selector layer 322.

[0085] Selector layer 322 may include a first part 322-1 and a second part 322-2.

[0086] A first portion 322-1 may be formed on top of the lower electrode layer 321. One sidewall of the first portion 322-1 may contact the separator layer 303, the upper portion of the other sidewall of the first portion 322-1 may contact the third interlayer dielectric layer 304, and the lower portion of the other sidewall of the first portion 322-1 may contact the second portion 322-2. In one example, the entire area of ​​the sidewall may contact the separator layer 303.

[0087] A second portion 322-2 may be formed between the second interlayer dielectric layer 302 and the third interlayer dielectric layer 304. The two sidewalls of the second portion 322-2 may contact the first portion 322-1, respectively. In one example, the entire area of ​​the two sidewalls of the second portion 322-2 may contact the first portion 322-1, respectively.

[0088] Selector layer 322 may include a dielectric material and dopants. Selector layer 322 may have a uniform dopant distribution in both directions parallel and perpendicular to the surface of the layer.

[0089] In an implementation, even if the spacing is reduced to, for example, 50 nm, the selector layer 322 can be implemented without using SPT by the method described above.

[0090] refer to Figure 3H , can Figure 3G An intermediate electrode layer 323, a variable resistor layer 324, and an upper electrode layer 325 are sequentially formed on top of the structure. Therefore, a memory cell 320 including a lower electrode layer 321, a selector layer 322, an intermediate electrode layer 323, a variable resistor layer 324, and an upper electrode layer 325 can be formed.

[0091] The intermediate electrode layer 323 can be formed as follows: Figure 3G A fourth interlayer dielectric layer 305 with holes is formed on the structure; a material layer for an intermediate electrode layer 323 is formed in the holes; and a planarization process such as CMP is performed.

[0092] The variable resistance layer 324 can be formed after the intermediate electrode layer 323 is formed by forming a material layer for the variable resistance layer 324 and patterning the material layer. Then, the fifth interlayer dielectric layer 306 can be formed.

[0093] The upper electrode layer 325 can be formed by forming a fifth interlayer dielectric layer 306 with holes after forming the variable resistance layer 324; forming a material layer for the upper electrode layer 325 in the holes; and performing a planarization process such as CMP.

[0094] In one embodiment, the intermediate electrode layer 323, the variable resistance layer 324, and the upper electrode layer 325 can be formed by separate processes. In another embodiment, at least two of the intermediate electrode layer 323, the variable resistance layer 324, and the upper electrode layer 325 can be formed by a single process. For example, the intermediate electrode layer 323 and the variable resistance layer 324 can be formed by sequentially forming material layers for the intermediate electrode layer 323 and for the variable resistance layer 324 while simultaneously patterning the material layers, and then the upper electrode layer 325 can be formed by the method described above. Alternatively, the intermediate electrode layer 323, the variable resistance layer 324, and the upper electrode layer 325 can be formed by sequentially forming material layers for the intermediate electrode layer 323, for the variable resistance layer 324, and for the upper electrode layer 325 while simultaneously patterning the material layers.

[0095] refer to Figure 3I , can Figure 3H A second conductor 330 is formed on top of the structure.

[0096] The second conductor 330 can be formed by forming a conductive layer for the second conductor 330 on the upper electrode layer 325 and etching the conductive layer using a linear mask pattern extending in the second direction.

[0097] The semiconductor device comprising a first conductive line 310, a memory cell 320, and a second conductive line 330 can be formed using the process described above. The memory cell 320 may include a lower electrode layer 321, a selector layer 322, an intermediate electrode layer 323, a variable resistor layer 324, and an upper electrode layer 325 that are stacked sequentially.

[0098] Selector layer 322 may include a first portion 322-1 and a second portion 322-2. The first portion 322-1 is formed on the lower electrode layer 321, and the second portion 322-2 is formed between the second interlayer dielectric layer 302 and the third interlayer dielectric layer 304. One sidewall of the first portion 322-1 may contact the separator layer 303, the upper portion of the other sidewall of the first portion 322-1 may contact the third interlayer dielectric layer 304, and the lower portion of the other sidewall of the first portion 322-1 may contact the second portion 322-2. In one example, the entire area of ​​the sidewall of the first portion 322-1 may contact the separator layer 303. Both sidewalls of the second portion 322-2 may contact the first portion 322-1, respectively. In one example, the entire area of ​​the two sidewalls of the second portion 322-2 may contact the first portion 322-1, respectively.

[0099] Selector layer 322 may include a dielectric material and dopants, and has a uniform dopant distribution in both directions parallel and perpendicular to the surface of the layer. Therefore, according to embodiments, cell-to-cell distribution can be improved to prevent or reduce variability in cell array operation and the burden on the controller. Furthermore, according to embodiments, selector layer 322 can be formed using a single patterning process instead of SPT, thereby reducing process complexity and cost and increasing process efficiency.

[0100] The substrate 300, the first conductive line 310, the storage cell 320, the lower electrode layer 321, the selector layer 322, the intermediate electrode layer 323, the variable resistor layer 324, the upper electrode layer 325, and the second conductive line 330 can respectively correspond to the substrate 100, the first conductive line 110, the storage cell 120, the lower electrode layer 121, the selector layer 122, the intermediate electrode layer 123, the variable resistor layer 124, the upper electrode layer 125, and the second conductive line 130.

[0101] Although this patent document contains numerous details, this should not be construed as limiting the scope of any disclosure or potentially claimed protection, but rather as a description of features that may be specific to particular embodiments of a particular disclosure. Certain features described in the context of individual embodiments of this patent document may also be implemented in combination in a single embodiment. Conversely, multiple features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from a claimed combination may be removed from the combination in certain circumstances, and the claimed combination may involve sub-combinations or variations thereof.

[0102] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific or sequential order shown, or that all illustrated operations be performed to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0103] Only a few embodiments and examples are described. The disclosed embodiments can be enhanced or modified, and other embodiments can be formed, based on what is described and shown in this patent document.

Claims

1. A semiconductor device, comprising: First conductor; A second conductor is disposed above the first conductor and spaced apart from the first conductor; as well as Selector layer, which: is disposed between the first wire and the second wire, and includes a dielectric material and dopant doped in a uniform dopant distribution; The semiconductor device further includes: a first dielectric layer disposed in the space between the first conductive lines; a separator layer disposed in the first space between the selector layers and above the first dielectric layer; and a second dielectric layer disposed in the second space between the selector layers and above the first dielectric layer, wherein the first space and the second space are different. The separator layer comprises a dielectric material, and the separator layer is configured such that the center-to-center distance between adjacent separator layers is twice the center-to-center distance between adjacent first conductors.

2. The semiconductor device according to claim 1, wherein, The dielectric material includes: silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, or niobium nitride, or a combination of two or more of the following: silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, or niobium nitride.

3. The semiconductor device according to claim 1, wherein, The dopant includes one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

4. The semiconductor device according to claim 1, wherein, Each of the selector layers includes a first part and a second part. The first portion is disposed on the first conductor, and the second portion is disposed on the first dielectric layer and below the second dielectric layer. The first sidewall of the first portion contacts the adjacent separator layer, the upper portion of the second sidewall of the first portion contacts the adjacent second dielectric layer, and the lower portion of the second sidewall of the first portion contacts the second portion. The first and second sidewalls of the second part are in contact with the first part.

5. The semiconductor device according to claim 1, wherein, The separator layer, the first dielectric layer, and the second dielectric layer may be made of the same dielectric material or different dielectric materials.

6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a variable resistance layer disposed above or below the selector layer.

7. A method for manufacturing a semiconductor device, comprising: Trenches are formed on a dielectric material formed on a substrate; A first conductor is formed in the trench, such that the first conductor and the first dielectric layer are disposed on the substrate; A separation layer is formed on the first dielectric layer at a center-to-center distance between adjacent separation layers, wherein the center-to-center distance between adjacent separation layers is twice the center-to-center distance between adjacent first conductors, and wherein the separation layer comprises a dielectric material; A dielectric material layer, which will be formed as a selector layer, is formed over the first conductor, the first dielectric layer, and the separator layer; and An initial selector layer is formed by performing a first ion implantation of the dopant into the dielectric material layer at a first tilt angle and a second ion implantation of the dopant into the dielectric material layer at a second tilt angle. Wherein, the first tilt angle is in a direction opposite to the second tilt angle relative to a line perpendicular to the surface of the dielectric material layer, and The initial selector layer has a uniform dopant distribution.

8. The method of claim 7, further comprising: A second dielectric layer is formed to cover the structure in which the initial selector layer is formed; as well as The selector layer is formed by performing a planarization process to expose the separator layer.

9. The method according to claim 8, wherein, The selector layer comprises a first part and a second part. The first portion is disposed on the first conductor, and the second portion is disposed on the first dielectric layer and below the second dielectric layer. The first sidewall of the first portion contacts the adjacent separator layer, the upper portion of the second sidewall of the first portion contacts the adjacent second dielectric layer, and the lower portion of the second sidewall of the first portion contacts the second portion. The first and second sidewalls of the second part are in contact with the first part.

10. The method according to claim 8, wherein, The selector layer has a uniform dopant distribution.

11. The method according to claim 7, wherein, The first tilt angle is an angle of 45 to 85 degrees relative to a line perpendicular to the surface of the dielectric material layer, and the second tilt angle is an angle of 45 to 85 degrees relative to a line perpendicular to the surface of the dielectric material layer.

12. The method according to claim 7, wherein, The dielectric material layer comprises: silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, or niobium nitride, or a combination of two or more of the following: silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, or niobium nitride.

13. The method according to claim 7, wherein, The dopant includes one or more selected from boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), and germanium (Ge).

14. The method according to claim 8, wherein, The separator layer, the first dielectric layer, and the second dielectric layer may be made of the same dielectric material or different dielectric materials.

15. The method of claim 8, further comprising forming a variable resistance layer above or below the selector layer.

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