Apparatus and method for clearing memory contents

Abstract

Aspects of the disclosure relate to systems and methods for issuing and performing a clear content command within a memory. Certain embodiments provide a method of clearing content stored on a volatile memory, the memory including a plurality of memory banks, a plurality of memory cells disposed on each of the plurality of memory banks, each of the plurality of memory cells coupled to an associated sense amplifier, the method comprising: receiving a clear content command configured to clear content stored on the memory in a first set of memory cells of the plurality of memory cells of the plurality of memory banks; and in response to the clear content command, activating a first switch and a second switch of each sense amplifier associated with each of the first set of memory cells, the first switch coupled between a first bit line coupled to a corresponding memory cell and ground, the second switch coupled between a second bit line and ground, wherein the second bit line is configured to act as a reference bit line when sensing content of the corresponding memory cell.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 17 / 010,037, filed September 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to various aspects of memory devices, and more particularly to systems and methods for issuing and executing commands to clear the contents of memory. Background Technology

[0004] Typically, the main memory in a computing system can use random access memory (RAM) devices as a source of volatile memory. RAM is particularly useful as memory due to its density and speed. One drawback is that RAM can occasionally malfunction due to factors such as neutrons or alpha particles passing through the die, faulty components, or inaccurate system timing. This drawback can be especially problematic for computing systems that transmit critical data or require data with virtually zero error tolerance.

[0005] Therefore, a computer system may include an error correction circuitry that generates and stores one or more error correction code (ECC) bits associated with data stored in RAM. Here, when the stored data is read from main memory, the associated ECC bits are also read and transmitted to the error correction circuitry for appropriate evaluation and, if necessary, error correction. In some RAM devices, the ECC bits are stored "in-line" with the corresponding data. In one example, for every 512 bits of payload data stored in the RAM device, the associated ECC bits are stored at a different location (address) in the same DRAM than the payload data.

[0006] However, in order to perform certain memory functions (such as partial data writing), the RAM region containing the stored data and its corresponding ECC bits must be initialized with matching values. For example, an application or processor might need to perform a process to initialize the RAM region by writing zeros into both the RAM region containing the stored data and the ECC bits. However, such a process can be relatively time-consuming and power-intensive. In one example, this could pose a problem for battery-powered RAM devices. As RAM devices are utilized more extensively, there is a need for further improvements to such devices. Summary of the Invention

[0007] The systems, methods, and apparatuses of this disclosure each have several aspects, none of which are solely responsible for their desired properties. Without limiting the scope of this disclosure as set forth in the following claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," it will be possible to understand how the features of this disclosure provide advantages.

[0008] Some embodiments provide a method for clearing contents stored on a memory of an electronic device, the memory including a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier. In some examples, the method includes receiving a clear contents command configured to clear contents stored on the memory in a first group of memory cells among the plurality of memory cells in the plurality of memory banks. In some examples, the method includes, in response to the clear contents command, activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

[0009] In some examples, the content clearing command includes a first-stage command and a second-stage command, wherein the first-stage command includes a first bit sequence and the second-stage command has a second bit sequence that is complementary to the first bit sequence.

[0010] In some examples, receiving a clear content command includes receiving a first-stage command before receiving a second-stage command.

[0011] In some examples, receiving a clear command includes reading a multi-bit command stored in the mode register.

[0012] In some examples, the method also includes clearing the mode register in response to determining that the contents of the first set of memory cells have been cleared.

[0013] In some examples, the memory is dynamic random access memory (DRAM) that utilizes in-line error correction codes (ECC).

[0014] In some examples, the controller receives commands in response to one or more of the following events: startup of the electronic device; a status error detected in memory; or a transient error detected in memory.

[0015] In some examples, the clear contents command includes an indicator configured to identify the first set of memory cells.

[0016] In some examples, the first set of memory cells includes at least one row of memory cells in each of the multiple memory banks.

[0017] Some aspects describe a device. In some examples, the device includes a memory comprising a plurality of memory banks, each of which has a plurality of memory cells disposed thereon, each of the memory cells being coupled to an associated sense amplifier. In some examples, the device includes a processor communicatively coupled to the memory. In some examples, the processor is configured to receive a clear contents command configured to clear contents stored on a first group of memory cells in the plurality of memory banks. In some examples, the processor is configured, in response to the clear contents command, to activate a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to clear the corresponding memory cell by grounding the first and second bit lines.

[0018] Some aspects relate to an apparatus configured to erase contents stored in a memory of an electronic device, the memory including a plurality of memory banks, each of which has a plurality of memory cells disposed thereon, each of the memory cells being coupled to an associated sense amplifier. In some examples, the apparatus includes means for receiving a erase contents command configured to erase contents stored in a first group of memory cells among the plurality of memory cells in the plurality of memory banks. In some examples, the apparatus includes means for activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells in response to the erase contents command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to erase the corresponding memory cell by grounding the first and second bit lines.

[0019] Some aspects relate to a non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a device, cause the device to perform a method of erasing contents stored on a memory of an electronic device. The memory includes a plurality of memory banks, each of which has a plurality of memory cells disposed thereon, and each of the memory cells is coupled to an associated sense amplifier. In some examples, the method includes the device receiving a erase contents command configured to erase contents stored on a first group of memory cells in the plurality of memory banks. In some examples, the method includes the device activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells in response to the erase contents command. The first switch is coupled between a first bit line of the corresponding memory cell and ground, and the second switch is coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to erase the corresponding memory cell by grounding the first and second bit lines.

[0020] The following description and accompanying drawings illustrate certain illustrative features of one or more embodiments. Attached Figure Description

[0021] The accompanying drawings depict certain aspects of one or more embodiments and should therefore not be construed as limiting the scope of this disclosure.

[0022] Figure 1 Example components and interconnects coupled to memory in a system-on-a-chip (SoC) suitable for implementing various aspects of this disclosure are shown.

[0023] Figure 2 Example components and interconnections in a memory suitable for implementing various aspects of this disclosure are shown.

[0024] Figure 3 This is a block diagram illustrating a high-level example of a DRAM memory system suitable for implementing various aspects of this disclosure.

[0025] Figure 4 This is a schematic diagram illustrating an example bit line (BL) sense amplifier suitable for implementing various aspects of this disclosure.

[0026] Figure 5A This is a first block diagram illustrating an example CA-encoded content clearing command suitable for implementing various aspects of this disclosure.

[0027] Figure 5B This is a second block diagram illustrating example CA encoding of a content clearing command suitable for implementing various aspects of this disclosure.

[0028] Figure 6This is a flowchart illustrating an example procedure for executing a clear content command in a mode register, suitable for implementing various aspects of this disclosure.

[0029] Figure 7 This is a schematic diagram illustrating a first example readout amplifier with two additional switches suitable for implementing various aspects of this disclosure.

[0030] Figure 8 This is a schematic diagram illustrating a second example readout amplifier with two additional switches suitable for implementing various aspects of this disclosure.

[0031] Figure 9 This is a flowchart illustrating example operations for clearing contents stored in the memory of an electronic device, suitable for implementing various aspects of this disclosure.

[0032] Figure 10 A processing system is shown that may include various components (e.g., corresponding to device plus functional components) configured to perform operations of the techniques disclosed herein.

[0033] For ease of understanding, the same reference numerals are used where possible to denote the same elements commonly seen in the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0034] This disclosure provides methods and apparatus for issuing and executing content-clearing commands to clear contents stored in a memory device.

[0035] The following description provides examples but does not limit the scope, applicability, or embodiments set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be appropriately omitted, substituted, or added to the various examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functions, or structures and functions other than those described herein. It should be understood that any aspect of this disclosure disclosed herein may be embodied by one or more elements of the claims.

[0036] While some teachings of this disclosure are illustrated using dynamic random access memory (DRAM) devices as example memory devices, these teachings are applicable to other fields, such as other volatile memory devices (e.g., static RAM (SRAM), synchronous SRAM (SDRAM), graphics DRAM (GDRAM), etc.). Furthermore, although some teachings of this disclosure are illustrated in the context of a system-on-a-chip (SoC), these teachings are also applicable to any suitable computing device utilizing memory. Therefore, the disclosed teachings should not be construed as limiting them to DRAM devices or SoCs or the illustrated embodiments. The illustrated embodiments are merely tools for describing and illustrating examples of the teachings of the invention disclosed herein.

[0037] Figure 1 Example components and interconnects coupled to volatile memory 124 (e.g., DRAM) in a system-on-a-chip (SoC) 100 suitable for implementing various aspects of this disclosure are shown. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may operate independently of the others. The processors 102, 104, 106, 108 may be organized very close to each other (e.g., on a single substrate, die, integrated chip, etc.) such that they can operate at a frequency / clock rate much higher than the frequency / clock frequency at which signals leave the chip. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails) and more coordinated cooperation between cores.

[0038] Processors 102, 104, 106, and 108 can be interconnected to memory controller 114 and other system components (not shown) via interconnect / bus module 122, which may include a reconfigurable gate array and / or implement a bus architecture (e.g., CoreConnect, Advanced Microcontroller Bus Architecture (AMBA), etc.). Communication can also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0039] Memory controller 114 may include a dedicated hardware module configured to receive various memory transactions from one or more hosts and to address and transfer memory transactions to memory 124. The multiple host devices may include one or more processors of processors 102, 104, 106, 108, and / or applications operating on processors 102, 104, 106, 108. Memory controller 114 may also manage the maintenance of memory 124, such as scheduling and / or initiating refresh cycles, and, as described herein, clearing contents (e.g., data and / or code) commands. In some examples, memory controller 114 may include one or more processors configured to perform the operations disclosed herein. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. The memory 124 and the memory controller 114 may be on-chip components of the SoC 100 (e.g., on a substrate, die, integrated chip, etc.); however, it should be noted that in some examples, one or more of the memory 124 and the memory controller 114 may be located off-chip.

[0040] Memory 124 is a computer-readable storage medium having an interface to processors 102, 104, 106, and 108 via bus module 122. As discussed, memory 124 may be an on-chip component, or alternatively (as shown) an off-chip component. Memory 124 may provide volatile memory, such as DRAM, for processors 102, 104, 106, 108, and / or other functional aspects of SoC 100. As shown, memory controller 114 includes ECC module 130. ECC module 130 is configured to implement ECC logic for detecting and correcting errors in memory 124, as discussed and known in the art. In some aspects, ECC module 130 is configured to execute ECC logic in-line.

[0041] Memory 124 may also include one or more memory ranks 134 and a hierarchy of multiple memory banks 132a-132j (collectively referred to as bank 132) within each memory rank 134. For example, memory 124 may include multiple memory ranks, where each memory rank includes multiple internal bank structures. In some examples, each bank structure may include multiple memory pages or "rows". Typically, at a given time, one row of memory is accessible on each bank. Each bank in the bank 132 of a given memory rank 134 may share a bus (not shown) for reading / writing data. Memory controller 114 may support simultaneous operation of different memory ranks 134 and banks 132 that can be accessed independently. Because each bank 132 acts as an independent entity, bank 132 can serve multiple memory requests in parallel, thereby providing bank-level parallelism.

[0042] Figure 2 Example components and interconnects in a SoC 100 suitable for implementing various aspects of this disclosure are shown. (As...) Figure 2 As shown, the memory controller 114 includes an ECC module 130. The ECC module 130 includes an ECC generator 205 and an ECC checker / corrector 210. In some aspects, when the ECC module operates in normal mode, the ECC generator 205 is configured to receive data to be written by, for example, the memory controller 114 to one or more unit banks 132. When the payload data is written to memory 114 (e.g., in unit banks 132), the ECC generator 205 can generate check bits (e.g., ECC parity bits) to correct errors in the received payload data. These generated parity bits are also written to memory 124, in the same or different unit banks 132 as the payload data. The ECC generator 205 or the memory controller 114 is directly configured to write data to unit banks 132, and the ECC generator 205 is also configured to write the generated check bits corresponding to the data in the unit banks(s) 132.

[0043] When a read command for stored data is received (e.g., from memory controller 114), ECC checker / corrector 210 is configured to read the stored data and corresponding parity bits from cell memory 132. ECC checker / corrector 210 is also configured to use the parity bits to check (e.g., using a known ECC procedure) whether the read data contains any errors. If the read data contains any errors, ECC checker / corrector 210 is further configured to use the parity bits to correct (e.g., using a known ECC procedure) the data. ECC checker / corrector 210 then passes the data (e.g., checked / corrected data) to memory controller 114 for delivery to the appropriate components.

[0044] As discussed, in the case of in-line ECC, the data to be stored in memory 124, along with the corresponding ECC data, is transferred to memory 124 for storage of both. However, before using in-line ECC, memory 124 must first be initialized to enable in-line ECC. That is, each cell of memory 124 that needs to store both the data and the ECC data needs to be set to zero.

[0045] Figure 3 This is a block diagram illustrating a high-level example of a DRAM memory system 300 according to various aspects described herein. As discussed, the memory controller (e.g., Figure 1 The memory controller 114) communicates with the memory (e.g., memory controller 114) via an interface. Figure 1 The memory 124 communicates with the memory bank 124. In this example, the memory 124 includes multiple memory columns (collectively referred to as memory columns 134). Each memory column 134 may include one or more sets of memory banks (e.g., memory banks 124, memory banks 13 ... Figure 1 Storage units 132a-132j).

[0046] Each memory bank 132 may include an array of cells 304 organized in rows and columns. In some examples, multiple memory cells 304 associated with memory bank 132 may be organized or arranged in rows and columns, wherein each row of memory cells is associated with at least one memory cell 302 and each column of memory cells is associated with at least one memory cell 304. Each memory cell may be connected to or coupled to an associated sense amplifier 302. Specifically, each row of memory cells may share a common word line (WL), while each column may share a common bit line (BL), wherein the memory cell associated with each column may be coupled to a corresponding sense amplifier 302. Each DRAM cell may include two components: 1) a capacitor 308 that stores one bit of data / code as charge, and 2) an access transistor 306 that connects the capacitor 308 to the BL (e.g., implemented as a wire), which is shared by the corresponding column cell 304. The access transistor 306 is controlled by the WL (e.g., implemented as a wire), which is shared by the corresponding row cell 304. When the voltage of WL rises to, for example, the power supply voltage, the corresponding row cell becomes connected to BL, thereby allowing content (e.g., data or code) to be read from or written to the connected row cell 304. Each column cell 304 shares a sense amplifier 302 configured to read or write content on BL.

[0047] Each cell 304's capacitor 308 is configured to store one bit of data as charge. Over time, the capacitor 308 loses its charge, causing the stored data to change. As a result, the memory controller 114 performs a refresh operation that periodically restores the charge in the cell 304 to maintain data integrity. Each cell 304 must be refreshed periodically at each refresh interval, depending on the DRAM type (e.g., Low Power Double Data Rate Type 4 (LPDDR4), LPDDR5, etc.). The refresh operation is initiated by a refresh command issued by the memory controller 114. Typically, there are two main refresh operations in modern DRAM systems: all-bank (AB) refresh (or column-level refresh) and per-bank (PB) refresh.

[0048] The AB refresh command can operate by simultaneously refreshing one or more rows of all banks in a memory column of memory 124. Therefore, this causes each bank 132 within memory column 134 to be unavailable to serve memory requests until the refresh command is complete. The PB refresh command can operate by refreshing multiple rows in a single bank 132 at a time. This allows the bank to be accessed while another bank 132 in the same memory column 134 is refreshed. The following describes aspects of clear content commands based on the AB refresh command.

[0049] Figure 4 This illustrates an example BL readout amplifier 400 (e.g., Figure 3 A schematic diagram of the readout amplifier 302 is shown. It should be noted that... Figure 4 The readout amplifier is used as a general example for describing and illustrating various aspects of the teachings disclosed herein. Therefore, while the readout amplifier 400 shown can be used in the disclosed implementations, it is understood that readout amplifiers of different forms and configurations can also be used. The general operation of the BL readout amplifier 400 is described below.

[0050] Initially, the BL 402 is pre-charged to a defined voltage (e.g., half of the internal power supply voltage VDD). When the memory controller (e.g., Figure 1 The memory controller 114) sends data to the memory (e.g., Figure 1 When the memory 124 issues a read command, the memory controller 114 activates the control signals RTO 406 and SB 408 of the sense amplifier 400, and the charged cell capacitor (e.g., Figure 3 A charge-sharing operation occurs between capacitor 308 and pre-charged BL 402, resulting in a small voltage difference between BL 402 and reference BL (BLB 404). This voltage difference is amplified by sense amplifier 400 according to the polarity of the stored content, and then the amplified voltage is transmitted to output data buffer.

[0051] For example, if the cell capacitor 308 is at a low voltage (e.g., the content stored in the cell is binary 0), the potential of BL 402 connected to capacitor 308 becomes lower than the pre-charge voltage potential, and the potential of BLB 404 remains at the pre-charge voltage potential, thereby creating a potential difference between the two bit lines.

[0052] However, if both BL 402 and BLB 404 are grounded (e.g., both BL 402 and BLB 404 are bonded to SB408), then the corresponding capacitor 308 is grounded, and any content stored on that capacitor 308 is cleared. Therefore, according to some aspects, the memory controller 114 can receive and execute a clear content command by grounding the BL 402 and BLB 404 lines of the sense amplifier 400.

[0053] In one example, the memory controller 114 can be controlled from the processor (e.g., Figure 1 The CPU 102 receives a clear content command. The clear content command is configured to cause the memory controller 114 to activate one or more switches (e.g., transistors) of the read amplifier 400 to clear content from one or more memory cells (e.g., memory cells) of one or more cell banks 132. Figure 3The memory cell 304) is cleared of its contents. The clear contents command may include an indicator configured to identify one or more memory cells 304 to be cleared. For example, the indicator may identify a set of memory banks 132 and a row of cells 304 within that set of memory banks 132 to be cleared. In such an example, the clear contents command may simultaneously clear the identified row in each of the identified memory banks 132 within the identified set of memory banks 132.

[0054] In response to receiving a clear content command, memory controller 114 may activate one or more switches of each sense amplifier 400 corresponding to one or more memory cells 304. For example, in one or more switches, a first switch may be coupled between a first bit line (e.g., BL 402) of a corresponding column of memory cells and ground, and a second switch may be coupled between a second bit line (e.g., BLB404) associated with a corresponding column of memory cells 304 and ground. Thus, by activating the first and second switches, the first and second bit lines are grounded, thereby clearing any content of the corresponding memory cell 304. The clear content command may be issued in response to the startup of the device containing memory 114, or to a status error or transient error detected in memory 124 (e.g., by one of processors 102, 104, 106, 108, or memory controller 114).

[0055] Example technology for implementing a command to clear content from a command address.

[0056] The examples described herein provide techniques and methods for implementing a clear content command to clear memory cells in memory 124. In some aspects, a single clear content command can clear the same row of each of multiple memory banks. In some examples, the clear content command is executed by memory controller 114 and is configured to activate one or more switches (e.g., transistors) in sense amplifier 400 to ground BL 402 and BLB 404. By grounding both BL402 and BLB 404, any memory content of the corresponding cell 304 is cleared (e.g., the cell is set to 0 volts).

[0057] In some aspects, the memory controller 114 receives a clear contents command via a command address (CA) bus. In some examples, the clear contents command can be encoded depending on the type of memory 124. For example, if memory 124 is of type LPDDR4, the clear contents command can be encoded as a two-phase single data rate (SDR) command. In some examples, if memory 124 is of type LPDDR5, the clear contents command can be encoded as a two-phase double data rate (DDR) command. In some subsequent examples, a first stage of the clear contents command includes a first bit sequence, and a second stage of the clear contents command includes a second bit sequence complementary to the first bit sequence.

[0058] Figure 5A This is a first block diagram illustrating an example CA encoding of the Clear Content command 502. It should be understood that the command value shown is an example and can be changed to different values. For example, the Clear Content command 502 may include a single-stage command, and the signaling on each bit of the CA bus can be set to any suitable complementary or non-complementary configuration. Furthermore, the number of bits used to encode the Clear Content command 502 may include more or fewer bits to suit any suitable bit size of the CA bus.

[0059] In this example, the clear content command 502 is a six-bit SDR two-stage command transmitted via a six-bit CA bus. In this example, the first stage 504 is a low-high-low-high-low-high combination of bits transmitted on the first rising clock edge (R1). The second stage 506 is a high-low-high-low-high-low combination of bits transmitted on the second rising clock edge (R2) (e.g., a rising clock edge after R1). That is, the first-stage command is received by the memory controller 114 before the second stage of the command, where the second stage of the command is complementary to the first stage. Therefore, the illustrated two-stage command is a complementary command format. The complementary command format can provide additional protection against transient errors on the CA bus by alternating the signal between low and high for each bit in the successive stages of the command.

[0060] Figure 5B This is a second block diagram illustrating an example CA encoding of the Clear Content command 522. It should be understood that the command value shown is an example and can be changed to different values. For example, the Clear Content command 522 may include a single-stage command, and the signaling on each bit of the CA bus can be set to any appropriate complementary or non-complementary configuration. Furthermore, the number of bits used to encode the Clear Content command 522 can be increased or decreased to accommodate any bit size of the CA bus.

[0061] In this example, the clear content command 522 is a six-bit DDR two-stage command transmitted via a six-bit CA bus. In this example, the first stage 524 is a low-low-low-high-high combination of bits transmitted on the first rising clock edge (R1). The second stage 526 is a high-high-high-low-low-low combination of bits transmitted on the first falling clock edge (F2) (e.g., the falling clock edge immediately following R1). That is, the first-stage command is received by the memory controller 114 before the second stage of the command. This supplementary command format can provide additional protection against transient errors on the CA bus.

[0062] Example technology for implementing commands to write clear contents to a mode register.

[0063] In some examples, a clear command can be written to the mode register. The memory controller 114 can then read the mode register at periodic intervals and execute the clear command. For example, the application or processor issuing the command might need to write a specific multi-bit sequence (e.g., 0xA5) into the register. Once the memory controller 114 has read and executed the clear command, it can clear the mode register.

[0064] Figure 6 This is a flowchart illustrating an example procedure 600 for executing a clear content command in the mode register. Initially, the memory controller 114 may periodically / non-periodically check the contents of the mode register. In block 605, the memory controller 114 determines whether a clear content command has been written to the register. If no command has been written to the register, the memory controller 114 may wait until the next periodic time interval to check the register, or until it receives notification of new contents in the mode register.

[0065] If a clear content command has been written to the mode register, then in box 610, the memory controller 114 can determine whether the clear content command has been executed. In some examples, the memory controller 114 can determine whether the rows corresponding to the clear content command have been cleared in all memory banks. If the clear content command has not been executed, process 600 can proceed to box 615, where the memory controller 114 executes the clear content command. If the clear content command has been executed, process 600 can proceed to box 620, where the memory controller 114 clears the mode register.

[0066] It should be noted that, Figure 5A and Figure 5B In the two examples shown, the memory controller 114 can execute a clear content command upon receiving a command via the CA bus. However, in Figure 6In this configuration, the memory controller 114 may not need to immediately execute the clear command. For example, the memory controller 114 may only periodically check the contents of the mode register. It should also be noted that the memory controller 114 can operate normally while the mode register is being written to. This may be a preferred method for transmitting clear commands if the CA bus is relatively busy.

[0067] As discussed, upon receiving a clear content command, the memory controller 114 can execute the command by activating one or more switches of the sense amplifier of the memory 124 to ground BL 402 and BLB 404, and simultaneously clear the contents of each memory cell in a row of memory banks 132 for all memory banks 132. As previously mentioned, the sense amplifier 400 can have many configurations relative to... Figure 4 Those shown have fewer or more components.

[0068] For example, Figure 7 It shows relative to Figure 4 A schematic diagram of an example sense amplifier 700 with two additional switches 710, 712 is provided. In this example, BL 702 and BLB 704 are coupled to SB 708 (e.g., ground) via the first switch 710 and the second switch 712. Therefore, in order to execute a clear content command, the memory controller 114 can use a clear command signal (e.g., in the...) Figure 7 The signal is indicated by "CB" or "C" to activate one of the switches at its gate, thereby grounding BL702 or BLB 704 and clearing the corresponding memory cell. For example, it may be necessary to enable only one transistor (e.g., the transistor's gate is activated). Here, when the memory cell is driving BL 702, the first switch 710 corresponding to BL702 driven by the memory cell must be activated (e.g., the clear command signal "C" is activated to clear the memory cell). BLB is then used as a reference level line for the sense amplifier 700. Alternatively, when the memory cell is driving BLB 704, the clear command signal "CB" is activated to clear the memory cell.

[0069] exist Figure 7 In the example, the first switch 710 and the second switch 712 may be switches already present on the readout amplifier 700 for purposes unrelated to the clear content command. In this case, the switches can be reused for the execution of the clear content command. In some examples, combinations of switches already present on the readout amplifier can be reused for the execution of the clear content command.

[0070] Figure 8This is a schematic diagram illustrating another example of a sense amplifier 800 with two additional switches suitable for implementing various aspects of this disclosure. As discussed, many different forms of sense amplifiers can be found, each including more or fewer components or different configurations. For example, Figure 8 The 800 sense amplifier includes a ratio Figure 7 The 700 readout amplifier has more components.

[0071] In this example, the first memory cell 304A is coupled to a bit line (BL) and a first word line (word line A) of the sense amplifier 800. The BLB of the sense amplifier 800 is also coupled to a second word line (word line B). The sense amplifier 800 is connected to two bit lines (BL and BLB), each connected to a memory cell array including the first memory cell 304A and the second memory cell 304B. As discussed, the sense amplifier 800 can sense voltage changes in the active BL (e.g., activated by word line A) in the bit lines and amplify these voltage changes to generate output data. In this example, the sense amplifier 800 receives an isolation signal (ISO) configured to cause the sense amplifier to perform a memory refresh operation. Similarly, the sense amplifier 800 can sense voltage changes in the active BLB (e.g., activated by word line B) in the bit lines.

[0072] Here, the first switch 810 is coupled between the first ISO line and ground (e.g., SB), and the second switch 812 is coupled between the second ISO line and ground. Both the first switch 810 and the second switch 812 are configured to receive a clear command from the memory controller 114. In this example, the clear command (e.g., "C" or "CB") can activate the corresponding gate of the first or second switch and force BL or BLB to ground during a refresh cycle (e.g., when the ISO signal activates the first and second ISO lines), which forces the first memory cell 304 or the second memory cell 304B (and any other memory cells in the memory cell array associated with the first memory cell 304 or the second memory cell 304B) to ground, thereby clearing the memory cell. Therefore, in this particular example, the refresh command of the sense amplifier 800 can be reused as a clear command, where an additional transistor is added for each line in the sense amplifier 800.

[0073] Figure 9 This is a flowchart illustrating example operation 900 for clearing contents stored in the memory of an electronic device according to certain aspects of this disclosure. For example, Figure 9 The operation steps can be controlled by the memory controller (e.g., Figure 1 The memory controller 114 or another suitable circuit shall perform this operation.

[0074] Operation 900 begins at step 905, receiving a clear content command configured to clear the contents of a first set of memory cells stored in a plurality of memory cells of a plurality of memory banks.

[0075] Operation 900 can continue in step 910, in response to the clear content command, activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells, the first switch being coupled between the first bit line of the corresponding memory cell and ground, and the second switch being coupled between the second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

[0076] In some respects, the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

[0077] In some respects, receiving a clear content command includes receiving a first-stage command before receiving a second-stage command.

[0078] In some respects, receiving a clear command includes reading a multi-bit command stored in the mode register.

[0079] In some respects, operation 900 includes clearing the mode register in response to determining that the contents of the first set of memory cells have been cleared.

[0080] In some respects, the memory is dynamic random access memory (DRAM) that utilizes in-line error correction codes (ECC).

[0081] In some respects, the controller receives commands in response to one or more of the following events: startup of the electronic device; a status error detected in memory; or a transient error detected in memory.

[0082] In some respects, the clear contents command includes an indicator configured to identify the first set of memory cells.

[0083] In some aspects, the first group of memory cells includes at least one row of memory cells in each of a plurality of memory banks. In some alternative aspects, the first group of memory cells includes two or more rows of memory cells in each memory bank. In some alternative aspects, the first group of memory cells includes all rows of memory cells in a memory bank. By addressing multiple rows or all rows in a memory bank, the memory cells of multiple rows or the entire memory bank are cleared simultaneously. In these examples, the voltage of the corresponding plurality of OR word lines is increased, for example, increased to the power supply voltage.

[0084] Figure 10 A processing system 1000 is shown, which may include operations configured to perform the techniques disclosed herein (such as...). Figure 6 and Figure 8 The processing system 1000 includes various components (e.g., corresponding to device plus functional components) of the operation shown. The processing system 1000 includes a processor 1004 coupled to a computer-readable medium / memory 1012 via a bus 1006. In some aspects, the computer-readable medium / memory 1012 is configured to store instructions (e.g., computer-executable code) that, when executed by the processor 1004, cause the processor 1004 to perform. Figure 6 and Figure 8 The operations shown, or other operations used to perform the various techniques for memory arbitration discussed in this article.

[0085] In some aspects, the computer-readable medium / memory 1012 stores code 1030 for receiving a clear content command configured to clear the contents of a first set of memory cells stored in a plurality of memory cells of a plurality of memory banks; code 1032 for activating a first switch and a second switch of a sense amplifier associated with each memory cell in the first set of memory cells in response to the clear content command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line; code 1034 for reading a mode register to determine whether a multi-bit command is stored in the mode register; code 1036 for determining whether a command stored in the mode register has been executed; and code 1038 for clearing the mode register when it is determined that a command stored in the mode register has been executed.

[0086] In some aspects, processor 1004 has circuitry configured to implement code stored in computer-readable medium / memory 1012. Processor 1004 includes: circuitry 1020 for receiving a clear content command configured to clear the contents of a first set of memory cells stored in a plurality of memory banks; circuitry 1022 for activating a first switch and a second switch of a sense amplifier associated with a corresponding memory cell in each of the first set of memory cells in response to the clear content command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first and second switches is configured to clear the corresponding memory cell by grounding the first and second bit lines; circuitry 1024 for reading a mode register to determine whether a multi-bit command is stored in the mode register; circuitry 1026 for determining whether a command stored in the mode register has been executed; and circuitry 1028 for clearing the mode register when it is determined that a command stored in the mode register has been executed.

[0087] Example

[0088] In a first aspect, a method for clearing contents stored on a memory of an electronic device, the memory including a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier, the method comprising: receiving a clear contents command configured to clear contents stored on the memory in a first group of memory cells in the plurality of memory banks; and in response to the clear contents command, activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells, the first switch being coupled between a first bit line of the corresponding memory cell and ground, the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

[0089] In the second aspect, either alone or in combination with the first aspect, the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

[0090] In the third aspect, receiving a clear content command, either alone or in combination with one or more of the first and second aspects, includes receiving a first-stage command before receiving a second-stage command.

[0091] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, receiving a clear content command includes a command to read multiple bits stored in the mode register.

[0092] In the fifth aspect, alone or in combination with one or more of the first to fourth aspects, it also includes clearing the mode register in response to determining that the contents of the first set of memory cells have been cleared.

[0093] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, the memory is a dynamic random access memory (DRAM) utilizing in-line error correction codes (ECC).

[0094] In the seventh aspect, either alone or in combination with one or more of the first through sixth aspects, the controller receives a command in response to one or more of the following events: startup of the electronic device; a status error detected in the memory; or a transient error detected in the memory.

[0095] In the eighth aspect, either alone or in combination with one or more of the first to seventh aspects, the clear content command includes an indicator configured to identify the first group of memory cells.

[0096] In the ninth aspect, either alone or in combination with one or more of the first to eighth aspects, the first group of memory cells includes at least one row of memory cells in each of the plurality of memory banks.

[0097] In a tenth aspect, an apparatus includes: a memory including a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier; and a processor communicatively coupled to the memory, the processor being configured to: receive a clear content command, the clear content command being configured to clear content stored on a first group of memory cells in the plurality of memory banks; and in response to the clear content command, activate a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells, the first switch being coupled between a first bit line of the corresponding memory cell and ground, the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

[0098] In the eleventh aspect, alone or in conjunction with the tenth aspect, the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

[0099] In the twelfth aspect, the processor configured to receive the clear content command, either alone or in combination with one or more aspects of the tenth and eleventh aspects, is also configured to receive the first-stage command before receiving the second-stage command.

[0100] In the thirteenth aspect, either alone or in combination with one or more aspects from the tenth to the twelfth aspects, the processor configured to receive a clear content command is also configured to read a multi-bit command stored in a mode register.

[0101] In the fourteenth aspect, alone or in combination with one or more of the tenth to thirteenth aspects, the processor is further configured to clear the mode register in response to determining that the contents of the first set of memory cells have been cleared.

[0102] In the fifteenth aspect, alone or in combination with one or more aspects from the tenth to the fourteenth aspects, the memory is a dynamic random access memory (DRAM) utilizing in-line error correction codes (ECC).

[0103] In the sixteenth aspect, alone or in combination with one or more of aspects ten through fifteen, the command is received in response to one or more of the following events: startup of the electronic device; a status error detected in the memory; or a transient error detected in the memory.

[0104] In the seventeenth aspect, alone or in combination with one or more of the tenth to sixteenth aspects, the clear content command includes an indicator configured to identify the first group of memory cells.

[0105] In the eighteenth aspect, alone or in combination with one or more aspects from the tenth to the seventeenth aspect, the first group of memory cells includes at least one row of memory cells in each of the plurality of memory banks.

[0106] In a nineteenth aspect, an apparatus configured to erase contents stored in a memory of an electronic device, the memory including a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier, the apparatus comprising: means for receiving a erase contents command configured to erase contents stored in a first group of memory cells in the plurality of memory banks; and means for activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells in response to the erase contents command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to erase the corresponding memory cell by grounding the first bit line and the second bit line.

[0107] In the twentieth aspect, alone or in conjunction with the nineteenth aspect, the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

[0108] In aspect 21, alone or in combination with one or more of aspects 19 and 20, the component for receiving the clear content command includes a component for receiving the first-stage command prior to the second-stage command.

[0109] In the twenty-second aspect, alone or in combination with one or more of aspects nineteen to twenty-one, the component for receiving a clear content command includes a component for reading a multi-bit command stored in a mode register.

[0110] In the twenty-third aspect, alone or in combination with one or more of the nineteenth to twenty-second aspects, it also includes means for clearing the mode register in response to determining that the contents of the first set of memory cells have been cleared.

[0111] In aspect 24, alone or in combination with one or more aspects from aspects 19 to 23, the memory is a dynamic random access memory (DRAM) utilizing in-line error correction codes (ECC).

[0112] In aspect twenty-five, alone or in combination with one or more of aspects nineteen through twenty-four, the command is received in response to one or more of the following events: device startup; a status error detected in memory; or a transient error detected in memory.

[0113] In the twenty-sixth aspect, alone or in combination with one or more of aspects nineteen through twenty-five, the clear content command includes an indicator configured to identify the first group of memory cells.

[0114] In the twenty-seventh aspect, alone or in combination with one or more aspects from the nineteenth to the twenty-sixth aspects, the first group of memory cells includes at least one row of memory cells in each of the plurality of memory banks.

[0115] In a twenty-eighth aspect, a non-transitory computer-readable storage medium stores instructions that, when executed by a processor of a device, cause the device to perform a method of erasing contents stored in a memory of an electronic device, the memory including a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier, the method comprising: receiving a erase contents command by the device, the erase contents command being configured to erase contents stored in a first group of memory cells in the plurality of memory banks; and activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells by the device in response to the erase contents command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to erase the corresponding memory cell by grounding the first bit line and the second bit line.

[0116] In aspect 29, alone or in combination with aspect 28, the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

[0117] In the thirtieth aspect, alone or in combination with one or more of the twenty-eighth and twenty-ninth aspects, receiving a clear content command includes receiving a first-stage command before receiving a second-stage command.

[0118] Other information

[0119] The above description is provided to enable those skilled in the art to practice the various embodiments described herein. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments. For example, changes can be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various examples may be appropriately omitted, substituted, or added to various processes or components. Furthermore, features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein can be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatuses or methods that can be practiced with structures, functions, or structures and functions other than those set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0120] As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as superior to the others.

[0121] As used herein, the phrase referring to a list of "at least one" items means any combination of these items, including a single member. For example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0122] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" can include calculating, computing, processing, deducing, investigating, searching (e.g., looking up data in a table, database, or other data structure), confirming, etc. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Additionally, "determine" can include resolving, selecting, recommending, establishing, etc.

[0123] The methods disclosed herein include one or more steps or actions for implementing the methods. Method steps and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims. Furthermore, the various operations of the above methods can be performed by any suitable component capable of performing the corresponding function. This component may include various hardware (one or more) hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, if the operations shown in the figures are present, these operations may have corresponding means plus functional components with similar numbering.

[0124] The various illustrative logic blocks, modules, and circuits described in this disclosure may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such construction.

[0125] The processing system can be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus can include any number of interconnect buses and bridges. The bus can link together various circuits, including processors, machine-readable media, and input / output devices. User interfaces (e.g., keyboards, displays, mice, joysticks, etc.) can also be coupled to the bus. The bus can also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and therefore will not be described further. The processor can be implemented using one or more general-purpose and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuit systems capable of executing software. Those skilled in the art will recognize how the above-described functions of the processing system can be optimally implemented according to the specific application and the overall design constraints imposed on the system as a whole.

[0126] If implemented in software, these functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Software should be interpreted broadly as instructions, data, or any combination thereof, whether referring to software, firmware, middleware, microcode, hardware description languages, or others. Computer-readable media includes computer storage media and communication media, such as any medium that facilitates the transfer of computer programs from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on the computer-readable storage medium. The computer-readable storage medium may be coupled to the processor, allowing the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. As an example, the computer-readable medium may include a transmission line, a data-modulated carrier wave, and / or a separate computer-readable storage medium containing instructions, all accessible to the processor via a bus interface. Alternatively or additionally, the computer-readable medium or any portion thereof may be integrated into the processor, such as caches and / or general-purpose register files. Examples of machine-readable storage media may include RAM (random access memory), flash memory, ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), registers, disks, optical disks, hard disks, or any other suitable storage media, or any combination thereof. Machine-readable media may be implemented in computer program products.

[0127] Software modules can include single or multiple instructions and can be distributed across several different code segments, different programs, and multiple storage media. Computer-readable media can include multiple software modules. A software module includes instructions that, when executed by a device such as a processor, cause the processing system to perform various functions. Software modules can include issue and receive modules. Each software module can reside in a single storage device or be distributed across multiple storage devices. For example, when a trigger event occurs, a software module can be loaded from a hard disk drive into RAM. During the execution of a software module, the processor can load some instructions from the set of instructions into a cache to improve access speed. Then, one or more cache lines can be loaded into a general-purpose register file for execution by the processor. When referring to the functionality of a software module, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

[0128] The following claims are not limited to the embodiments shown herein, but should be accorded the full scope consistent with the language of the claims. In a claim, unless otherwise specified, the singular form of an element means not "one and only one," but "one or more." Unless otherwise specified, the term "some" means one or more. No element of a claim shall be construed under 35 U.S.C. 112(f) unless the element is explicitly stated using the phrase "component for..." or, in the case of a method claim, the element is stated using the phrase "step for...". All structural and functional equivalents of elements known or to be known later by one of ordinary skill in the art throughout the various aspects described in this disclosure are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended as a donation to the public, whether or not such disclosure is expressly stated in the claims.

Claims

1. A method for erasing contents stored in a memory of an electronic device, the memory comprising a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier, the method comprising: Receive a content clearing command, the content clearing command being configured to clear the content stored in the memory in a first group of memory cells among the plurality of memory cells in the plurality of memory banks; as well as In response to the clear content command, a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells are activated. The first switch is coupled between the first bit line of the corresponding memory cell and ground, and the second switch is coupled between the second bit line of the corresponding memory cell and ground. Activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

2. The method of claim 1, wherein the content clearing command includes a first-stage command and a second-stage command, the first-stage command including a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

3. The method of claim 2, wherein receiving the clear content command includes receiving the first stage command before receiving the second stage command.

4. The method of claim 1, wherein receiving the clear content command includes reading a multi-bit command stored in the mode register.

5. The method according to claim 4, further comprising: The mode register is cleared in response to determining that the contents of the first set of memory cells have been cleared.

6. The method according to claim 1, wherein the memory is a dynamic random access memory (DRAM) utilizing in-line error correction code (ECC).

7. The method of claim 1, wherein the controller receives the command in response to an event including one or more of the following: The electronic device is started; A status error was detected in the memory; or A transient error was detected in the memory.

8. The method of claim 1, wherein the clear content command includes an indicator configured to identify the first set of memory cells.

9. The method of claim 1, wherein the first group of memory cells comprises at least one row of memory cells in each of the plurality of memory banks.

10. An apparatus comprising: The memory includes a plurality of memory banks, each of which has a plurality of memory cells arranged thereon, and each of the plurality of memory cells is coupled to an associated sense amplifier. as well as A processor, communicatively coupled to the memory, is configured to: Receive a clear content command, the clear content command being configured to clear the content stored in a first group of memory cells among the plurality of memory cells in the plurality of memory banks; as well as In response to the clear content command, a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells are activated. The first switch is coupled between the first bit line of the corresponding memory cell and ground, and the second switch is coupled between the second bit line of the corresponding memory cell and ground. Activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

11. The device of claim 10, wherein the content clearing command comprises a first-stage command and a second-stage command, the first-stage command comprising a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

12. The device of claim 11, wherein the processor configured to receive the clear content command is further configured to receive the first stage command before receiving the second stage command.

13. The device of claim 10, wherein the processor configured to receive the clear content command is further configured to read a multi-bit command stored in a mode register.

14. The device of claim 13, wherein the processor is further configured to clear the mode register in response to determining that the contents of the first set of memory cells have been cleared.

15. The device of claim 10, wherein the memory is a dynamic random access memory (DRAM) utilizing in-line error correction code (ECC).

16. The device of claim 10, wherein the command is received in response to an event including one or more of the following: The device is started; A status error was detected in the memory; or A transient error was detected in the memory.

17. The device of claim 10, wherein the clear content command includes an indicator configured to identify the first set of memory cells.

18. The device of claim 10, wherein the first group of memory cells comprises at least one row of memory cells in each of the plurality of memory banks.

19. An apparatus configured to erase contents stored in a memory of an electronic device, the memory comprising a plurality of memory banks, each of the plurality of memory banks having a plurality of memory cells disposed thereon, each of the plurality of memory cells being coupled to an associated sense amplifier, the apparatus comprising: A component for receiving a clear content command, the clear content command being configured to clear the content stored in a first group of memory cells among the plurality of memory cells of the plurality of storage banks; as well as Components for activating a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells in response to the clear content command, the first switch being coupled between a first bit line of the corresponding memory cell and ground, and the second switch being coupled between a second bit line of the corresponding memory cell and ground, wherein activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

20. The apparatus of claim 19, wherein the content clearing command comprises a first-stage command and a second-stage command, the first-stage command comprising a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

21. The apparatus of claim 20, wherein the component for receiving the clear content command includes a component for receiving the first stage command prior to the second stage command.

22. The apparatus of claim 19, wherein the component for receiving the clear content command includes a component for reading a multi-bit command stored in a mode register.

23. The apparatus of claim 22, further comprising means for clearing the mode register in response to determining that the contents of the first set of memory cells have been cleared.

24. The apparatus of claim 19, wherein the memory is a dynamic random access memory (DRAM) utilizing in-line error correction code (ECC).

25. The apparatus of claim 19, wherein the command is received in response to an event including one or more of the following: The device is activated; A status error was detected in the memory; or A transient error was detected in the memory.

26. The apparatus of claim 19, wherein the clear content command includes an indicator configured to identify the first set of memory cells.

27. The apparatus of claim 19, wherein the first group of memory cells comprises at least one row of memory cells in each of the plurality of memory banks.

28. A non-transitory computer-readable storage medium storing instructions, said instructions, when executed by a processor of a device, causing the device to perform a method of erasing contents stored in a memory of an electronic device, said memory comprising a plurality of memory banks, each of said plurality of memory banks having a plurality of memory cells arranged thereon, each of said plurality of memory cells being coupled to an associated sense amplifier, said method comprising: The device receives a clear content command, which is configured to clear the content stored in a first group of memory cells among the plurality of memory cells in the plurality of memory banks; as well as The device activates a first switch and a second switch of each sense amplifier associated with each memory cell in the first group of memory cells in response to the clear content command. The first switch is coupled between the first bit line of the corresponding memory cell and ground, and the second switch is coupled between the second bit line of the corresponding memory cell and ground. Activating the first switch and the second switch is configured to clear the corresponding memory cell by grounding the first bit line and the second bit line.

29. The non-transitory computer-readable storage medium of claim 28, wherein the erase content command comprises a first-stage command and a second-stage command, the first-stage command comprising a first bit sequence, and the second-stage command having a second bit sequence complementary to the first bit sequence.

30. The non-transitory computer-readable storage medium of claim 29, wherein receiving the clear content command includes receiving the first stage command before receiving the second stage command.

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