Reading multi-level memory cells

Abstract

This application relates to reading multi-level memory cells. The memory cells can be configured to store three or more logic states. The memory device can apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device can determine whether a first snapback event occurs based on applying the first read voltage and apply a second read voltage based on determining that the first snapback event fails to occur. The memory device can determine whether a second snapback event occurs and determine the logic state based on whether the first snapback event or the second snapback event occurs.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 039539, entitled "Reading a Multi-Level Memory Cell," filed June 29, 2021, by Robustelli et al., which claims priority to U.S. Patent Application No. 16 / 926,557, entitled "Reading a Multi-Level Memory Cell," filed July 10, 2020, by Robustelli et al., each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field involves reading multi-level memory cells. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power supply. FeRAM can achieve densities similar to volatile memory, but its non-volatile nature is attributed to the use of ferroelectric capacitors as storage devices.

[0006] Improving memory devices typically involves increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. It is desirable to store multiple bits of information in memory cells to increase data storage density without increasing the physical memory cell density. Summary of the Invention

[0007] Describe a method. The method may include: applying a first read voltage of a first polarity to a memory cell to determine logical states stored by the memory cell configured to store three or more logical states; determining whether a first backlash event occurs after the application of the first read voltage; applying a second read voltage of a second polarity to the memory cell based at least in part on the determination that the first backlash event did not occur; determining whether a second backlash event occurs after the application of the second read voltage; and determining the logical states stored by the memory cell based at least in part on the determination that either the first backlash event or the second backlash event occurred.

[0008] Another method is described. The method may include: applying a first read voltage having a first polarity and a first magnitude to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states; determining whether a first backlash event occurs after the application of the first read voltage; applying a second read voltage having the first polarity and a second magnitude to the memory cell, at least in part based on the determination that the first backlash event did not occur; determining whether a second backlash event occurs after the application of the second read voltage; applying a third read voltage having the first polarity and a third magnitude to the memory cell, at least in part based on the determination that the second backlash event did not occur; determining whether a third backlash event occurs after the application of the third read voltage; and determining the logic state stored by the memory cell, at least in part based on the determination that the first backlash event, the second backlash event, or the third backlash event occurred.

[0009] Describe a device. The device may include: a memory array including memory cells; and a control component coupled to the memory array, the control component being configured to cause the device to: apply a first read voltage having a first polarity to the memory cells to determine logical states stored by the memory cells configured to store three or more logical states; determine whether a first backlash event occurs after the first read voltage is applied; apply a second read voltage having a second polarity to the memory cells based at least in part on the determination that the first backlash event did not occur; determine whether a second backlash event occurs after the second read voltage is applied; and determine the logical states stored by the memory cells based at least in part on the determination that either the first backlash event or the second backlash event occurred.

[0010] Describing another device. The device may include: a memory array including memory cells; and a control component coupled to the memory array, the control component being configured to cause the device to: apply a first read voltage having a first polarity and a first magnitude to the memory cells to determine logical states stored by the memory cells configured to store three or more logical states; determine whether a first backlash event occurs after the first read voltage is applied; apply a second read voltage having the first polarity and a second magnitude to the memory cells, at least in part based on the determination that the first backlash event did not occur; determine whether a second backlash event occurs after the second read voltage is applied; apply a third read voltage having the first polarity and a third magnitude to the memory cells, at least in part based on the determination that the second backlash event did not occur; determine whether a third backlash event occurs after the third read voltage is applied; and determine the logical states stored by the memory cells, at least in part based on the determination that the first backlash event, the second backlash event, or the third backlash event occurred.

[0011] A non-transitory computer-readable medium storing code is described. The code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: apply a first read voltage of a first polarity to a memory cell to determine logical states stored by the memory cell, which is configured to store three or more logical states; determine whether a first pop-up event occurs after the application of the first read voltage; apply a second read voltage of a second polarity to the memory cell, at least in part based on the determination that the first pop-up event did not occur; determine whether a second pop-up event occurs after the application of the second read voltage; and determine the logical states stored by the memory cell, at least in part based on the determination that the second pop-up event occurred. Attached Figure Description

[0012] Figure 1 This describes an instance memory device that supports reading multi-level memory cells, as illustrated in the examples disclosed herein.

[0013] Figure 2 This describes an example of a memory array that supports reading multi-level memory cells, as illustrated in the examples disclosed herein.

[0014] Figure 3A The illustration shows an example of a diagram illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multi-level memory cells, as disclosed in this document.

[0015] Figure 3B This describes an example of a timing diagram supporting reading of multi-level memory cells, as disclosed in this document.

[0016] Figure 4A The illustration shows an example of a diagram illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multi-level memory cells, as disclosed in this document.

[0017] Figure 4B This document describes an example of a flowchart illustrating support for reading multi-level memory cells, as disclosed in the examples herein.

[0018] Figure 5A The illustration shows an example of a diagram illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multi-level memory cells, as disclosed in this document.

[0019] Figure 5B This document describes an example of a flowchart illustrating support for reading multi-level memory cells, as disclosed in the examples herein.

[0020] Figure 6A The illustration shows an example of a diagram illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multi-level memory cells, as disclosed in this document.

[0021] Figure 6B This document describes an example of a flowchart illustrating support for reading multi-level memory cells, as disclosed in the examples herein.

[0022] Figure 7 This describes an example of a timing diagram supporting reading of multi-level memory cells, as disclosed in this document.

[0023] Figure 8 A block diagram illustrating a memory device that supports reading multi-level memory cells, based on examples disclosed herein.

[0024] Figure 9 and 10The flowchart illustrates one or more methods for supporting the reading of multi-level memory cells, based on examples disclosed herein. Detailed Implementation

[0025] A self-select memory cell containing chalcogenide material can be an example of a multilevel cell configured to store three or more unique states. Thus, a single multilevel self-select memory cell can be configured to store more than one data bit. In some cases, the self-select memory cell can be selected by applying a bias voltage between the word line and the digital line. The logic state stored in the self-select memory cell can be based on the polarity of the programming pulse applied to the self-select memory cell. For some multilevel self-select memory cells, a programming pulse sequence comprising two pulses can be used to program one or more intermediate memory states to the self-select memory cell. The first pulse of the programming pulse sequence may have a first polarity and a first magnitude, and the second pulse of the programming pulse sequence may have a second polarity different from the first polarity and a second magnitude different from the first magnitude. After applying two pulses in the programming pulse sequence, the self-select memory cell can store an intermediate state representing two data bits (e.g., logic '01' or logic '10').

[0026] This invention describes apparatus, systems, and techniques for reading multi-level auto-select memory cells storing three or more states. To read one or more memory states of the auto-select memory cells, two or more read voltages are sequentially applied to the memory cells. For example, a first read voltage may be applied, and if the first read voltage does not cause a backflow event, a second read voltage may be applied to the memory cell as part of a read operation. In some instances, if the second read voltage does not cause a backflow event, a third read voltage may be applied to the memory cell as part of a read operation.

[0027] Some logical states that can be stored in a memory cell may be disturbed by the application of a read voltage (e.g., a first read voltage, a second read voltage, or a third read voltage). In such cases, the memory cell can be reprogrammed after the read operation. In some cases, different read schemes may use read voltages of different polarities to reduce the need for reprogramming operations after a read operation. Reading one or more memory states from a selected memory cell by sequentially applying two or more read voltages can result in less disturbance to the programmed state.

[0028] Originally in reference Figures 1 to 2Features of this disclosure are described in the background context of the memory array and system description. Features of this disclosure are described in the background context of diagrams, flowcharts, and timing diagrams illustrating the distribution of threshold voltages, as described with reference to Figures 3 to 7. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts relating to reading multi-level memory cells, as described with reference to... Figures 8 to 10 describe.

[0029] Figure 1 This describes an example memory device 100 that supports reading multi-level memory cells, as disclosed herein. The memory device 100 may also be referred to as an electronic memory device. In some cases, components and features of the memory device 100 are shown to illustrate their functional interrelationships without specifying their actual physical location within the memory device 100. Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array. The memory array includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some instances, memory cells 105 may be configured to store more than two logic states. In some instances, memory cells 105 may include self-selectable memory cells. Although indicated by numeric indicators... Figure 1 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0030] 3D memory arrays can comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or generated on a single die or substrate, which in turn can reduce manufacturing costs or increase the performance of the memory device, or both. Figure 1 The example depicted shows a memory array comprising two levels of memory cells 105 and thus can be considered a 3D memory array; however, the number of levels is not limited to two. Each level can be aligned or positioned such that the memory cells 105 can be aligned with each other across each level (completely, overlapping, or approximately), thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may contain multiple self-selecting memory cells laid on top of each other while sharing access lines, as explained below. In some cases, the self-selecting memory cells may be multi-level self-selecting memory cells configured to use multi-level storage techniques to store more than one data bit.

[0031] In some instances, each row of memory cells 105 is connected to access lines 110, and each column of memory cells 105 is connected to bit lines 115. Access lines 110 and bit lines 115 can be substantially perpendicular to each other and can create an array of memory cells. For example... Figure 1 As shown, two memory cells 105 in a memory cell stack 145 can share a common conductive line (e.g., bit line 115). That is, bit line 115 can electronically communicate with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible; for example, a third material can share access line 110 with the lower material. Generally, a memory cell 105 can be located at the intersection of two conductive lines (e.g., access line 110 and bit line 115). This intersection point can be referred to as the address of the memory cell. The target memory cell 105 can be a memory cell 105 located at the intersection of the energized access line 110 and bit line 115; that is, the access line 110 and bit line 115 can be energized to read or write to the memory cell 105 at its intersection point. Other memory cells 105 that communicate electronically with the same access line 110 or bit line 115 (e.g., connected to the same access line 110 or bit line 115) may be referred to as unlabeled memory cells 105.

[0032] As discussed above, electrodes may be coupled to memory cell 105 and access line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may include traces, wires, conductive lines, conductive materials, or the like that providing a conductive path between elements or components of memory device 100. In some instances, memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to access line 110 and the other side of the first electrode may be coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to bit line 115 and the other side of the second electrode may be coupled to the chalcogenide material. The first electrode and the second electrode may be made of the same material (e.g., carbon) or different materials.

[0033] Operations (e.g., read and write) can be performed on memory cell 105 by activating or selecting access line 110 and bit line 115. In some instances, access line 110 may also be referred to as word line 110, and bit line 115 may also be referred to as bit line 115. References to word lines and bit lines or the like are interchangeable without loss of understanding or operation. Activating or selecting word line 110 or bit line 115 may involve applying a voltage to the respective line. Word line 110 and bit line 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors, or other conductive materials, alloys, compounds, or the like.

[0034] Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 can receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 can receive a column address from memory controller 140 and activate the appropriate digital line 115. Therefore, by activating word line 110 and digital line 115, memory cell 105 at their intersection can be accessed.

[0035] After access, the stored state of memory cell 105 can be determined by reading or sensing memory cell 105 through sensing component 125. For example, a voltage can be applied to memory cell 105 (using corresponding word line 110 and bit line 115), and the presence of the resulting current may depend on the applied voltage and threshold voltage of memory cell 105. In some cases, more than one voltage may be applied. Furthermore, if the applied voltage does not result in current flow, other voltages may be applied until current is detected by sensing component 125. By evaluating the voltage that causes current flow, the stored logic state of memory cell 105 can be determined. In some cases, the voltage may be ramped up in magnitude until current flow is detected. In other cases, predetermined voltages may be applied sequentially until current is detected. Similarly, current may be applied to memory cell 105, and the magnitude of the voltage that produces the current may depend on the resistance or threshold voltage of memory cell 105.

[0036] Sensing component 125 may include various transistors or amplifiers to detect and amplify differences in signals (this may be referred to as latching). The detected logic state of memory unit 105 can then be output as input / output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Sensing component can be associated with column decoder or row decoder without losing its functional purpose.

[0037] Memory cell 105 can be set or written by similarly activating the associated word line 110 and digital line 115, and at least one logic value can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data to be written to memory cell 105 (for example, input / output 135). In the case of a self-selecting memory cell containing chalcogenide material, data can be stored by applying a programming sequence comprising a first pulse having a first polarity and a second pulse having a second polarity. The programming pulses can have various shapes. See below for reference. Figure 3A , 3BThis process is discussed in more detail in sections 4A, 4B, 5A, and 5B.

[0038] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cell 105 through various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals to activate the desired word line 110 and digital line 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0039] The memory controller 140 can be configured to perform write operations on programmable self-selecting memory cells having more than two states. For example, the memory controller 140 can be configured to program self-selecting memory cells having four states (e.g., logic '00', logic '01', logic '10', or logic '11'). In some cases, two or more read voltages can be sequentially applied to read one or more memory states of the self-selecting memory cell. A first read voltage can be applied with a first polarity and a second read voltage can be applied with a second polarity. In some cases, the first and second polarities can be the same. In other instances, the first and second polarities can be different.

[0040] For example, memory controller 140 may apply a first read voltage to a selectable memory cell to determine the logic state stored by the selectable memory cell configured to store three or more logic states. Next, memory controller 140 may determine whether a backlash event has occurred after the application of the first read voltage. For example, memory controller 140 may determine that a backlash event has not occurred. In such a case, memory controller 140 may then apply a second read voltage to the selectable memory cell. Memory controller 140 may determine whether a backlash event has occurred after the application of the second read voltage and determine the logic state stored by the memory cell based on whether either of the two backlash events has occurred.

[0041] In some instances, the memory controller 140 may determine that a backlash event failed after the second read voltage was applied. In such cases, the memory controller 140 may then apply a third read voltage to the self-selected memory cell. The memory controller 140 may determine whether a backlash event occurred after the third read voltage was applied and determine the logic state stored in the memory cell based on whether any of the three backlash events occurred.

[0042] Figure 2This describes an example of a memory array 200 that supports reading multi-level memory cells, as disclosed in the examples herein. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory array. Memory array 200 may include a first memory cell array or stack 205 positioned above substrate 204 and a second memory cell array or stack 210 located on top of the first array or stack 205. Memory array 200 may also include word lines 110-a and 110-b, and bit line 115-a, which may be as described in reference... Figure 1 Examples of word line 110 and bit line 115 are described. The memory cells of the first stack 205 and the second stack 210 may each have one or more self-selectable memory cells. Although the numerical indicators are used to indicate the inclusion of... Figure 2 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0043] The selectable memory cell of the first stack 205 may include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the selectable memory cell of the second stack 210 may include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, the selectable memory cells of the first stack 205 and the second stack 210 may have a common conductive line, such that corresponding selectable memory cells of each stack 205 and 210 can share a common conductive line, as shown in the reference. Figure 1 The bit line 115 or word line 110 is described. For example, the first electrode 215-b of the second stack 210 and the second electrode 225-a of the first stack 205 can be coupled to the bit line 115-a, such that the bit line 115-a is shared by vertically adjacent self-select memory cells.

[0044] The architecture of memory array 200 can be referred to as a cross-point architecture, in which memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 2 The explanation is as follows. Compared to other memory architectures, this crossover architecture can provide relatively high-density data storage at a lower production cost. For example, the crossover architecture can have a smaller area and therefore increased memory cell density compared to other architectures. For example, compared to architectures with 6F... 2 Other architectures with smaller memory cell areas (e.g., architectures with three-terminal selection components) may have a 4F [cell area]. 2 The memory cell area, where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as the selection component for each memory cell and can have a larger memory cell area compared to a cross-point architecture.

[0045] In some architectures (not shown), multiple word lines may be formed on a parallel plane or layer parallel to the substrate. The multiple word lines may be configured to include multiple vias to allow multiple bit lines to be formed orthogonally to the plane of the word lines, such that each of the multiple bit lines penetrates a set of vertical alignment vias (e.g., the bit lines are positioned perpendicular to the plane of the word lines and the horizontal substrate). Memory cells containing storage elements (e.g., self-selecting memory cells containing chalcogenide material) may be formed at the intersection of the word lines and bit lines (e.g., the space between the word lines and bit lines in the set of vertical alignment vias). (Refer to the above) Figure 1 A similar approach can be described where a memory cell (e.g., a self-selecting memory cell containing chalcogenide material) can be operated (e.g., read and / or programmed) by selecting the appropriate access line (e.g., bit line and word line) and applying a voltage or current pulse.

[0046] Although Figure 2 The examples show two memory stacks, but other configurations are possible. In some instances, a single memory stack of self-selecting memory cells (which may be referred to as a two-dimensional memory) may be constructed on top of substrate 204. In some instances, three or four memory stacks of memory cells may be configured in a manner similar to that in a three-dimensional cross-point architecture. In some instances, one or more of the memory stacks may contain self-selecting memory cells comprising chalcogenide material 220. Chalcogenide material 220 may (for example) comprise chalcogenide glasses, such as (for example) alloys of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may comprise silicon (Si), and this chalcogenide material may be referred to as SiSAG alloys. In some instances, chalcogenide glasses may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0047] In some instances, a selectable memory cell containing chalcogenide material 220 can be read by applying two or more read voltages to the selectable memory cell using bit line 115 and word line 110. In one instance, a controller associated with the selectable memory cell can apply a first read voltage, and if the first read voltage does not cause a backlash event, a second read voltage can be applied to the selectable memory cell as part of a read operation. In some instances, if the second read voltage does not cause a backlash event, a third read voltage can be applied to the selectable memory cell as part of a read operation.

[0048] Figure 3AThe illustration shows an example of diagram 300 illustrating the distribution of threshold voltages for a self-selecting memory cell that supports reading multi-level memory cells, as disclosed herein. The multi-level self-selecting memory cell can be configured to store logic states representing multiple data bits using multi-level memory technology. The voltage distribution depicts the readable logic states.

[0049] The self-selectable memory unit may include, as referenced Figure 1 and 2 The chalcogenide material is described. The threshold voltage distribution can represent a multi-level cell programming scheme for storing at least two bits per cell. Figure 3A In some instances, distribution 305 may represent logic state 00, distribution 310 may represent logic state 01, distribution 315 may represent logic state 10, and distribution 320 may represent logic state 11. In some cases, distributions 305, 310, 315, and 320 may represent the intermediate voltage value (e.g., a normal quantile) of the voltage distribution corresponding to each logic state. For example, distribution 305 may represent the normal quantile of the distribution corresponding to logic state 00. Similarly, distribution 310 may represent the normal quantile of the distribution corresponding to logic state 01, distribution 315 may represent the normal quantile of the distribution corresponding to logic state 10, and distribution 320 may represent the normal quantile of the distribution corresponding to logic state 11. In some instances, two distributions may have overlapping portions, and therefore there may not be a clear separation between the two distributions. In some instances, each distribution may not be symmetrical about its midpoint. In some instances, each distribution may represent a different range of voltage values. In some cases, two or more pulses can be used to write the logic state to the auto-select memory cell. In other cases, two or more pulses can be used to read the logic state from the auto-select memory cell.

[0050] Figure 3BThis section describes an example of timing diagram 350 supporting reading of multi-level memory cells, as disclosed herein. Timing diagram 350 shows a first pulse sequence 355 for programming logic state '11' (e.g., distribution 320) and a second pulse sequence 360 ​​for programming intermediate logic state '01' (e.g., distribution 310). Pulse sequences 355 and 360 can be used to program multi-level auto-select memory cells. Specifically, the second pulse sequence 360 ​​can be configured to store intermediate states in the auto-select memory device. Diagram 350 plots the magnitude of the current applied to one or more pulses (y-axis) relative to time (x-axis) to the auto-select memory cell. In some cases, the voltage applied during programming the auto-select memory cell may be independent of the energy associated with the programming pulse. Therefore, the voltage can be selected in a manner sufficient to select the auto-select memory cell regardless of its current state. In some cases, if a preset bias is insufficient to select the high voltage associated with the auto-select memory cell, the bias associated with the programming pulse can be increased. In some instances, once the self-selective memory cell is activated, the bias voltage across the active material of the self-selective memory cell can be less than the external bias voltage. In such cases, the bias voltage may depend on one or more properties of the active material. Therefore, the pulse energy can be controlled for a given pulse duration by controlling the current flowing through the self-selective memory cell. Static or dynamic configurations can be used to control the current flowing through the self-selective memory cell. In some cases, clamping devices or current mirrors can be used to control the current flowing in the self-selective memory cell.

[0051] Upon receiving the first pulse sequence 355, a self-selecting memory cell with a chalcogenide material can be programmed using a first logic state. The first pulse sequence 355 may include a pulse 365-a having a magnitude corresponding to I1 and a first polarity. The pulse 365-a can be applied for a duration T1 during which a fixed amplitude corresponding to I1 is maintained. In some instances, the duration T1 may range from a few nanoseconds (nsec) to microseconds (μsec) (e.g., 10 nsec to 1 μsec). Upon receiving the pulse 365-a, a self-selecting memory cell can be programmed using logic state 11. Using the first pulse sequence, regardless of the current state of the memory cell, the new state of the memory cell will be the logic state associated with distribution 320. Figure 3A Arrow 325 indicates a self-selected memory cell from distribution 305 to distribution 320 based on receiving the first pulse 365-a during a write operation. In other instances, pulse 365-a would cause a self-selected memory cell to move from distribution 310 or distribution 315 to distribution 320.

[0052] The second pulse sequence 360 ​​can be configured to program a self-selecting memory cell using an intermediate logic state having a threshold voltage distribution located between two other threshold voltage distributions. The second pulse sequence 360 ​​may include a first pulse 365-b and a second pulse 370. The amplitude and polarity of the first pulse 365-b may be similar to those of pulse 365-a. The second pulse 370 can be configured to move a self-selecting memory cell from distribution 320 to distribution 310. The second pulse 370 may be a square pulse having a second polarity and maintaining a fixed amplitude corresponding to I2 for a duration T3 during its duration. In some cases, the second polarity of the second pulse 370 differs from the first polarity of the first pulse 365-b. This polarity difference may cause the threshold voltage distribution of the self-selecting memory cell to shift in a different direction than when the first pulse 365-b is applied.

[0053] In some cases, write operations to multi-level memory cells can exhibit large latency due to the detection of memory cell characteristics or fine-tuning of the pulses applied to the memory cells. A second pulse sequence 360 ​​is configured to provide relatively fast write operations for intermediate levels of the self-selected memory cells. In the second pulse sequence 360, a first pulse 365-b can be configured to move the self-selected memory cell to an extreme distribution (e.g., distribution 320). Once moved to the extreme distribution, the memory controller can be confident in the current state of the self-selected memory cell and apply a second pulse 370 to move the self-selected memory cell to the desired intermediate distribution (e.g., distribution 310). This pulse sequence avoids having multiple different pulse sequences for each combination of the current state and the desired state of the self-selected memory cell.

[0054] As shown in timing diagram 350, a first pulse 365-b can be applied for a first duration T1 and a second pulse 370 can be applied for a duration T3 at a certain time after the first pulse 365-b. Figure 3A Arrow 330 indicates a self-selected memory cell from distribution 305 to distribution 320 based on receiving a first pulse 365-b during a write operation, and then from distribution 320 to distribution 310 based on receiving a second pulse 370 during a write operation. In other instances, pulse 365-b will cause a self-selected memory cell to move from distribution 310 or distribution 315 to distribution 320. Duration T3 may occur after duration T1. In some cases, pulse sequence 360 ​​may include a gap time, where the self-selected memory cell may be biased to zero voltage level or ground during duration T2. ​​The gap time may occur between duration T1 and duration T3. In some instances, there is no gap time between applying the first pulse 365-b and the second pulse 370. In such cases, the second pulse 370 may be applied immediately after the first voltage pulse.

[0055] Although the pulse is depicted as a square pulse in Figure 350, it should be understood that programming pulses of various shapes can be applied to the self-select memory device without loss of functionality. For example, the programming pulse can be a square pulse, a rectangular pulse, a ramp pulse, or a combination thereof.

[0056] In some instances, the second pulse sequence 360 ​​can be replaced by a programming pulse sequence that includes verification. As previously described, verification can be a read voltage corresponding to the desired logic state of at least one bit. Figure 3A and 3B In some instances, the desired state may be an intermediate logic state 01. In some cases, the programming pulse sequence may contain multiple programming pulses, each associated with an energy level. To achieve intermediate logic state 01, a first programming pulse from the programming pulse sequence may be applied. A read operation may be performed to verify whether the current state of the self-selected memory cell corresponds to intermediate logic state 01. In some cases, the read operation may be a non-destructive read operation. In such cases, to verify whether the current state of the self-selected memory cell is between intermediate logic state 10 and intermediate logic state 01, the read operation may non-destructively evaluate a threshold voltage higher than the corresponding logic state. In some cases, the read operation may be selected at least partially based on the desired logic state. If the desired logic state (i.e., 01) is not achieved, a second programming pulse from the programming pulse sequence may be applied. The second programming pulse may be configured to have an energy level higher than the first programming pulse. After applying the second programming pulse, a second read operation may be performed to verify whether the desired logic state is achieved. In some cases, one or more parameters associated with the first read operation may be different from one or more parameters associated with the second read operation. If the desired logic state (i.e., intermediate logic state 01) is achieved, then no further programming pulse is applied. In some cases, using a program verification operation can increase the likelihood of accurate bit placement, but it can reduce other parameters (e.g., delay and / or power consumption).

[0057] In some instances, a self-selected memory cell can be read by applying two or more read voltages to it. In one instance, a controller associated with the self-selected memory cell may apply a first read voltage, and if the first read voltage does not cause a backlash event, a second read voltage may be applied to the self-selected memory cell as part of a read operation. In some instances, if the second read voltage does not cause a backlash event, the controller associated with the self-selected memory cell may apply a third read voltage to the self-selected memory cell as part of a read operation. The first read voltage, the second read voltage, the third read voltage, or any combination thereof may be used to determine the logical state stored by the self-selected memory cell.

[0058] Figure 4AThe illustration shows an example of diagram 400 illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multilevel memory cells, based on examples disclosed herein. The multilevel selectable memory cell can be configured to store logic states representing multiple data bits using multilevel memory technology. The voltage distribution depicts the readable logic states.

[0059] Threshold voltage distribution can represent a multi-level cell read scheme used to determine the logic stored through memory cells. Figure 4A In the example, distribution 405 may represent logic state 11, distribution 410 may represent logic state 10, distribution 415 may represent logic state 01, and distribution 420 may represent logic state 00. Distributions 405-a, 410-a, 415-a, and 420-a in part 402-a may correspond to distributions formed using write pulses with positive or negative polarity and read using read pulses with negative polarity. Distributions 405-b, 410-b, 415-b, and 420-b in part 402-b may correspond to distributions formed using write pulses with positive or negative polarity and read using read pulses with positive polarity. Corresponding distributions (e.g., distributions 405-a and 405-b, distributions 410-a and 410-b, distributions 415-a and 415-b, and distributions 420-a and 420-b) may be distributions obtained by applying the same write pulse or write pulse sequence to each pair of corresponding distributions. For example, based on the polarity of the read pulse, a memory cell programmed with a given write pulse can be in either of the corresponding distributions (e.g., distribution 405-a or distribution 405-b).

[0060] In some cases, distributions 405, 410, 415, and 420 may represent the intermediate voltage values ​​(e.g., normal quantiles) corresponding to the voltage distribution for each logic state. In some instances, two distributions may have overlapping portions, and therefore there may not be a clear separation between the two distributions. In some instances, each distribution may not be symmetrical about its midpoint. In some instances, each distribution may represent a different range of voltage values.

[0061] Figure 4B This illustrates an example of flowchart 475, which describes the support for reading multi-level memory cells, as disclosed herein. This can be seen through references... Figure 1 The described memory device or its components implement the operations of flowchart 475.

[0062] In block 440, the memory device may apply a first read voltage 425. For example, the memory device may apply the first read voltage 425, having a first polarity and a first magnitude, to a memory cell to determine the logic state stored by the memory cell. In some cases, the first polarity may be negative. In some instances, the first read voltage 425 may be an example of a ramp voltage. After applying the first read voltage 425, the memory device may determine whether a first backlash event has occurred. The first backlash event may be a backlash event that may or may not occur after the application of the first read voltage 425. Whether a backlash event occurs after the voltage is applied is a way of detecting information stored by the memory cell. In some instances, a backlash event that occurs after the application of a read voltage different from the first read voltage 425 (e.g., a second read voltage 430 or a third read voltage 435, etc.) may be referred to as a second backlash event or a third backlash event, respectively, even if the first backlash event and / or other previous backlash events have not yet occurred.

[0063] In block 445, if the memory device determines that a first bump event has occurred, the memory device may determine the logic state stored through the memory cell. In some cases, the memory device may determine that the first bump event has occurred by determining that the memory cell has been thresholded after the first read voltage 425 is applied. For example, the memory device may determine that the logic state is logic state 11 (e.g., represented by distribution 405-a). For some logic states stored through the memory cell, the memory device may perform a write-back operation (e.g., a refresh operation or a reprogramming operation) after the first bump event has occurred. However, some logic states may be enhanced by the occurrence of the first bump event and a write-back operation may not occur. In some cases, the memory device may identify whether the logic state stored through the memory cell is of a first type (e.g., a state requiring a write-back operation) or a second type (e.g., a state not requiring a write-back operation). In other cases, the memory device may be configured to perform a write-back operation (or avoid performing a write-back operation) based on determining the logic state stored through the memory cell after the first bump event. In some cases, logic state 11 may correspond to an extreme logic state (e.g., a logic state of the second type). In such cases, the memory device can recognize that the logical state stored through the memory cell is of a second type that can be enhanced by a burst event, and therefore a write-back operation may not be used. In some instances, the memory device can avoid performing a write-back or refresh operation based on the fact that the logical state stored through the memory cell is of the second type. In some instances, the memory device can avoid applying the second read voltage 430 based on recognizing the second type of logical state.

[0064] The memory device may determine that a first backflush event has not occurred. In this case, the memory device may determine that the memory cell was not thresholded after the first read voltage 425 was applied. If the memory device determines that the first backflush event has not occurred, then the memory device may apply a second read voltage 430 at block 450. For example, the memory device may apply a second read voltage 430 having a first polarity and a second magnitude to the memory cell. In some cases, the first polarity may be negative. In such cases, the second read voltage 430 may have the same polarity as the first read voltage 425. The magnitude of the second read voltage 430 may be greater than the magnitude of the first read voltage 425. In some instances, the second read voltage 430 may be an instance of a ramp voltage. After applying the second read voltage 430, the memory device may determine whether a second backflush event has occurred.

[0065] In block 455, if the memory device determines that a second bump event has occurred, the memory device may determine the logic state stored through the memory cell. In some cases, the memory device may determine that a second bump event has occurred by determining that the memory cell has been thresholded after the second read voltage 430 is applied. For example, the memory device may determine that the logic state is logic state 10 (e.g., represented by distribution 410-a). For some logic states stored through the memory cell, the memory device may perform a write-back operation (e.g., a refresh operation or a reprogramming operation) after the second bump event occurs. However, some logic states may be enhanced by the occurrence of a second bump event and a write-back operation may not occur. In some cases, the memory device may identify whether the logic state stored through the memory cell is of a first type (e.g., a state requiring a write-back operation) or a second type (e.g., a state not requiring a write-back operation). In other cases, the memory device may be configured to perform a write-back operation (or avoid performing a write-back operation) based on determining the logic state stored through the memory cell after the second bump event. In some cases, logic state 10 may correspond to an intermediate logic state (e.g., a logic state of the first type). In such cases, the memory device can identify that the logic state stored in the memory cell is of a first type that can be interfered with after a backlash event occurs (e.g., a write-back operation can be used to reprogram the memory cell after a backlash event is determined to have occurred). The memory device can then perform a reprogramming operation on the memory cell after determining logic state 10, determining that a second backlash event has occurred, or both. In some instances, the memory device can avoid applying the second read voltage 430 based on the identification of a second type of logic state.

[0066] The memory device may determine that a second backflash event has not occurred. In this case, the memory device may determine that the memory cell was not thresholded after the second read voltage 430 was applied. If the memory device determines that a second backflash event has not occurred, then the memory device may apply a third read voltage 435 at block 460. In this case, the second backflash event may be a backflash event that may or may not occur after the second read voltage 430 is applied. Whether a backflash event occurs after the voltage is applied is a way of detecting information stored through the memory cell. In some instances, a backflash event that occurs after the application of a read voltage different from the first read voltage 425 (e.g., the second read voltage 430) may be referred to as a second backflash event, even if the first backflash event and / or other previous backflash events have not yet occurred.

[0067] In block 460, the memory device may apply a third read voltage 435 having a first polarity and a third magnitude to the memory cell. In some cases, the first polarity may be negative. In such cases, the third read voltage 435 may have the same polarity as the first read voltage 425 and the second read voltage 430. The magnitude of the third read voltage 435 may be greater than the magnitude of the second read voltage 430. In such cases, the magnitude of the third read voltage 435 may be greater than the magnitude of the first read voltage 425. In some instances, the third read voltage 435 may be an example of a ramp voltage. After applying the third read voltage 435, the memory device may determine whether a third backlash event has occurred. The third backlash event may be a backlash event that may or may not occur after the application of the third read voltage 435. Whether a backlash event occurs after the voltage is applied is a way of detecting information stored through the memory cell. In some instances, a reversal event that occurs after a read voltage different from the first read voltage 425 or the second read voltage 430 (e.g., the third read voltage 435) is applied may be referred to as a third reversal event, even if the first reversal event, the second reversal event, and / or other previous reversal events have not yet occurred.

[0068] In block 465, if the memory device determines that a third surge event has occurred, the memory device may determine the logic state stored through the memory cell. In some cases, the memory device may determine that a third surge event has occurred by determining that the memory cell has been thresholded after the third read voltage 435 is applied. For example, the memory device may determine that the logic state is logic state 01 (e.g., represented by distribution 415-a). For some logic states stored through the memory cell, the memory device may perform a write-back operation (e.g., a refresh operation or a reprogramming operation) after the occurrence of the third surge event. However, some logic states may be enhanced by the occurrence of the third surge event and a write-back operation may not occur. In some cases, the memory device may identify whether the logic state stored through the memory cell is of a first type (e.g., a state requiring a write-back operation) or a second type (e.g., a state not requiring a write-back operation). In other cases, the memory device may be configured to perform a write-back operation (or avoid performing a write-back operation) based on determining the logic state stored through the memory cell after the third surge event. In some cases, logic state 01 may correspond to an intermediate logic state (e.g., a logic state of the first type). In such cases, the memory device can identify that the logic state stored in the memory cell is of a first type that can be interfered with after a backlash event occurs (e.g., the memory cell can be reprogrammed after a backlash event is determined to have occurred). The memory device can then perform a write-back operation (e.g., a reprogramming operation) on the memory cell after determining logic state 01, determining that a third backlash event has occurred, or both.

[0069] The memory device can determine that a third burst event has not occurred. In this case, the memory device can determine that the memory cell was not thresholded after the third read voltage 435 was applied. If the memory device determines that a third burst event has not occurred, then the memory device can determine a logic state at block 470. For example, the memory device can determine that the logic state is logic state 00 (e.g., represented by distribution 420-a). In some cases, logic state 00 may correspond to an extreme logic state (e.g., a second type of logic state). In this case, the memory device can identify that the logic state stored by the memory cell may be of the second type. At block 470, the memory device can avoid performing a reprogramming operation (e.g., a refresh operation) on the memory cell after determining that the logic state is 00. In this case, the memory device can avoid performing a separate write operation to refresh the memory cell.

[0070] In some cases, flowchart 475 corresponding to the operation of diagram 400 may use the application of three read voltages, wherein the polarity of each read voltage may not be reversed. For example, the first read voltage 425, the second read voltage 430, and the third read voltage 435 may have the same polarity (e.g., negative polarity). In such cases, a window budget (e.g., the distance between each distribution 405-a, 410-a, 415-a, and 420-a) may be maintained for a single polarity (e.g., corresponding to portion 402-a). However, reprogramming operations (e.g., two total reprogramming operations) may be performed in blocks 455 and 465, and a higher bias read voltage (e.g., the third read voltage 435 compared to the first read voltage 425) may be applied, thereby increasing power consumption.

[0071] Figure 5A The illustration shows an example of diagram 500 illustrating the distribution of threshold voltages in a selectable memory cell that supports reading multilevel memory cells, as disclosed herein. The multilevel selectable memory cell can be configured to store logic states representing multiple data bits using multilevel storage technology. The voltage distribution depicts the readable logic states.

[0072] Threshold voltage distribution can represent a multi-level cell read scheme used to determine the logic stored through memory cells. Figure 5A In the example, distribution 505 may represent logic state 11, distribution 510 may represent logic state 10, distribution 515 may represent logic state 01, and distribution 520 may represent logic state 00. Distributions 505-a, 510-a, 515-a, and 520-a in portion 502-a may correspond to distributions formed using write pulses with negative or positive polarity and read using read pulses with negative polarity. Distributions 505-b, 510-b, 515-b, and 520-b in portion 502-b may correspond to distributions formed using write pulses with negative or positive polarity and read using read pulses with positive polarity. Corresponding distributions (e.g., distributions 505-a and 505-b, distributions 510-a and 510-b, distributions 515-a and 515-b, and distributions 520-a and 520-b) may be distributions obtained by applying the same write pulse or write pulse sequence to each pair of corresponding distributions. For example, based on the polarity of the read pulse, a memory cell programmed with a given write pulse can be in either of the corresponding distributions (e.g., distribution 505-a or distribution 505-b).

[0073] In some cases, distributions 505, 510, 515, and 520 may represent the intermediate voltage values ​​(e.g., normal quantiles) corresponding to the voltage distribution for each logic state. In some instances, two distributions may have overlapping portions, and therefore there may not be a clear separation between the two distributions. In some instances, each distribution may not be symmetrical about its midpoint. In some instances, each distribution may represent a different range of voltage values.

[0074] Figure 5B This illustrates an example of flowchart 575, which describes the support for reading multi-level memory cells, as disclosed herein. This can be seen through references... Figure 1 The described memory device or its components implement the operation of flowchart 575. The operation of flowchart 575 may be similar to the operation described in flowchart 475 with reference to FIG. 4. Thus, some features described with reference to FIG. 4 may be applied to flowchart 575 of FIG. 5. One difference between the operation of flowchart 575 and the operation of flowchart 475 includes that one of the read voltages (e.g., the second read voltage 530) has a different polarity than the first read voltage 525 or the third read voltage 535. This feature reduces the likelihood of a write-back operation occurring during a read operation associated with flowchart 575 compared to a read operation associated with flowchart 475. In some cases, switching the polarity of the read voltage can increase the amount of time or energy used to perform a read operation.

[0075] In block 540, the memory device may apply a first read voltage 525. For example, the memory device may apply a first read voltage 525 having a first polarity to a memory cell to determine a logical state stored by the memory cell. In some cases, the first polarity may be negative. In some instances, the first read voltage 525 may be an example of a ramp voltage. After applying the first read voltage 525, the memory device may determine whether a first backlash event has occurred. The first backlash event may be a backlash event that may or may not occur after the application of the first read voltage 525. Whether a backlash event occurs after the voltage is applied is a way of detecting information stored by the memory cell. In some instances, a backlash event that occurs after the application of a read voltage different from the first read voltage 525 (e.g., a second read voltage 530 or a third read voltage 535, etc.) may be referred to as a second backlash event or a third backlash event, respectively, even if the first backlash event and / or other previous backlash events have not yet occurred.

[0076] In block 545, if the memory device determines that a first bump event has occurred, the memory device may determine a logic state. In some cases, the memory device may determine that the first bump event has occurred by determining that the memory cell has been thresholded after the first read voltage 525 has been applied. In block 545, the memory device may determine that the logic state is logic state 11 (e.g., represented by distribution 505-a). In some cases, logic state 11 may correspond to an extreme logic state (e.g., a second type of logic state). In such cases, the logic state may be enhanced after the bump event has occurred (e.g., the memory cell may be refreshed after the bump event has been determined to have occurred). In some instances, the memory device may avoid performing a write-back operation or a refresh operation based on the logic state stored by the memory cell being of the second type. In some instances, the memory device may avoid applying the second read voltage 530 based on identifying the second type of logic state.

[0077] The memory device may determine that a first backflush event has not occurred. In this case, the memory device may determine that the memory cell was not thresholded after the first read voltage 525 was applied. If the memory device determines that the first backflush event has not occurred, then the memory device may apply a second read voltage 530 at block 550. For example, the memory device may apply a second read voltage 530 having a second polarity to the memory cell. In some cases, the second polarity may be positive. In such cases, the second read voltage 530 may have a different polarity than the first read voltage 525. In some instances, the second read voltage 530 may have a similar magnitude to the first read voltage 525 (e.g., within the same range as the first read voltage 525). The second read voltage 530 may have the same magnitude as the first read voltage 525. In some instances, the second read voltage 530 may be an example of a ramp voltage. After applying the second read voltage 530, the memory device may determine whether a second backflush event has occurred.

[0078] In block 555, if the memory device determines that a second burst event has occurred, the memory device may determine a logic state. In some cases, the memory device may determine that a second burst event has occurred by determining that the memory cell has been thresholded after the second read voltage 530 is applied. In block 555, the memory device may determine that the logic state is logic state 00 (e.g., represented by distribution 520-b). In some cases, logic state 00 may correspond to an extreme logic state (e.g., a second type of logic state). In such cases, the memory device may identify that the logic state stored through the memory cell is of the second type. The second type of logic state may be enhanced after a burst event occurs (e.g., the memory cell may be refreshed after a burst event is determined to have occurred). In some instances, the memory device may avoid performing a write-back operation or a refresh operation based on the fact that the logic state stored through the memory cell is of the second type. In some instances, the memory device may avoid applying a third read voltage 535 based on the identification of the second type of logic state.

[0079] The memory device may determine that a second backflash event has not occurred. In this case, the memory device may determine that the memory cell was not thresholded after the second read voltage 530 was applied. If the memory device determines that a second backflash event has not occurred, then the memory device may apply a third read voltage 535 at block 560. In this case, the second backflash event may be a backflash event that may or may not occur after the second read voltage 530 is applied. Whether a backflash event occurs after the voltage is applied is a way of detecting information stored by the memory cell. In some instances, a backflash event that occurs after the application of a read voltage different from the first read voltage 525 (e.g., the second read voltage 530) may be referred to as a second backflash event, even if the first backflash event and / or other previous backflash events have not yet occurred.

[0080] In block 560, the memory device may apply a third read voltage 535 having a first polarity to the memory cell. In some cases, the first polarity may be negative. In such cases, the third read voltage 535 may have the same polarity as the first read voltage 525 and may have a different polarity than the second read voltage 530. The magnitude of the third read voltage 535 may be greater than the magnitude of both the second read voltage 530 and the first read voltage 525. In some instances, the third read voltage 535 may be an example of a ramp voltage. After applying the third read voltage 535, the memory device may determine whether a third backlash event has occurred. The third backlash event may be a backlash event that may or may not occur after the application of the third read voltage 535. Whether a backlash event occurs after the voltage is applied is a way of detecting information stored through the memory cell. In some instances, a surge event that occurs after a read voltage different from the first read voltage 525 or the second read voltage 530 (e.g., the third read voltage 535) is applied may be referred to as a third surge event, even if the first surge event, the second surge event and / or other previous surge events have not yet occurred.

[0081] In block 565, if the memory device determines that a third surge event has occurred, then the memory device may determine a logic state. In some cases, the memory device may determine that a third surge event has occurred by determining that the memory cell has been thresholded after a third read voltage 535 has been applied. In block 565, the memory device may determine that the logic state is logic state 10 (e.g., represented by distribution 510-a). In some cases, logic state 10 may correspond to an intermediate logic state (e.g., a first type of logic state). In such cases, the memory device may identify that the logic state stored by the memory cell may be of the first type. The first type of logic state may be interfered with after a surge event occurs (e.g., the memory cell may be reprogrammed after a surge event is determined). In block 565, the memory device may perform a write-back operation (e.g., a reprogramming operation or a refresh operation) on the memory cell after determining logic state 10, determining that a third surge event has occurred, or both.

[0082] The memory device can determine that a third surge event has not occurred. In this case, the memory device can determine that the memory cell was not thresholded after the third read voltage 535 was applied. If the memory device determines that a third surge event has not occurred, then the memory device can determine a logic state at block 570. For example, the memory device can determine that the logic state is logic state 01 (e.g., represented by distribution 515-a). In some cases, logic state 01 may correspond to an intermediate logic state (e.g., a first type of logic state). In such cases, the memory device can identify that the logic state stored by the memory cell may be of the first type. At block 570, the memory device can avoid performing a reprogramming operation (e.g., a refresh operation) on the memory cell after determining that the logic state is 01 because no surge event occurred to interfere with the logic state of the memory cell.

[0083] In some cases, flowchart 575 corresponding to the operation of diagram 500 may use the application of three read voltages, wherein the polarity of each sequential read voltage can be reversed. In such cases, the memory device may reverse the polarity of the read voltages twice. For example, the polarity of the first read voltage 525 may be negative, the polarity of the second read voltage 530 may be positive, and the polarity of the third read voltage 535 may be negative. In such cases, diagram 500 may include window budgets for two polarities (e.g., corresponding to portions 502-a and 502-b) (e.g., the distance between each distribution 505-a, 510-a, 515-a, and 520-a or the distance between each distribution 505-b, 510-b, 515-b, and 520-b). However, a reprogramming operation (e.g., a total reprogramming operation) can be performed in block 565 and a lower bias read voltage (e.g., a third read voltage 535 compared to the first read voltage 525) can be applied, thereby reducing power consumption compared to the operation of FIG4.

[0084] Figure 6A The illustration shows an example of diagram 600 illustrating the distribution of threshold voltages in a self-selecting memory cell that supports reading multi-level memory cells, according to examples disclosed herein. The multi-level self-selecting memory cell can be configured to store logic states representing multiple data bits using multi-level memory technology. The voltage distribution depicts the readable logic states. Diagram 600 may be as referenced. Figure 5A An example of the described diagram 500.

[0085] Figure 6B This illustrates an example of flowchart 675, which describes the support for reading multi-level memory cells, as disclosed herein. This can be seen through references... Figure 1The described memory device or its components implement the operation of flowchart 675. The operation of flowchart 675 may be similar to the operation described with reference to flowcharts 475 and 575 of Figures 4 and 5. Therefore, some features described with reference to Figures 4 and 5 can be applied to flowchart 675 of Figure 6. One difference between the operation of flowchart 675 and the operation of flowchart 575 includes a reduction in the number of transitions between different polarities of the read voltage from a maximum of two transitions to a maximum of one transition. This feature can be achieved by sequentially grouping two read voltages of the same polarity in timing. Compared to the read operation associated with flowchart 575, this feature reduces the duration or amount of energy required to perform the read operation associated with flowchart 675. In some cases, switching the polarity of the read voltage can increase the amount of time or energy required to perform the read operation.

[0086] The operations performed in boxes 640, 645, 650, and 655 can be as follows (see reference). Figure 5B Examples of operations performed by blocks 540, 545, 550, and 555 are described. A first backslip event may or may not occur after the application of a first read voltage 625. Whether a backslip event occurs after the voltage is applied is a way of detecting information stored by the memory cell. In some instances, a backslip event occurring after the application of a read voltage different from the first read voltage 625 (e.g., a second read voltage 630 or a third read voltage 635, etc.) may be referred to as a second backslip event or a third backslip event, respectively, even if the first backslip event and / or other previous backslip events have not yet occurred.

[0087] In block 660, if the memory device determines that a second rush event has not occurred, the memory device may apply a third read voltage 635. In this case, the second rush event may be a rush event that may or may not occur after the application of the second read voltage 630. In some instances, a rush event that occurs after the application of a read voltage different from the first read voltage 625 (e.g., the second read voltage 630) may be referred to as a second rush event, even if the first rush event and / or other previous rush events have not yet occurred.

[0088] In block 660, the memory device may apply a third read voltage 635 having a second polarity to the memory cell. In some cases, the second polarity may be positive. In such cases, the third read voltage 635 may have the same polarity as the second read voltage 630 and may have a different polarity than the first read voltage 625. The magnitude of the third read voltage 635 may be greater than the magnitudes of the second read voltage 630 and the first read voltage 625. In some instances, the third read voltage 635 may be an example of a ramp voltage. After applying the third read voltage 635, the memory device may determine whether a third backlash event has occurred. The third backlash event may be a backlash event that may or may not occur after the application of the third read voltage 635. In some instances, a backlash event that occurs after applying a read voltage different from the first read voltage 625 or the second read voltage 630 (e.g., the third read voltage 635) may be referred to as a third backlash event, even if the first backlash event, the second backlash event, and / or other previous backlash events have not yet occurred.

[0089] If the memory device determines that a third surge event has occurred, the memory device may determine a logic state at block 665. In some cases, the memory device may determine that a third surge event has occurred by determining that the memory cell has been thresholded after the third read voltage 635 is applied. At block 665, the memory device may determine that the logic state is logic state 01 (e.g., represented by distribution 615-b). In some cases, logic state 01 may correspond to an intermediate logic state (e.g., a first type of logic state). In such cases, the memory device may identify that the logic state stored by the memory cell may be of the first type. The first type of logic state may be interfered with after a surge event occurs (e.g., the memory cell may be reprogrammed after a surge event is determined to have occurred). At block 665, the memory device may then perform a reprogramming operation on the memory cell after determining that the logic state is 01, determining that a third surge event has occurred, or both.

[0090] The memory device can determine that a third surge event has not occurred. In this case, the memory device can determine that the memory cell was not thresholded after the third read voltage 635 was applied. If the memory device determines that a third surge event has not occurred, then the memory device can determine a logic state at block 670. For example, the memory device can determine that the logic state is logic state 10 (e.g., represented by distribution 610-b). In some cases, logic state 10 may correspond to an intermediate logic state (e.g., a first-type logic state). In this case, the memory device can identify that the logic state stored by the memory cell may be of the first type. At block 670, the memory device can avoid performing a reprogramming operation (e.g., a refresh operation) on the memory cell after determining that the logic state is 10, determining that a third surge event has not occurred, or both. In this case, the memory device can avoid performing a separate write operation to refresh the memory cell.

[0091] In some cases, flowchart 675 corresponding to the operation of diagram 600 may use the application of three read voltages, wherein the polarities of the first two sequential read voltages can be reversed. In such cases, the memory device may reverse the polarity of the read voltages once. For example, the polarity of the first read voltage 625 may be negative, the polarity of the second read voltage 630 may be positive, and the polarity of the third read voltage 635 may be positive. In such cases, diagram 600 may include window budgets for two polarities (e.g., corresponding to portions 602-a and 602-b) (e.g., the distance between each distribution 605-a, 610-a, 615-a, and 620-a or the distance between each distribution 605-b, 610-b, 615-b, and 620-b). However, a reprogramming operation (e.g., a total reprogramming operation) can be performed in block 665, and a lower bias read voltage (e.g., a third read voltage 635 compared to the first read voltage 625) can be applied, thereby reducing power consumption compared to the operation of FIG. 4. In some instances, the read scheme according to FIG. 600 can reduce power consumption and improve the performance of the memory device compared to the operation of FIG. 5.

[0092] Figure 7This describes an example of a timing diagram 700 supporting reads of multi-level memory cells, as disclosed herein. Timing diagram 700 may include a read pulse 705 and a reprogramming pulse 710. Timing diagram 700 may plot the magnitude of the voltage applied to the memory cell with respect to time (x-axis) and one or more pulses (y-axis). The reprogramming pulse 710 may be of opposite polarity to the read pulse 705 and may have a lower magnitude than the read pulse 705. In some instances, the reprogramming pulse 710 may be of opposite polarity to the read pulse 705 and may have a higher magnitude than the read pulse 705. In some cases, the read pulse 705 may include a voltage distribution through the memory cell stored in an extreme state (e.g., as shown in reference). Figure 3A (Described distribution 305 or distribution 320). In such cases, the reprogramming pulse 710 can reduce the energy value because the desired change in the voltage distribution of the memory cell is small. This type of case is, in principle, similar to the reference... Figure 3A and 3B The described write operation. The reprogramming pulse 710 with a reduced magnitude saves power compared to other possible solutions.

[0093] In some cases, memory cells can be programmed using intermediate logic states (e.g., logic state 01 or logic state 10). In such cases, two pulses of opposite polarities can be applied to the memory cell. For example, the memory device can apply a first pulse (e.g., read pulse 705). Read pulse 705 may contain a negative polarity. In such cases, read pulse 705 may be a square pulse with a negative polarity and a fixed value corresponding to V1. In some cases, read pulse 705 may be as referenced. Figure 4B and 5B Examples of the described third read voltage 435 and third read voltage 535 are provided. For example, a read pulse 705 may be applied based on the determination that a second return event has not occurred. In some instances, the read pulse 705 may be as described in the reference. Figure 4B An example of the second read voltage 430 is described. In such cases, a read pulse 705 may be applied after it is determined that the first return event has not occurred.

[0094] After applying the read pulse 705, the memory device may apply a second pulse (e.g., a reprogramming pulse 710). The reprogramming pulse 710 may contain a polarity opposite to that of the read pulse 705. For example, the reprogramming pulse 710 may contain a positive polarity while the read pulse 705 may contain a negative polarity. The reprogramming pulse 710 may be a square pulse having a positive polarity and a fixed value corresponding to V2. The value of the reprogramming pulse 710 may be less than the value of the read pulse 705. In some instances, the value of the reprogramming pulse 710 may be greater than the value of the read pulse 705. In some cases, the reprogramming pulse 710 may be as described in reference... Figure 4B and 5B Examples of reprogramming operations performed by blocks 455, 465, and 565 are described. For example, a reprogramming pulse 710 may be applied based on determining that the logic state is an intermediate state (e.g., logic state 01 or logic state 10).

[0095] In some cases, the read pulse 705 may contain a positive polarity. In such cases, the read pulse 705 may be as described in the reference. Figure 6B An example of the described third read voltage 635. For example, a read pulse 705 may be applied based on the determination that a second backslip event has not occurred. After applying the positive read pulse 705, the memory device may apply a second pulse with a negative polarity (e.g., a reprogramming pulse 710). In some cases, the reprogramming pulse 710 may be as described in the reference... Figure 6B The described block 665 describes an example of a reprogramming operation performed. For example, a reprogramming pulse 710 may be applied based on determining that the logic state is an intermediate state (e.g., logic state 01). A reprogramming pulse 710 with negative polarity may contain a magnitude smaller than that of a read pulse 705 with positive polarity. In some instances, a reprogramming pulse 710 with negative polarity may contain a magnitude larger than that of a read pulse 705 with positive polarity.

[0096] The memory device may perform a reprogramming operation (e.g., apply a reprogramming pulse 710) after performing a read operation (e.g., apply a read pulse 705). In some cases, the first pulse (e.g., read pulse 705) may serve as the first step in the reprogramming operation, thereby resulting in additional time and power consumption compared to performing the reprogramming operation using a single pulse. In such cases, the first pulse may not be part of the reprogramming operation, such that the first pulse is read pulse 705 and the second pulse is reprogramming pulse 710. In some cases, the reprogramming operation may be part of a read operation as an embedded command or a separate command dedicated to the reprogramming operation.

[0097] Figure 8A block diagram 800 illustrates a memory device 805 supporting reading of multi-level memory cells according to an example disclosed herein. The memory device 805 may be as described in the references... Figures 1 to 7 Examples of aspects of the described memory device. Memory device 805 may include a logic state component 810, a first voltage component 815, a second voltage component 820, a third voltage component 825, a first pop-back component 830, a second pop-back component 835, a third pop-back component 840, and a reprogramming component 845. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0098] The logic state component 810 can determine the logic state stored in the memory cell based on whether a first or second burst event has occurred. In some instances, the logic state component 810 can determine the logic state stored in the memory cell based on whether a first, second, or third burst event has occurred.

[0099] In some instances, the logic state component 810 may identify that the logic state stored in the memory cell contains a first type based on determining that a third backsliding event has occurred, wherein the reprogramming operation is performed based on the identification that the logic state stored in the memory cell contains the first type. In some instances, the logic state component 810 may identify that the logic state stored in the memory cell contains a first type that has been disturbed after the backsliding event has occurred.

[0100] In some instances, the logic state component 810 may identify, based on determining that a second backslip event has occurred, that the logic state stored in the memory cell contains a first type that was disrupted after the backslip event, wherein performing a reprogramming operation on the memory cell is based on identifying that the logic state contains the first type. In some instances, the logic state component 810 may identify, based on determining that a first backslip event has occurred, that the logic state stored in the memory cell contains a second type that was enhanced after the backslip event.

[0101] The first voltage component 815 may apply a first read voltage having a first polarity to a memory cell to determine a logic state stored by a memory cell configured to store three or more logic states. In some instances, the first voltage component 815 may apply a first read voltage having a first polarity and a first magnitude to a memory cell to determine a logic state stored by a memory cell configured to store three or more logic states.

[0102] In some cases, the first polarity contains a negative polarity and the second polarity contains a positive polarity. In some cases, the magnitude of the first read voltage is similar to the magnitude of the second read voltage. In some cases, the first polarity contains a negative polarity. In some cases, the second magnitude is greater than the first magnitude, and a third magnitude is greater than the second magnitude.

[0103] The second voltage component 820 may apply a second read voltage with a second polarity to the memory cell based on the determination that the first backlash event has not occurred. In some instances, the second voltage component 820 may apply a second read voltage with a first polarity and a second magnitude to the memory cell based on the determination that the first backlash event has not occurred.

[0104] The third voltage component 825 may apply a third read voltage having a first polarity and a third magnitude to the memory cell based on the determination that a second surge event has not occurred. In some embodiments, the third voltage component 825 may apply a third read voltage having a first polarity and a magnitude greater than the second read voltage to the memory cell based on the determination that a second surge event has not occurred. In some embodiments, the third voltage component 825 may apply a third read voltage having a second polarity and a magnitude greater than the second read voltage to the memory cell based on the determination that a second surge event has not occurred. In some embodiments, the third voltage component 825 may determine that a third surge event has not occurred.

[0105] The first surge-back component 830 can determine whether a first surge-back event has occurred after a first read voltage has been applied. In some instances, the first surge-back component 830 can determine that a memory cell has been thresholded after the first read voltage has been applied. In some instances, the first surge-back component 830 can determine that a first surge-back event has occurred based on determining that a memory cell has been thresholded after the first read voltage has been applied.

[0106] The second surge-back component 835 can determine whether a second surge-back event has occurred after the second read voltage has been applied. In some instances, the second surge-back component 835 can determine that a second surge-back event has occurred.

[0107] The third surge-back component 840 can determine whether a third surge-back event has occurred after a third read voltage has been applied. In some instances, the third surge-back component 840 can determine whether a third surge-back event has occurred after a third read voltage has been applied, wherein the determination of the logic state stored by the memory cell is based on the determination of whether a third surge-back event has occurred.

[0108] In some instances, the third surge-back component 840 can determine that a third surge-back event has occurred. In some instances, the third surge-back component 840 can determine that a third surge-back event has not occurred. In some instances, the third surge-back component 840 can determine whether a third surge-back event has occurred after a third read voltage has been applied, wherein the determination of the logic state stored in the memory cell is based on the determination of whether a third surge-back event has occurred.

[0109] The reprogramming component 845 may perform a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that a third surge event has occurred. In some instances, the reprogramming component 845 may avoid performing a reprogramming operation on the memory cell based on the determination that a third surge event has not occurred. In some instances, the reprogramming component 845 may perform a reprogramming operation on the memory cell based on the identification that the logical state contains a first type. In some instances, the reprogramming component 845 may perform a reprogramming operation on the memory cell based on the determination that a second surge event has occurred, wherein the determination of the logical state stored in the memory cell is based on the determination that a second surge event has occurred.

[0110] Figure 9 The flowchart illustrates one or more methods 900 for supporting reading of multi-level memory cells according to examples disclosed herein. The operation of method 900 can be implemented using a memory device or its components as described herein. For example, it can be implemented using... (See reference...) Figure 8 The described memory device performs the operation of method 900. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0111] In 905, the memory device may apply a first read voltage of a first polarity to a memory cell to determine the logic states stored by a memory cell configured to store three or more logic states. Operation of 905 may be performed according to the methods described herein. In some instances, it may be performed as described in reference... Figure 8 The first voltage component described performs the operation of 905.

[0112] In 910, the memory device can determine whether a first backlash event has occurred after a first read voltage is applied. The operation of 910 can be performed according to the method described herein. In some instances, it can be done as described in the reference... Figure 8 The first sudden return component described performs the operation of 910.

[0113] In 915, the memory device may apply a second read voltage of a second polarity to the memory cell based on the determination that a first surge event has failed. Operation of 915 can be performed according to the method described herein. In some instances, it can be performed as described in reference... Figure 8 The second voltage component described performs the operation of 915.

[0114] In 920, the memory device can determine whether a second surge event has occurred after the application of a second read voltage. Operation of 920 can be performed according to the method described herein. In some instances, it can be done via, as referenced... Figure 8 The second reversal component described performs the 920 operation.

[0115] In 925, the memory device can determine the logical state stored in the memory cell based on whether a first or second burst event has occurred. Operation of 925 can be performed according to the methods described herein. In some instances, it can be done as described in the reference... Figure 8 The described logical state component performs the 925 operation.

[0116] The first surge event can be a surge event that may or may not occur after the application of the first read voltage. Whether a surge event occurs after the application of voltage is a way of detecting information stored through the memory cell. In some instances, a surge event that occurs after the application of a read voltage different from the first read voltage (e.g., a second read voltage or a third read voltage, etc.) can be referred to as a second surge event or a third surge event, respectively, even if the first surge event and / or other previous surge events have not yet occurred.

[0117] In some instances, the device described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first read voltage of a first polarity to a memory cell to determine a logical state stored by the memory cell configured to store three or more logical states; determining whether a first pop-up event occurs after the first read voltage is applied; applying a second read voltage of a second polarity to the memory cell based on the determination that the first pop-up event did not occur; determining whether a second pop-up event occurs after the second read voltage is applied; and determining the logical state stored by the memory cell based on the determination that either the first or second pop-up event occurred.

[0118] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: applying a third read voltage having a first polarity and an amount greater than the second read voltage to a memory cell based on determining that a second back-end event has not occurred; and determining whether a third back-end event has occurred after the application of the third read voltage, wherein determining the logic state stored in the memory cell may be based on determining whether the third back-end event has occurred.

[0119] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third surge event has occurred; and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0120] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions of a first type for identifying a logical state stored in a memory cell that comprises a first type based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logical state stored in the memory cell comprises the first type.

[0121] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third backstab event has not occurred; and avoiding reprogramming of memory cells based on the determination that the third backstab event has not occurred.

[0122] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: applying a third read voltage having a second polarity and an amount greater than the second read voltage to a memory cell based on determining that a second back-end event has not occurred; and determining whether a third back-end event has occurred after the application of the third read voltage, wherein determining the logic state stored in the memory cell may be based on determining whether the third back-end event has occurred.

[0123] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third surge event has occurred; and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0124] Some examples of the method 900 and apparatus described herein may further include operations, features, components, and instructions for identifying a logic state stored in a memory cell that comprises a first type based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logic state stored in the memory cell comprises the first type.

[0125] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third backstab event has not occurred; and avoiding reprogramming of memory cells based on the determination that the third backstab event has not occurred.

[0126] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: identifying that a logical state stored in a memory cell contains a first type that can be disturbed after a relapse event; and performing a reprogramming operation on the memory cell based on the identification that the logical state contains the first type.

[0127] Some examples of the method 900 and device described herein may further include a second type of operation, feature, component, or instruction that can be enhanced after the occurrence of a first reversal event, based on determining that a first reversal event has occurred.

[0128] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: determining that a memory cell is thresholded after a first read voltage is applied; and determining that a first backlash event has occurred based on determining that the memory cell is thresholded after the first read voltage is applied.

[0129] In some instances of the method 900 and device described herein, the first polarity includes a negative polarity and the second polarity includes a positive polarity.

[0130] In some instances of the method 900 and device described herein, the magnitude of the first read voltage may be similar to the magnitude of the second read voltage.

[0131] Figure 10 The flowchart illustrates one or more methods 1000 for supporting reading of multi-level memory cells, as disclosed herein. The operation of method 1000 can be implemented using a memory device or its components as described herein. For example, it can be implemented using... (See reference...) Figure 8 The described memory device performs the operation of method 1000. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0132] In 1005, the memory device may apply a first read voltage having a first polarity and a first magnitude to a memory cell to determine the logic states stored by a memory cell configured to store three or more logic states. Operation of 1005 may be performed according to the method described herein. In some instances, it may be performed as described in reference... Figure 8 The first voltage component described performs the operation of 1005.

[0133] In 1010, the memory device can determine whether a first backlash event has occurred after a first read voltage is applied. The operation of 1010 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 8 The first sudden return component described performs the operation of 1010.

[0134] At 1015, the memory device may apply a second read voltage having a first polarity and a second magnitude to the memory cell based on the determination that a first backflash event has failed. Operation of 1015 can be performed according to the method described herein. In some instances, it can be performed as described in reference... Figure 8 The second voltage component described performs the operation of 1015.

[0135] In 1020, the memory device can determine whether a second surge event has occurred after the application of a second read voltage. The operation of 1020 can be performed according to the method described herein. In some instances, it can be done as described in the reference... Figure 8 The second sudden return component described performs the operation of 1020.

[0136] In step 1025, the memory device may apply a third read voltage having a first polarity and a third magnitude to the memory cell based on the determination that a second surge event has not occurred. The operation of step 1025 can be performed according to the method described herein. In some instances, it can be performed as described in reference... Figure 8 The third voltage component described performs the operation of 1025.

[0137] In 1030, the memory device can determine whether a third surge event has occurred after a third read voltage is applied. The operation of 1030 can be performed according to the method described herein. In some instances, it can be done via, as referenced... Figure 8 The third reentry component described performs the operation of 1030.

[0138] In 1035, the memory device can determine the logical state stored in the memory cell based on whether a first, second, or third burst event has occurred. The operation of 1035 can be performed according to the methods described herein. In some instances, it can be performed as described in the reference... Figure 8The described logical state component performs the 1035 operation.

[0139] The first surge event can be a surge event that may or may not occur after the application of the first read voltage. Whether a surge event occurs after the application of voltage is a way of detecting information stored through the memory cell. In some instances, a surge event that occurs after the application of a read voltage different from the first read voltage (e.g., a second read voltage or a third read voltage, etc.) can be referred to as a second surge event or a third surge event, respectively, even if the first surge event and / or other previous surge events have not yet occurred.

[0140] In some instances, the device described herein may perform one or more methods, such as method 1000. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first read voltage having a first polarity and a first magnitude to a memory cell to determine a logical state stored by the memory cell configured to store three or more logical states; determining whether a first pop-up event occurs after the first read voltage is applied; applying a second read voltage having a first polarity and a second magnitude to the memory cell based on the determination that the first pop-up event did not occur; determining whether a second pop-up event occurs after the second read voltage is applied; applying a third read voltage having a first polarity and a third magnitude to the memory cell based on the determination that the second pop-up event did not occur; determining whether a third pop-up event occurs after the third read voltage is applied; and determining the logical state stored by the memory cell based on the determination that the first pop-up event, the second pop-up event, or the third pop-up event occurred.

[0141] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third surge event has occurred; and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0142] Some examples of the method 1000 and device described herein may further include operations, features, components, or instructions of a first type for identifying a logical state stored in a memory cell that comprises a first type based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logical state stored in the memory cell comprises the first type.

[0143] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: determining that a third backlash event has not occurred; and avoiding reprogramming of memory cells based on the determination that the third backlash event has not occurred.

[0144] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: determining that a second surge event has occurred; and performing a reprogramming operation on a memory cell based on determining that the second surge event has occurred, wherein determining the logical state stored in the memory cell may be based on determining that the second surge event has occurred.

[0145] Some examples of the method 1000 and apparatus described herein may further include identifying, based on determining that a second backslip event has occurred, a logical state stored in a memory cell contains a first type of operation, feature, component, or instruction that may be interfered with after the backslip event has occurred, wherein performing a reprogramming operation on the memory cell may be based on identifying that the logical state contains the first type.

[0146] Some examples of the method 1000 and device described herein may further include a second type of operation, feature, component, or instruction that can be enhanced after the occurrence of a first reversal event, for identifying a logical state stored in a memory cell based on determining that a first reversal event has occurred.

[0147] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: determining that a memory cell is thresholded after a first read voltage is applied; and determining that a first backlash event has occurred based on determining that the memory cell is thresholded after the first read voltage is applied.

[0148] In some instances of the method 1000 and device described herein, the first polarity includes a negative polarity.

[0149] In some instances of the method 1000 and device described herein, the second value may be greater than the first value, and the third value may be greater than the second value.

[0150] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods may be combined.

[0151] Describe a device. The device may include: a memory array including memory cells; and a control component coupled to the memory array, the control component being configured to cause the device to: apply a first read voltage having a first polarity to the memory cells to determine logical states stored by the memory cells configured to store three or more logical states; determine whether a first backlash event occurs after the first read voltage is applied; apply a second read voltage having a second polarity to the memory cells based on the determination that the first backlash event did not occur; determine whether a second backlash event occurs after the second read voltage is applied; and determine the logical states stored by the memory cells based on the determination that either the first backlash event or the second backlash event occurred.

[0152] Some instances may further include applying a third read voltage with a first polarity and a magnitude greater than the second read voltage to the memory cell based on determining that a second back-end event has not occurred, and determining whether a third back-end event has occurred after the application of the third read voltage, wherein determining the logic state stored in the memory cell may be based on determining whether the third back-end event has occurred.

[0153] Some instances may further include determining that a third surge event has occurred, and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0154] Some instances may further include identifying a first type of logical state stored in the memory cell based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logical state stored in the memory cell contains the first type.

[0155] Some instances may further include determining that a third surge event has not occurred, and avoiding reprogramming the memory cell based on the determination that the third surge event has not occurred.

[0156] Some instances may further include applying a third read voltage with a second polarity and a magnitude greater than the second read voltage to the memory cell based on determining that a second back-end event has not occurred, and determining whether a third back-end event has occurred after the application of the third read voltage, wherein determining the logic state stored in the memory cell may be based on determining whether the third back-end event has occurred.

[0157] Some instances may further include determining that a third surge event has occurred, and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0158] Some instances may further include identifying a first type of logical state stored in the memory cell based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logical state stored in the memory cell contains the first type.

[0159] Some instances may further include determining that a third surge event has not occurred, and avoiding reprogramming the memory cell based on the determination that the third surge event has not occurred.

[0160] Some instances may further include identifying that the logical states stored in the memory cell contain a first type that can be disturbed after a sudden return event, and performing a reprogramming operation on the memory cell based on the identification that the logical states contain the first type.

[0161] Some instances may further include a second type of logic state stored in the memory cell that can be enhanced after the occurrence of the first backlash event, based on the determination that a first backlash event has occurred.

[0162] Some instances may further include determining that a memory cell is thresholded after a first read voltage is applied, and determining that a first backlash event has occurred based on determining that the memory cell is thresholded after the first read voltage is applied.

[0163] In some instances, the first polarity contains a negative polarity and the second polarity contains a positive polarity.

[0164] In some instances, the magnitude of the first read voltage may be similar to the magnitude of the second read voltage.

[0165] Describe a device. The device may include: a memory array including memory cells; and a control component coupled to the memory array, the control component being configured to cause the device to: apply a first read voltage having a first polarity and a first magnitude to the memory cells to determine logical states stored by the memory cells configured to store three or more logical states; determine whether a first backlash event occurs after the first read voltage is applied; apply a second read voltage having the first polarity and a second magnitude to the memory cells based on the determination that the first backlash event did not occur; determine whether a second backlash event occurs after the second read voltage is applied; apply a third read voltage having the first polarity and a third magnitude to the memory cells based on the determination that the second backlash event did not occur; determine whether a third backlash event occurs after the third read voltage is applied; and determine the logical states stored by the memory cells based on the determination that the first backlash event, the second backlash event, or the third backlash event occurred.

[0166] Some instances may further include determining that a third surge event has occurred, and performing a reprogramming operation on the memory cell after determining the logical state stored in the memory cell based on the determination that the third surge event has occurred.

[0167] Some instances may further include identifying a first type of logical state stored in the memory cell based on determining that a third recurrence event has occurred, wherein performing a reprogramming operation may be based on identifying that the logical state stored in the memory cell contains the first type.

[0168] Some instances may further include determining that a third surge event has not occurred, and avoiding reprogramming the memory cell based on the determination that the third surge event has not occurred.

[0169] Some instances may further include determining that a second surge event has occurred, and performing a reprogramming operation on the memory cell based on determining that the second surge event has occurred, wherein determining the logical state stored in the memory cell may be based on determining that the second surge event has occurred.

[0170] Some instances may further include identifying, based on determining that a second backsliding event has occurred, that the logical state stored in the memory cell contains a first type that can be interfered with after the backsliding event has occurred, wherein performing a reprogramming operation on the memory cell may be based on identifying that the logical state contains the first type.

[0171] Some instances may further include a second type of logic state stored in the memory cell that can be enhanced after the occurrence of the first backlash event, based on the determination that a first backlash event has occurred.

[0172] Some instances may further include determining that a memory cell is thresholded after a first read voltage is applied, and determining that a first backlash event has occurred based on determining that the memory cell is thresholded after the first read voltage is applied.

[0173] In some instances, the first polarity includes the negative polarity.

[0174] In some instances, the second value may be greater than the first value, and the third value may be greater than the second value.

[0175] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0176] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports signal flow between them. Components are considered to be in electronic communication (or conductive contact, connection, or coupling) with each other if any conductive path exists between them that can readily support signal flow between them. At any given time, the conductive path between components that are in electronic communication (or conductive contact, connection, or coupling) can be open or closed, depending on the operation of a device containing connected components. The conductive path between connected components can be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0177] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact to other components of a memory cell or memory array. Electrodes can comprise traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of the memory array.

[0178] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOS)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0179] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0180] The descriptions and accompanying drawings herein depict exemplary configurations and do not represent all instances that can be implemented or are within the scope of the claims. The term "example" as used herein means "serving as an example, illustration, or illustration" and is not "preferred" or "superior to other examples." Specific details are included to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, structures and apparatus are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0181] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the second reference label.

[0182] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips described above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0183] The various illustrative blocks and modules described herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0184] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Furthermore, as used herein, the word "or" included in the claims, such as in a list of items (for example, a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates a list of inclusions such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an instance step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0185] Computer-readable media includes both non-transitory computer storage media and communication media containing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is suitably referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The above combination also includes computer-readable media.

[0186] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for reading multi-level memory cells, comprising: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first or second recurrence event has occurred.

2. The method according to claim 1, further comprising: The logic states stored in the memory unit are identified as belonging to a first type that were disrupted after a sudden return event. and The memory cell is reprogrammed at least in part based on the recognition that the logical state includes the first type.

3. The method according to claim 1, further comprising: The logic state stored in the memory cell is identified, at least in part, as including a second type enhanced after the occurrence of the first backsliding event, based on the determination that the first backsliding event has occurred.

4. The method of claim 1, further comprising: It is determined that the memory cell is thresholded after the first read voltage is applied; and The occurrence of the first backlash event is determined at least in part based on the fact that the memory cell is thresholded after the first read voltage is applied.

5. The method of claim 1, wherein the first polarity includes a negative polarity and the second polarity includes a positive polarity.

6. The method of claim 1, wherein the magnitude of the first read voltage is similar to the magnitude of the second read voltage.

7. A method for reading multi-level memory cells, comprising: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the first polarity and an amount greater than the second read voltage is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

8. The method of claim 7, further comprising: The occurrence of the third sudden return event has been confirmed; and After determining the logical state stored in the memory cell based at least in part on the occurrence of the third relapse event, a reprogramming operation is performed on the memory cell.

9. The method of claim 8, further comprising: The reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes a first type, wherein the reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes the first type.

10. The method of claim 7, further comprising: It was determined that the aforementioned third recurrence event did not occur; and The reprogramming operation on the memory cell is avoided at least in part based on the determination that the third recurrence event did not occur.

11. A method for reading multi-level memory cells, further comprising: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the second polarity and a magnitude greater than the second read voltage is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

12. The method of claim 11, further comprising: The occurrence of the third sudden return event has been confirmed; and After determining the logical state stored in the memory cell based at least in part on the occurrence of the third relapse event, a reprogramming operation is performed on the memory cell.

13. The method of claim 12, further comprising: The reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes a first type, wherein the reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes the first type.

14. The method of claim 11, further comprising: It was determined that the aforementioned third recurrence event did not occur; and The reprogramming operation on the memory cell is avoided at least in part based on the determination that the third recurrence event did not occur.

15. A method for reading multi-level memory cells, comprising: A first read voltage having a first polarity and a first magnitude is applied to a memory cell to determine the logic states stored by the memory cell configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first return event has not occurred, a second read voltage having the first polarity and the second magnitude is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second sudden return event has not occurred, a third read voltage having the first polarity and the third magnitude is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

16. The method of claim 15, further comprising: The occurrence of the third sudden return event has been confirmed; and After determining the logical state stored in the memory cell based at least in part on the occurrence of the third relapse event, a reprogramming operation is performed on the memory cell.

17. The method of claim 16, further comprising: The reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes a first type, wherein the reprogramming operation is performed based at least in part on the determination that the logical state stored in the memory cell includes the first type.

18. The method of claim 15, further comprising: It was determined that the aforementioned third recurrence event did not occur; and The reprogramming operation on the memory cell is avoided at least in part based on the determination that the third recurrence event did not occur.

19. The method of claim 15, further comprising: The second sudden return event has been confirmed; and The memory cell is reprogrammed at least in part based on the determination that the second backsliding event has occurred, wherein the determination of the logical state stored in the memory cell is at least in part based on the determination that the second backsliding event has occurred.

20. The method of claim 19, further comprising: The logic state stored in the memory cell is identified as including a first type that was disturbed after the occurrence of the second backsliding event, at least in part based on the determination that the second backsliding event has occurred, wherein the reprogramming operation on the memory cell is performed at least in part based on the identification that the logic state includes the first type.

21. The method of claim 15, further comprising: The logic state stored in the memory cell is identified, at least in part, as including a second type enhanced after the occurrence of the first backsliding event, based on the determination that the first backsliding event has occurred.

22. The method of claim 15, further comprising: It is determined that the memory cell is thresholded after the first read voltage is applied; and The occurrence of the first backlash event is determined at least in part based on the fact that the memory cell is thresholded after the first read voltage is applied.

23. The method of claim 15, wherein the first polarity comprises a negative polarity.

24. The method of claim 15, wherein the second value is greater than the first value, and wherein the third value is greater than the second value.

25. A device for reading multi-level memory cells, comprising: A memory array, comprising memory cells; and A control component, coupled to the memory array, is configured to cause the device to: A first read voltage of first polarity is applied to the memory cell to determine the logic states stored by the memory cell configured to store three or more logic states; Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first or second recurrence event has occurred.

26. An apparatus for reading multi-level memory cells, comprising: A memory array, comprising memory cells; and A control component, coupled to the memory array, is configured to cause the device to: A first read voltage of first polarity is applied to the memory cell to determine the logic states stored by the memory cell configured to store three or more logic states; Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the first polarity and an amount greater than the second read voltage is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

27. The device of claim 26, wherein the control component is further configured to cause the device to: It is determined that the third sudden return event has occurred; and After determining the logical state stored in the memory cell based at least in part on the occurrence of the third relapse event, a reprogramming operation is performed on the memory cell.

28. A device for reading multi-level memory cells, comprising: A memory array, comprising memory cells; and A control component, coupled to the memory array, is configured to cause the device to: A first read voltage of first polarity is applied to the memory cell to determine the logic states stored by the memory cell configured to store three or more logic states; Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the second polarity and a magnitude greater than the second read voltage is applied to the memory cell; Determine whether a third back-end event occurs after the third read voltage is applied and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

29. A device for reading multi-level memory cells, comprising: A memory array, comprising memory cells; and A control component, coupled to the memory array, is configured to cause the device to: A first read voltage having a first polarity and a first magnitude is applied to the memory cell to determine the logic states stored by the memory cell configured to store three or more logic states; Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first return event has not occurred, a second read voltage having the first polarity and the second magnitude is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second sudden return event has not occurred, a third read voltage having the first polarity and the third magnitude is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory unit is determined at least in part based on whether the first, second, or third sudden return event has occurred.

30. The device of claim 29, wherein the control component is further configured to cause the device to: It is determined that the third sudden return event has occurred; and After determining the logical state stored in the memory cell based at least in part on the occurrence of the third relapse event, a reprogramming operation is performed on the memory cell.

31. The device of claim 29, wherein the control component is further configured to cause the device to: It was determined that the aforementioned third sudden return event did not occur; and The reprogramming operation on the memory cell is avoided at least in part based on the determination that the third recurrence event did not occur.

32. The device of claim 29, wherein the control component is further configured to cause the device to: It is determined that the second sudden return event has occurred; and The memory cell is reprogrammed at least in part based on the determination that the second backsliding event has occurred, wherein the determination of the logical state stored in the memory cell is at least in part based on the determination that the second backsliding event has occurred.

33. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; and The logical state stored in the memory cell is determined at least in part based on whether the second sudden return event has occurred.

34. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the first polarity and an amount greater than the second read voltage is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory cell is determined at least in part based on whether the third sudden return event has occurred.

35. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: A first read voltage of first polarity is applied to a memory cell to determine the logic states stored by the memory cell, which is configured to store three or more logic states. Determine whether a first backslip event occurs after the first read voltage is applied; At least in part based on the determination that the first back-in event failed to occur, a second read voltage with a second polarity is applied to the memory cell; Determine whether a second backslip event occurs after the second read voltage is applied; At least in part based on the determination that the second back-in event has not occurred, a third read voltage having the second polarity and a magnitude greater than the second read voltage is applied to the memory cell; Determine whether a third backslip event occurs after the third read voltage is applied; and The logical state stored in the memory cell is determined at least in part based on whether the third sudden return event has occurred.

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