camera device

Abstract

[Problem] To provide an imaging device having low noise and high dynamic range. [Solution] An imaging device includes: a conversion unit that converts an incident electromagnetic wave into an electric charge; a first capacitor that accumulates the electric charge when a voltage corresponding to the electric charge is equal to or lower than a predetermined threshold value; a second capacitor that accumulates the electric charge when the voltage exceeds the threshold value; a voltage conversion circuit that converts the electric charge accumulated in the first capacitor and the second capacitor into a voltage; a first storage unit that stores a voltage corresponding to the accumulated electric charge in the first capacitor after a first period elapses since the first capacitor starts to accumulate the electric charge; and a second storage unit that stores a voltage corresponding to the accumulated electric charges in the first capacitor and the second capacitor after a second period longer than the first period elapses since the first capacitor starts to accumulate the electric charge.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] Imaging devices that capture electromagnetic waves such as incident radiation require low noise performance, high speed, and high dynamic range. Patent Document 1 discloses an X-ray detector equipped with an integrating capacitor to perform signal reading and integration operations in parallel. Patent Document 2 discloses a computed tomography apparatus that determines the gain of the next frame based on the output value in the current frame by utilizing the fact that the changes between frames are small. Patent Document 3 discloses a radiation imaging system in which a noise output line is added and voltage values ​​with high and low conversion gains are stored in the pixels.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-503325

[0006] Patent Document 2: Japanese Patent Application Publication No. 2002-533691

[0007] Patent Document 3: Japanese Patent Application Publication No. 2016-82255 Summary of the Invention

[0008] The problem to be solved by the present invention

[0009] In the X-ray detector of Patent Document 1, the integrating capacitor has a fixed capacitance and saturates at high doses, thus causing a problem in the inability to correctly detect X-ray doses.

[0010] The tomographic imaging device in Patent Document 2 can switch the capacitance of the feedback capacitor, but because it selects the feedback capacitor for the next frame based on the current output value, it is difficult to cope with sudden changes in the input signal. Furthermore, the use of a feedback amplifier presents a problem for high-speed operation.

[0011] The radiation imaging system in Patent Document 3 has a switching switch for "broad coverage," but if a high dose is input before the switching switch, the circuit saturates, causing the charge serving as the signal to disappear. Furthermore, there is a limitation on the exposure time within a single frame.

[0012] In view of the above-mentioned problems in related technologies, this disclosure provides a camera device with low noise, high speed and high dynamic range.

[0013] Technical solutions to the problem

[0014] To address the aforementioned problems, according to this disclosure, a camera device is provided, comprising:

[0015] A conversion unit that converts incident electromagnetic waves into electrical charges;

[0016] A first capacitor accumulates the charge when the voltage corresponding to the charge is equal to or lower than a predetermined threshold.

[0017] A second capacitor accumulates the charge when the voltage exceeds the threshold.

[0018] A voltage conversion circuit that converts the charge accumulated in the first capacitor and the second capacitor into voltage;

[0019] A first storage cell, after a first cycle since the first capacitor began accumulating charge, stores a voltage corresponding to the accumulated charge in the first capacitor; and

[0020] The second storage cell stores a voltage corresponding to the accumulated charge in the first capacitor and the second capacitor after a second period longer than the first period since the first capacitor began accumulating the charge.

[0021] It may also provide: a third storage unit, which stores a voltage corresponding to the accumulated charge in the first capacitor after the first cycle has elapsed since the first capacitor began accumulating the charge; and

[0022] The fourth storage cell, after the second cycle has elapsed since the first capacitor began accumulating the charge, stores the voltage corresponding to the accumulated charge in the first capacitor and the second capacitor.

[0023] This allows the corresponding voltages to be stored in the first and second memory cells respectively during a predetermined frame period, while the voltages stored in the third and fourth memory cells during the frame period immediately preceding the predetermined frame period are output to the signal line.

[0024] While storing corresponding voltages in the third and fourth storage cells in a frame period immediately following the predetermined frame period, the voltages stored in the first and second storage cells in the predetermined frame period are output to the signal line.

[0025] It may also provide: a first reset circuit that discharges the accumulated charge in the first capacitor and the second capacitor to initialize; and

[0026] The fifth storage unit stores the initialization voltage when the first capacitor and the second capacitor are initialized.

[0027] A first transmission circuit may also be provided, which outputs the differential voltage between the voltage stored in the second storage unit and the voltage stored in the fifth storage unit to a signal line each frame period.

[0028] A sixth storage unit may also be provided, which stores the voltage of the path connected to the first reset circuit when the initialization performed by the first reset circuit is deactivated.

[0029] A second transmission circuit may also be provided, which outputs the differential voltage between the voltage stored in the first storage cell and the voltage stored in the sixth storage cell to the signal line each frame period.

[0030] A first voltage limiter may also be provided, which cuts off the accumulation of the charge in the second capacitor when the voltage corresponding to the charge is equal to or lower than the threshold, and allows the charge to accumulate in the second capacitor when the voltage exceeds the threshold.

[0031] A mode selection unit may also be provided, which selects whether to store the voltage corresponding to the accumulated charge of one of the first capacitor and the second capacitor in the second storage unit, or to store the voltage corresponding to the accumulated charge of the first capacitor and the second capacitor in the second storage unit.

[0032] It may also provide: a sample-and-hold circuit that samples and holds the voltage of a signal line at a predetermined period, the signal line sequentially transmitting voltages stored in the first memory cell and the second memory cell; and

[0033] An AD converter converts the voltage sampled and held by the sample-and-hold circuit into a digital signal.

[0034] It may also provide: a first holding circuit that holds one of the voltages stored in the first memory cell and the voltages stored in the second memory cell; and

[0035] The second holding circuit holds another voltage between the voltage stored in the first storage cell and the voltage stored in the second storage cell.

[0036] It may also provide: a judgment circuit that, based on digital signals held in the first holding circuit and the second holding circuit, determines whether the accumulated charge in the first capacitor is saturated; and

[0037] The selection circuit selects and outputs the digital signal held in the first holding circuit or the second holding circuit based on the judgment result of the judgment circuit.

[0038] The AD converter may include:

[0039] A ramp selector selects a first ramp voltage when the voltage held in the sample-and-hold circuit is equal to or higher than a predetermined reference voltage, and selects a second ramp voltage when the voltage held in the sample-and-hold circuit is lower than the reference voltage. Compared with the first ramp voltage, the second ramp voltage has a smaller voltage amplitude variation width and a lower voltage change rate over time.

[0040] The comparison unit compares the voltage held in the sample-and-hold circuit with either the first ramp voltage or the second ramp voltage; and

[0041] A counter that generates the digital signal based on the comparison result of the comparison unit.

[0042] Multiple pixel circuits connected to the signal lines can also be provided.

[0043] The pixel circuit includes the conversion unit, the first capacitor, the second capacitor, the first storage unit, and the second storage unit.

[0044] The sample-and-hold circuit sequentially holds the voltages output from the plurality of pixel circuits during a frame period.

[0045] A mode selection unit may also be provided, which can select a predetermined mode for expanding the dynamic range.

[0046] This results in the length of the first period being shorter in one of two consecutive frame periods compared to the length of the first period in the other frame period when the predetermined mode is selected, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage unit is limited.

[0047] During one frame cycle, after the first capacitor and the second capacitor begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first capacitor and the second capacitor can be temporarily discharged. Afterward, the accumulation of charge can resume.

[0048] The second storage unit may store, during the frame period, a voltage corresponding to the accumulated charge after the accumulation of charge has restarted in the first and second capacitors.

[0049] A mode selection unit may also be provided, which can select a predetermined mode for expanding the dynamic range.

[0050] This causes the length of the first period to be shorter in one of two consecutive frame periods compared to the length of the first period in the other frame period when the predetermined mode is selected, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage unit and the fourth storage unit is limited.

[0051] During one frame cycle, after the first capacitor and the second capacitor begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first capacitor and the second capacitor can be temporarily discharged. Afterward, the accumulation of charge can resume.

[0052] The fourth storage unit can store, during the frame period, the voltage corresponding to the accumulated charge after the first capacitor and the second capacitor have restarted the accumulation of charge. Attached Figure Description

[0053] Figure 1 This is a block diagram illustrating a schematic structure of a camera device according to the first embodiment.

[0054] Figure 2 This is a cross-sectional view of the camera device according to this embodiment.

[0055] Figure 3 It is shown Figure 1 The circuit diagram shows an example of the specific circuit construction of the pixel circuit.

[0056] Figure 4 yes Figure 3 Timing diagram of the pixel circuit.

[0057] Figure 5 This is a block diagram showing the structure of the camera device on the back stage of the signal line.

[0058] Figure 6 This is a timing diagram of the ADC and logic circuit when the logic circuit includes only a hold circuit instead of a decision circuit.

[0059] Figure 7 This is a timing diagram of the ADC and logic circuit when the logic circuit includes a decision circuit, a first hold circuit, and a second hold circuit.

[0060] Figure 8 This is a timing diagram of the ADC and logic circuit with a fixed gain in the pixel circuit and a hold circuit in the logic circuit.

[0061] Figure 9 This is a timing diagram with a fixed gain in the pixel circuit and the logic circuit having a first hold circuit and a second hold circuit.

[0062] Figure 10 This is a detailed timing diagram illustrating the operation of the camera device according to this embodiment.

[0063] Figure 11 This is a timing diagram of the pixel circuit according to the second embodiment. Detailed Implementation

[0064] In the following description, embodiments of the camera device will be illustrated with reference to the accompanying drawings. Although the following description will focus on the main components of the camera device, the camera device may also have components and functions that are not shown or not described. The following description does not exclude components or functions that are not shown or not described.

[0065] (First Embodiment)

[0066] Figure 1 This is a block diagram illustrating a schematic structure of the camera device 1 according to the first embodiment. Figure 1 The imaging device 1 captures images of electromagnetic waves in a predetermined frequency band. In the following description, although the imaging device 1 for detecting X-rays (also referred to as an X-ray detection device) will be used as a specific example, this embodiment is also applicable to frequency bands other than X-rays.

[0067] Figure 1 The imaging device 1 includes a pixel array unit 1a and a peripheral circuit unit 1b. The pixel array unit 1a includes multiple pixel circuits 2 arranged along the horizontal direction X and the vertical direction Y, multiple signal lines VSL extending along the vertical direction Y, and multiple scan lines (not shown) extending along the horizontal direction X. The peripheral circuit unit 1b includes a scan line drive circuit (V_Driver) 4, a pseudo-source follower circuit (hereinafter referred to as DSF circuit) 5, a sample and hold circuit (hereinafter referred to as S / H circuit) 6, an analog-to-digital converter circuit (hereinafter referred to as ADC) 7, a logic circuit 8, and an interface circuit (IF circuit) 9.

[0068] exist Figure 1In the imaging device 1, the number of pixel circuits 2 and the number of signal lines VSL are freely set. The pixel array unit 1a and the peripheral circuit unit 1b can be formed on the same substrate, or as described later, at least a portion of the peripheral circuit unit 1b can be formed on a different substrate than the substrate on which the pixel array unit 1a is formed.

[0069] Pixel circuit 2 includes a photodiode and a readout circuit. The specific construction and operation of pixel circuit 2 will be described later. Multiple pixel circuits 2 arranged along the vertical Y direction are connected to multiple signal lines VSL. More specifically, multiple pixel circuits 2 arranged at intervals in the vertical direction are connected to a single signal line VSL. Each signal line VSL transmits the image signal captured by the multiple pixel circuits 2 in a frame.

[0070] The DSF circuit 5 sets the reference potential of the comparator in the ADC 7 (described later). The S / H circuit 6 periodically samples and holds the voltage of each signal line VSL. The ADC 7 converts the sampled and held voltages into digital signals. The logic circuit 8 sequentially holds the digital signals after the AD conversion. The IF circuit 9 outputs the digital signals held in the logic circuit 8.

[0071] Figure 2 This is a cross-sectional view of the camera device 1 according to this embodiment. Figure 2 As shown, the imaging device 1 according to this embodiment is obtained by bonding the first substrate 11 and the second substrate 12 together using Cu-Cu bonding, through-holes, or bumps. A plurality of pixel circuits 2 are formed in a portion of the first substrate 11 (pixel region) 11a. The first substrate 11, for example, has a photoelectric conversion region (photodiode) 13 formed by implanting and diffusing impurity ions into a floating region (FZ) silicon substrate. The photoelectric conversion region 13 includes a cathode (n) formed on the upper surface side. + Cathode layer 14 and anode (p) formed on the lower surface side + Anode layer 15 and ground layer (GND) 10.

[0072] An X-ray shielding plate 16 is disposed above the area (peripheral circuit area) 11b outside the pixel area 11a of the first substrate 11. On the second substrate 12 located below the X-ray shielding plate 16, a wiring layer 17 connected to the pixel circuit 2 and other components such as wiring circuitry are formed. Figure 1 The peripheral circuits 18 of the DSF circuit 5, S / H circuit 6, ADC 7, and IF circuit 9 are shown. A protective ring 19 is arranged on the lower surface of the peripheral circuit region 11b of the photoelectric conversion region 13, and a cathode (n) is formed on the outer periphery of the protective ring 19. + (Cathode layer) 14.

[0073] Figure 3 It is shown Figure 1 The circuit diagram shows an example of the specific circuit construction of pixel circuit 2. Figure 3 The circuit structure of pixel circuit 2 is shown. For example... Figure 3 As shown, the pixel circuit 2 includes a conversion unit 21, a first capacitor C0, a second capacitor C1, a voltage buffer 22, a first storage unit 23, and a second storage unit 24. Figure 3 The pixel circuit 2 shown includes multiple transistors. Figure 3 An example is shown where multiple transistors are constructed entirely using PMOS transistors, but multiple transistors can also be constructed entirely using NMOS transistors.

[0074] The conversion unit 21 is a photodiode 13 that converts incident electromagnetic waves (X-rays) into electrical charges. A first capacitor C0 and a second capacitor C1 constitute the conversion capacitor C, and a charge corresponding to the incident intensity of the X-rays accumulates in at least one of the first capacitor C0 and the second capacitor C1. In the first capacitor C0 and the second capacitor C1, the voltage between the two electrodes of each capacitor increases with the amount of accumulated charge. The first capacitor C0 accumulates charge when the voltage corresponding to the charge is equal to or below a predetermined threshold. The second capacitor C1 accumulates charge when the voltage corresponding to the charge exceeds the threshold.

[0075] Thus, when the incident intensity of X-rays is not too high, the first capacitor C0 accumulates charge, and when the accumulated charge in the first capacitor C0 increases to a certain level, the second capacitor C1 begins to accumulate charge.

[0076] Voltage buffer 22 is a voltage conversion circuit that converts the charge accumulated in the first capacitor C0 and the second capacitor C1 into voltage. Voltage buffer 22 includes transistor Q3. Current source 25 is connected between the source of transistor Q3 and the power supply voltage node. The anode of photodiode 13, one end of the first capacitor C0, and one end of the second capacitor C1 are connected to the gate of transistor Q3. The drain of transistor Q3 is connected to the ground node. The source voltage of transistor Q3 varies according to the accumulated charge in the first capacitor C0 and the second capacitor C1.

[0077] After a first cycle has elapsed since the first capacitor C0 began accumulating charge, the first storage cell 23 stores the voltage corresponding to the accumulated charge in the first capacitor C0. In this embodiment, it is assumed that exposure and voltage transfer to the signal line VSL occur within one frame cycle, and the first cycle is a period within one frame cycle.

[0078] The first storage cell 23 includes, for example, a capacitor Cs1 and a transistor Q1. The capacitor Cs1 is connected between the drain of the transistor Q1 and a reference voltage node (e.g., a ground node). A signal S1 is input to the gate of the transistor Q1.

[0079] After a second cycle, longer than the first cycle, since the first capacitor C0 began accumulating charge, the second storage cell 24 stores the voltage corresponding to the accumulated charge in the first capacitor C0 and the second capacitor C1. The second cycle is a period within a frame cycle.

[0080] The second storage cell 24 includes, for example, a transistor Q2 and a capacitor Cs2. The capacitor Cs2 is connected between the drain of transistor Q2 and the ground node. The signal S2 is input to the gate of transistor Q2.

[0081] like Figure 3 As shown, the pixel circuit 2 according to this embodiment may include a first voltage limiter 26. When the voltage corresponding to the charge is equal to or below a threshold, the first voltage limiter 26 cuts off the accumulation of charge in the second capacitor C1, and when the voltage exceeds the threshold, the first voltage limiter 26 allows the charge to accumulate in the second capacitor C1. The first voltage limiter 26 includes, for example, a transistor Q6. A voltage V1 is input to the gate of the transistor Q6. The drain of the transistor Q6 is connected to one end of the second capacitor C1, and the source of the transistor Q6 is connected to the anode of the photodiode 13 and one end of the first capacitor C0. By controlling the gate voltage V1 of the transistor Q6, the anode voltage of the photodiode 13 when the second capacitor C1 begins to accumulate charge can be controlled.

[0082] like Figure 3 As shown, the pixel circuit 2 according to this embodiment may include a third storage unit 27 and a fourth storage unit 28. Similar to the first storage unit 23, after a first cycle since the first capacitor C0 began accumulating charge, the third storage unit 27 stores the voltage corresponding to the accumulated charge in the first capacitor C0.

[0083] Similar to the second storage cell 24, after a second cycle longer than the first cycle since the first capacitor C0 began accumulating charge, the fourth storage cell 28 stores the voltage corresponding to the accumulated charge in the first capacitor C0 and the second capacitor C1.

[0084] like Figure 3As shown, the pixel circuit 2 according to this embodiment can include: a first system unit 29 including a first storage unit 23 and a second storage unit 24; and a second system unit 30 including a third storage unit 27 and a fourth storage unit 28. Therefore, while the voltage corresponding to the charge accumulated in the first capacitor C0 and the second capacitor C1 due to exposure is stored in the first storage unit 23 and the second storage unit 24 of the first system unit 29, the exposure result of the previous frame stored in the third storage unit 27 and the fourth storage unit 28 of the second system unit 30 can be output to the signal line VSL. Furthermore, while the voltage stored in the first storage unit 23 and the second storage unit 24 of the first system unit 29 is output to the signal line VSL, the voltage corresponding to the charge accumulated in the first capacitor C0 and the second capacitor C1 due to exposure can be stored in the third storage unit 27 and the fourth storage unit 28 of the second system unit 30. Therefore, Figure 3 The pixel circuit 2 in the middle can be exposed for most of a frame period.

[0085] like Figure 3 As shown, the pixel circuit 2 according to this embodiment may include a first reset circuit 31 and a fifth storage unit 32. The first reset circuit 31 discharges and initializes the accumulated charge in the first capacitor C0 and the second capacitor C1. The first reset circuit 31 includes, for example, a transistor Q4. The source of transistor Q4 is connected to the anode of photodiode 13, one end of the first capacitor C0, one end of the second capacitor C1, and the gate of transistor Q3 in voltage buffer 22. The drain of transistor Q4 is connected to a ground node. When the signal RST input to the gate of transistor Q4 is low, transistor Q4 is turned on to perform an initialization operation.

[0086] The fifth storage cell 32 stores the initialization voltage when the first capacitor C0 and the second capacitor C1 are initialized. The fifth storage cell 32 includes, for example, a transistor Q5 and a capacitor Ccds2. One end of the capacitor Ccds2 is connected to the drain of the transistor Q2, and the other end of the capacitor Ccds2 is connected to the source of the transistor Q5. The drain of the transistor Q5 is connected to a ground node. A signal S4 is input to the gate of the transistor Q5.

[0087] like Figure 3As shown, the pixel circuit 2 according to this embodiment may include a first transmission circuit 33. Each frame cycle, the first transmission circuit 33 outputs the differential voltage between the voltage stored in the second storage cell 24 and the voltage stored in the fifth storage cell 32 to the signal line VSL. The first transmission circuit 33 includes, for example, common-source and common-gate transistors Q7 and Q8. The source of transistor Q7 is connected to the output node of pixel circuit 2, and its drain is connected to the source of transistor Q8. The drain of transistor Q8 is connected to a ground node. The signal SEL2 is input to the gate of transistor Q7. The gate of transistor Q8 is connected to the other end of capacitor Ccds2 and the source of transistor Q5.

[0088] like Figure 3 As shown, the pixel circuit 2 according to this embodiment may include a sixth storage unit 34. The sixth storage unit 34 stores the voltage of the charge transport path immediately after the initialization performed by the first reset circuit 31 is released. When the first reset circuit 31 releases the reset, the sixth storage unit 34 stores kTC noise. The sixth storage unit 34 includes, for example, a transistor Q9 and a capacitor Ccds1. The capacitor Ccds1 is connected between the drain of transistor Q1 and the source of transistor Q9. The drain of transistor Q9 is connected to a ground node. A signal S3 is input to the gate of transistor Q9.

[0089] like Figure 3 As shown, the pixel circuit 2 according to this embodiment may include a second transmission circuit 35. Each frame cycle, the second transmission circuit 35 outputs the differential voltage between the voltage stored in the first storage cell 23 and the voltage stored in the sixth storage cell 34 to the signal line VSL. The second transmission circuit 35 includes, for example, common-source and common-gate transistors Q10 and Q11. The source of transistor Q10 is connected to the output node of pixel circuit 2. The drain of transistor Q10 is connected to the source of transistor Q11. The drain of transistor Q11 is connected to ground. The signal SEL1 is input to the gate of transistor Q10. The gate of transistor Q11 is connected to the other end of capacitor Ccds1 and the source of transistor Q9.

[0090] so, Figure 3 The first system unit 29 in the pixel circuit 2 includes transistors Q1, Q2, Q5, and Q7-Q11, and capacitors Cs1, Cs2, Ccds1, and Ccds2. Furthermore, the second system unit 30, having the same circuit structure as the first system unit 29, includes transistors Q12-Q19 and capacitors Cs3, Cs4, Ccds3, and Ccds4. As described above, the first system unit 29 and the second system unit 30 alternately perform exposure or voltage transfer to the signal line VSL in each frame period.

[0091] Figure 4 yes Figure 3 The timing diagram of pixel circuit 2 is shown below. (Refer to the following text.) Figure 4 illustrate Figure 3 The operation of pixel circuit 2 in the middle.

[0092] First, at time t1, the signal RST goes low, turning on transistor Q4 in the first reset circuit 31, and the voltage V1 goes low, turning on transistor Q6 in the first voltage limiter 26. Therefore, the first capacitor C0 and the second capacitor C1, connected to the sources of transistors Q6 and Q4, discharge the accumulated charge to initialize the circuit. At this time, signals S2 and S4 are low, so transistor Q2 in the second storage cell 24 and transistor Q5 in the fifth storage cell 32 turn on, and the charge corresponding to the reset potential accumulates in capacitor Ccds2.

[0093] Subsequently, at time t2, signal S4 goes high, causing transistor Q5 to turn off. Therefore, capacitor Ccds2 stores the reset potential obtained when the first reset circuit 31 initializes the first capacitor C0 and the second capacitor C1.

[0094] Subsequently, at time t3, according to the gain switching mode, the gate voltage of transistor Q6 in the first voltage limiter 26 is set to voltage level Vm. For example, in order to operate the pixel circuit 2 in a mode that can switch between two gains (hereinafter referred to as "two-gain mode"), the gate voltage Vm of transistor Q6 is preset such that transistor Q6 turns on when a certain amount of current flows through the anode of photodiode 13. In this case, transistor Q6 turns on when the anode voltage of photodiode 13 exceeds Vm + Vth. On the other hand, in order to operate the pixel circuit 2 in a fixed gain mode, the high-voltage gate voltage Vm is set so that transistor Q6 is always off.

[0095] Subsequently, at time t4, the signal RST goes high, transistor Q4 in the first reset circuit 31 turns off, and the reset is released. After time t4, the charge converted by photodiode 13 accumulates in the first capacitor C0, and according to the accumulated charge, the charge also accumulates in capacitor Cs1.

[0096] Subsequently, at time t5, signal S3 goes high, transistor Q9 in the sixth storage cell 34 is turned off, and the kTC noise generated when the first reset circuit 31 is released is stored in capacitor Ccds1.

[0097] Subsequently, at time t6, signal S1 goes high, causing transistor Q1 in the first storage cell 23 to turn off. Therefore, the voltage corresponding to the accumulated charge in the first capacitor C0 is stored in capacitor Cs1 in the first storage cell 23. The exposure time using the first capacitor C0 is between time t5 and time t6. In the following text, the gain when exposure is performed using only the first capacitor C0 is referred to as the high conversion gain C0.

[0098] At time t7, by reducing the gate voltage of transistor Q6 in the first voltage limiter 26, transistor Q6 is fully turned on, and both the first capacitor C0 and the second capacitor C1 accumulate charge from photodiode 13.

[0099] Subsequently, at time t8, signal S2 goes high, causing transistor Q2 in the second storage cell 24 to turn off. Therefore, the voltage corresponding to the accumulated charge in the first capacitor C0 and the second capacitor C1 is accumulated in capacitor Cs2 in the second storage cell 24. The exposure time using the first capacitor C0 and the second capacitor C1 is between time t4 and time t8. In the following text, the gain when exposure is performed using the first capacitor C0 and the second capacitor C1 is referred to as the low conversion gain (C0+C1).

[0100] When the anode voltage of photodiode 13 becomes Vm+Vth, transistor Q6 turns on, thus limiting the voltage at Vm+Vth. Therefore, by appropriately setting the gate voltage Vm of transistor Q6, saturation of pixel circuit 2 can be avoided. Furthermore, a high dynamic range of conversion gain C0 can be ensured before the anode voltage of photodiode 13 becomes Vm+Vth.

[0101] When the anode voltage of photodiode 13 exceeds Vm+Vth, the charge from photodiode 13 is accumulated in the second capacitor C1. Therefore, there is no possibility that the charge from photodiode 13 will disappear. By turning on transistor Q6 in the first voltage limiter 26 at time t7, the charge accumulated in the first capacitor C0 and the second capacitor C1 can be converted into voltage with a low conversion gain (C0+C1).

[0102] In this way, within an exposure time period of approximately the same length, it is possible to obtain a voltage with high conversion gain C0 and a voltage with low conversion gain (C0+C1), and the dynamic range can be expanded. In the case of photoelectric conversion with high conversion gain C0, the signal-to-noise ratio (S / N) is crucial; therefore, by canceling the kTC noise during reset, noise can be reduced, and a single photon of the X-ray can be accurately detected.

[0103] For example, from Figure 4 From time t1 to time t8, Figure 3 In the pixel circuit 2, the first system unit 29 performs an exposure operation, and during the exposure operation, the second system unit 30 outputs the voltage stored in the third storage unit 27 and the fourth storage unit 28 due to exposure in the previous frame to the signal line VSL. More specifically, at time t1, transistor Q18 is turned on, and the voltage obtained by subtracting the kTC noise stored in capacitor Ccds3 from the voltage stored in capacitor Cs3 in the third storage unit 27 after photoelectric conversion with high conversion gain C0 in the previous frame is output to the signal line VSL. Subsequently, at time t5, the voltage obtained by subtracting the reset potential stored in capacitor Ccds4 at reset time from the voltage stored in capacitor Cs4 in the fourth storage unit 28 with low conversion gain (C0+C1) in the previous frame is output to the signal line VSL.

[0104] Subsequently, in the next frame shown from time t8 to time t15, the second system unit 30 performs exposure, and the voltages stored in the first storage unit 23 and the second storage unit 24 in the previous frame (times t1 to t8) are output to the signal line VSL. More specifically, at time t9, the voltage of the charge transport path at reset is stored in capacitor Ccds4. Subsequently, at time t11, the voltage of kTC noise is stored in capacitor Ccds3. Subsequently, at time t13, the voltage with high conversion gain C0 is stored in capacitor Cs3. Subsequently, at time t15, the voltage with low conversion gain (C0+C1) is stored in capacitor Cs4.

[0105] Furthermore, when the second system unit 30 performs exposure from time t8 to time t15, at time t8, transistor Q10 in the first system unit 29 is turned on, and a voltage obtained by subtracting the voltage of kTC noise stored in capacitor Ccds1 from the voltage stored in capacitor Cs1 with high conversion gain C0 is output to signal line VSL. Furthermore, after time t12, transistor Q7 is turned on, and a voltage obtained by subtracting the reset voltage stored in capacitor Ccds2 from the voltage stored in capacitor Cs2 with low conversion gain (C0+C1) is output to signal line VSL.

[0106] Figure 5 This is a block diagram showing the configuration of the imaging device 1 at the rear stage of the signal lines VSL. Multiple signal lines VSL are arranged along the horizontal direction X, and multiple pixel circuits 2 are connected to each signal line VSL. Voltages output from the multiple pixel circuits 2 in a frame are sequentially sent to the signal lines VSL. The multiple signal lines VSL simultaneously transmit the voltages output from each pixel circuit 2 in parallel.

[0107] DSF circuit 5 is connected to each signal line VSL. DSF circuit 5 operates once per frame and sets the potential of the corresponding signal line VSL as the reference potential. Therefore, the reference potential of the comparator in ADC7 is set.

[0108] Before the AD conversion is performed in ADC 7, the voltage of each signal line VSL is sampled and held by S / H circuit 6. In X-ray imaging, the image size of each pixel is large, and the length of the signal line VSL connected to the pixel circuit 2 is, for example, about 5 cm. Therefore, even if a certain pixel is selected to output voltage, it takes time to stabilize by a time constant due to the resistance or capacitance of the signal line VSL, thus reducing the number of AD conversions that can be performed in one frame. Therefore, in this embodiment, by providing S / H circuit on the front-end side of ADC 7, the stabilization time of the signal line voltage on the signal line VSL can be shortened.

[0109] The S / H circuit 6 samples and holds the voltage of each signal line VSL in each predetermined cycle. Each pixel circuit 2 outputs a voltage with high conversion gain C0 and a voltage with low conversion gain (C0+C1) to each signal line VSL at staggered times, and these voltages are sequentially sampled and held by the S / H circuit 6.

[0110] ADC 7 includes a comparator 41, a ramp selector 42, and a counter 43. Comparator 41 compares the sampled and held signal line voltage with the ramp voltage. Two types of ramp voltages and a reference voltage Vref are input to... Figure 5 The ADC7. In the following text, these two types of ramp voltages will be referred to as coarse ramp voltage (Coarse_ramp or first ramp voltage) and fine ramp voltage (Fine_ramp or second ramp voltage). Compared to coarse ramp voltage, fine ramp voltage has a smaller voltage amplitude variation width and a lower rate of change of voltage over time. Figure 5 The comparator 41 and ramp selector 42 in the ADC 7 compare the sampled and held signal line voltage with the reference voltage Vref. When the signal line voltage is higher than the reference voltage Vref, a coarse ramp voltage is selected, and when the signal line voltage is equal to or lower than the reference voltage Vref, a fine ramp voltage is selected.

[0111] Comparator 41 compares the signal line voltage with either a coarse ramp voltage or a fine ramp voltage, and counter 43 counts the period from the sampling and holding time to the moment when the signal line voltage and the coarse ramp voltage or fine ramp voltage intersect. The count value of counter 43 is a digital signal obtained by performing an AD conversion on the signal line voltage.

[0112] The logic circuit 8 includes a first multiplexer (MUX) 44, a decision circuit 45, a first hold circuit (Latch 1) 46, a second hold circuit (Latch 2) 47, and a second multiplexer (MUX) 48.

[0113] The first multiplexer 44 divides the digital signal output from the counter 43 into two systems and outputs them in parallel.

[0114] The judgment circuit 45 determines whether to output a digital signal with high conversion gain C0 or a digital signal with low conversion gain (C0+C1). If the digital signal with high conversion gain is saturated, the judgment circuit 45 determines to output a digital signal with low conversion gain (C0+C1); if the digital signal with high conversion gain is not saturated, the judgment circuit 45 determines to output a digital signal with high conversion gain C0.

[0115] The first holding circuit 46 or the second holding circuit 47 latches the digital signal based on the judgment result in the judgment circuit 45. An idle holding circuit is selected from the first holding circuit 46 and the second holding circuit 47 to latch the digital signal. The digital signal latched by the first holding circuit 46 and the second holding circuit 47 is sent to the IF circuit 9 via the second multiplexer 48. The second multiplexer 48 controls whether to send the digital signal latched by the first holding circuit 46 and the second holding circuit 47 to the IF circuit 9 based on the judgment result of the judgment circuit 45.

[0116] The IF circuit 9 outputs the digital signal latched by the first holding circuit 46 or the second holding circuit 47 to the outside.

[0117] Since pixel circuit 2 sequentially outputs voltages with high conversion gain C0 and low conversion gain (C0+C1) to signal line VSL, if logic circuit 8 outputs all digital signals corresponding to the voltages with high conversion gain C0 and low conversion gain (C0+C1) from all pixel circuits 2, the number of digital signals to be output would be too large, which would degrade the imaging operation of camera device 1. Therefore, by setting as follows... Figure 5 The judgment circuit 45 shown outputs only valid digital signals, which can speed up the camera operation of the camera device 1.

[0118] Furthermore, if the digital signal output from counter 43 has n bits, then HG / LG discriminator 49 can determine whether the digital signal has a high conversion gain C0 or a low conversion gain (C0+C1), add 1 bit to the determination result, and output a (n+1) bit digital signal from IF circuit 9. Therefore, it is easy to identify whether the digital signal has a high conversion gain C0 or a low conversion gain (C0+C1).

[0119] like Figure 5 As shown, since multiple pixel circuits 2 are connected to a single signal line VSL, the signal line voltages with high conversion gain C0 and low conversion gain (C0+C1) output from each pixel circuit 2 are transmitted sequentially within a frame period. For example, in the case where four pixel circuits 2 are connected to a single signal line VSL, eight (2×4=8) signal line voltages are transmitted through the signal line VSL within a frame period, and the ADC 7 performs eight AD conversions within a frame period.

[0120] In this embodiment, as Figure 4 As shown, since the first system unit 29 and the second system unit 30 alternately perform exposure and AD conversion in one frame period, exposure operation can be performed for most of the time in one frame period even if multiple AD conversions are performed in one frame period.

[0121] Figure 5 The decision circuit 45 in the logic circuit 8 shown is not a necessary construction and can therefore be omitted. Furthermore, in Figure 5 In the logic circuit 8, a first holding circuit 46 and a second holding circuit 47 are provided, but only one holding circuit can be provided.

[0122] Figure 6 This is the timing diagram of ADC 7 and logic circuit 8 when logic circuit 8 does not include decision circuit 45 but only includes a hold circuit. Figure 6 The timing of the digital signal output from ADC 7, the timing of the latch transfer pulse input to the hold circuit, the timing of the latch output signal of the hold circuit, and the transfer timing of logic circuit 8 are shown.

[0123] Figure 6 Four pixel circuits 2 are shown. Figure 6 Example of pixel circuits #1 to #4 connected to a signal line VSL. At the beginning of a frame period, ADC 7 performs automatic zeroing (Auto Zero) on the reference potential of signal line VSL set by DSF circuit 5 to set the reference potential of comparator 41. Thereafter, the signal line voltage with high conversion gain C0 output from each pixel circuit 2 is... Figure 6 The HG in the middle is subjected to AD conversion, and then the signal line voltage with low conversion gain (C0+C1) is converted. Figure 6 The ADC 7 performs AD conversion on the LG pixel in the four-pixel circuit 2. This series of operations is repeated for each of the four pixels in the circuit 2. Finally, the ADC 7 performs AD conversion on a total of eight pixels in one frame cycle. The hold circuit in the logic circuit 8 sequentially latches the digital signals of the eight pixels output from the ADC 7. The hold circuit holds each digital signal for 1 / 9 of a frame cycle.

[0124] Figure 7 This is a timing diagram of the ADC 7 and the logic circuit 8, where the logic circuit 8 includes a decision circuit 45, a first holding circuit 46, and a second holding circuit 47. Figure 7 The timing of the digital signal output from ADC 7, the timing of the latch transmission pulses input to the first hold circuit 46 and the second hold circuit 47, the timing of the latch output signal (Latch 1) of the first hold circuit 46, the timing of the latch output signal (Latch 2) of the second hold circuit 47, and the transmission timing of the logic circuit 8 are shown.

[0125] As described above, ADC 7 performs AD conversion on eight pixels in one frame cycle and distributes the converted digital signal to the first hold circuit 46 and the second hold circuit 47, so that logic circuit 8 only needs to transmit the data of one pixel in 2 / 9 frame cycles. Therefore, the processing of logic circuit 8 has a time margin and can further improve the frame rate accordingly.

[0126] although Figure 3 The pixel circuit 2 can switch between high conversion gain C0 and low conversion gain (C0+C1), but it can also provide a mode that fixes the gain to either high conversion gain C0 or low conversion gain (C0+C1). When the gain is fixed, the shooting speed can be increased.

[0127] Figure 8 This is a timing diagram of ADC 7 and logic circuit 8 with the gain of pixel circuit 2 fixed and logic circuit 8 equipped with a hold circuit. In this case, since ADC 7 only needs to perform AD conversion on four pixels in one frame period, ADC 7 only needs to perform AD conversion on one pixel in 1 / 5 of a frame period. Therefore, the number of AD conversions of ADC 7 is less than that of other circuits. Figure 6 The number of times this occurs can be reduced, thus increasing the frame rate accordingly.

[0128] Figure 9 This is a timing diagram assuming the gain of pixel circuit 2 is fixed and logic circuit 8 is equipped with a first holding circuit 46 and a second holding circuit 47. Figure 9 In this case, logic circuit 8 only needs to transmit the digital data of each pixel in 1 / 4 of a frame period, compared to Figures 6 to 8 Compared to the previous situation, it can improve the frame rate.

[0129] Figure 10 This is a detailed timing diagram illustrating the operation of the camera device 1 according to this embodiment. Figure 10The timing diagram illustrates an example where eight pixel circuits 2 are connected to a single signal line VSL, and each pixel circuit 2 sequentially outputs data with high conversion gain C0 and data with low conversion gain (C0+C1) to the signal line VSL. Since each pixel circuit 2 outputs two signal line voltages, and at the beginning of each frame period, the DSF circuit 5 sets the signal line voltages to a reference potential, a total of 1+8+8=17 signal line voltages are transmitted through the single signal line VSL in one frame period.

[0130] At time t1, the S / H circuit 6 samples and holds the signal line voltage. At this time point, the signal line voltage is low; therefore, comparator 41 selects the fine-slope voltage. Figure 10 In the diagram, the thin ramp voltage is represented by a solid line, and the thick ramp voltage is represented by alternating long and short dashed lines. Comparator 41 in ADC 7 compares the sampled and held signal line voltage with the thin ramp voltage, and counter 43 performs a counting operation from time t1 to time t1a when the sampled and held signal line voltage intersects with the thin ramp voltage, outputting the count value obtained at time t1a as a digital signal. Subsequently, at time t1b, the second hold circuit 47 latches the digital signal. Therefore, IF circuit 9 outputs the digital signal latched by the second hold circuit 47 after time t1b.

[0131] At time t1b, the DSF circuit 5 begins the auto-zeroing cycle (AZ cycle) for setting the signal line VSL to the reference potential. At time t2, the S / H circuit 6 samples and holds the reference potential of the signal line VSL. Since the sampled and held signal line voltage is at the reference potential level, a fine ramp voltage is selected. Between time t2 and time t3, the ADC 7 sets the reference potential of the comparator 41 and does not perform normal AD conversion operation.

[0132] At time t3, the S / H circuit 6 samples and holds the signal line voltage #1HG of pixel circuit #1, which has a high conversion gain C0. Since the sampled and held signal line voltage is higher than the reference voltage Vref, a coarse ramp voltage is selected. Because the sampled and held signal line voltage intersects with the coarse ramp voltage at time t3a, the counter 43 in ADC 7 outputs the count value obtained from time t3 to time t3a as a digital signal. At the subsequent time t3b, the first hold circuit 46 latches the digital signal.

[0133] Subsequently, at time t4, the S / H circuit 6 samples and holds the signal line voltage #1LG of pixel circuit #1 with low conversion gain (C0+C1). Since the sampled and held signal line voltage is equal to or lower than the reference voltage Vref, a fine ramp voltage is selected. Because the sampled and held signal line voltage intersects with the fine ramp voltage at time t4a, the counter 43 in ADC7 outputs the count value obtained from time t4 to time t4a as a digital signal. At the subsequent time t4b, the second hold circuit 47 latches the digital signal.

[0134] The judgment circuit 45 determines that the digital signal #1HG with high conversion gain C0 held in the first holding circuit 46 is not saturated. Therefore, at time t4b, the IF circuit 9 outputs the digital signal #1HG held in the first holding circuit 46.

[0135] On the other hand, at a subsequent time t6b, the determination circuit 45 determines that the digital signal #2HG with high conversion gain C0, latched in the second holding circuit 47, is saturated. Therefore, at time t6b, the IF circuit 9 outputs the digital signal #2LG with low conversion gain (C0+C1), latched in the first holding circuit 46.

[0136] Thus, in the first embodiment, since a first capacitor C0 for high conversion gain and a second capacitor C1 for low conversion gain are provided in the pixel circuit 2, the first capacitor C0 and the second capacitor C1 can be selectively used to store charge according to the intensity of electromagnetic waves such as X-rays incident on the photodiode 13. Therefore, even if strong electromagnetic waves are incident on the photodiode 13, the intensity of the electromagnetic waves can be accurately detected without causing saturation.

[0137] Furthermore, since the first system unit 29 and the second system unit 30 are provided in the pixel circuit 2 and exposure operation and AD conversion operation are performed alternately, exposure operation can be performed for most of the time of a frame period, and the dead time when electromagnetic waves cannot be received can be reduced.

[0138] Furthermore, since two types of ramp voltages are provided for AD conversion operation, AD conversion of the intensity of electromagnetic waves received by photodiode 13 can be performed quickly and accurately.

[0139] Furthermore, the system stores the reset potential when the first reset circuit 31 has been reset, stores the kTC noise generated when the first reset circuit 31 has been de-reset, and cancels out the reset potential and kTC noise when the voltage is output to the signal line VSL. Therefore, it is particularly able to improve the S / N ratio when imaging weak electromagnetic waves.

[0140] (Second Embodiment)

[0141] The second embodiment provides an HDR mode for further expanding the dynamic range.

[0142] The pixel circuit in the camera device according to the second embodiment has a similar Figure 3 The circuit configuration is similar to that in the first embodiment. In addition to the high conversion gain mode and low conversion gain mode described in the first embodiment, the pixel circuit according to the second embodiment also includes an HDR mode.

[0143] Figure 11 This is a timing diagram of the pixel circuit according to the second embodiment. Figure 11 In one of two adjacent frames (N frames), exposures with high conversion gain and low conversion gain are performed for approximately the same length, and voltages with each gain are output to the signal line. In the other frame (N+1 frames), the exposure time with low conversion gain is made shorter than the exposure time with high conversion gain, and voltages with each gain are output to the signal line.

[0144] exist Figure 11 In the diagram, high conversion gain is represented by HG, and low conversion gain is represented by LG.

[0145] Figure 11 The timing diagram assumes that the X-ray dose remains constant during each frame period. When the X-ray dose remains constant within a frame period, the charge accumulated in the first capacitor C0 and the second capacitor C1 may become saturated. Therefore, in one of the two frames, the exposure time is shortened only for the low conversion gain. This allows for an increase in the equivalent dynamic range. For example, if the exposure time with low conversion gain is shortened to 1 / 10 of the exposure time with high conversion gain, the dynamic range becomes 10 times greater, even though the amount of light received remains the same.

[0146] In HDR mode, by increasing the ratio of exposure time period with high conversion gain to frame period, individual photons can be reliably detected, and by shortening the exposure time period with low conversion gain, the dynamic range can be further expanded.

[0147] In HDR mode, exposure and AD conversion operations are performed on a two-frame-per-second basis. Therefore, the equivalent frame rate is half that of the normal frame rate. In X-ray illumination, pixels exposed to strong X-rays and pixels exposed to only a single photon may occur simultaneously. For pixels exposed to only a single photon, it is desirable to extend the exposure time as much as possible to capture that single photon. For example, the exposure time with high conversion gain is set to a duty cycle of more than 90% of the total two-frame time. On the other hand, for pixels exposed to strong X-rays, a low conversion gain is selected. Figure 11In the example, within N frames, since the exposure time with low conversion gain LG is slightly longer than the exposure time with high conversion gain HG, the imaging data of N frames with low conversion gain LG can be used as long as the X-ray dose is at an unsaturated level. On the other hand, if the X-ray dose is saturated under the low conversion gain LG of N frames, the imaging data of (N+1) frames with low conversion gain LG and short exposure time is used.

[0148] In modes other than HDR, signal S8 goes high at time t2, and transistor Q14 turns off. Therefore, exposure operation with low conversion gain begins from the time point t3 when the reset is completed. On the other hand, in HDR mode, signal RST goes low at time t4, resetting the charge in capacitors C0 and C1, and signal RST goes high at time t5, turning off transistor Q4, and exposure operation with low conversion gain begins from that time point.

[0149] More specifically, in HDR mode, in one of two consecutive frame cycles (e.g., Figure 11 In the (N+1) frame period, with another frame period (e.g., Figure 11 Compared to the N-frame period in the previous method, the length of the first period (HG detection period) can be shortened, and the amount of accumulated charge in the first capacitor C0 and the second capacitor C1 can be limited. Specifically, within one frame period, after the first capacitor C0 and the second capacitor C1 begin to accumulate charge, and before the first period (HG detection period) and the second period (LG detection period) have elapsed, the accumulated charge in the first capacitor C0 and the second capacitor C1 is temporarily discharged, after which charge accumulation resumes. After the first period, the voltage corresponding to the accumulated charge in the first capacitor C0 is stored in the third storage unit 27, and after the second period, the voltage corresponding to the accumulated charge in the first capacitor C0 and the second capacitor C1 is stored in the fourth storage unit 28. Note that after the first period of the aforementioned frame period, the voltage corresponding to the accumulated charge in the first capacitor C0 can be stored in the first storage unit 23, and after the second period, the voltage corresponding to the accumulated charge in the first capacitor C0 and the second capacitor C1 can be stored in the fourth storage unit 28.

[0150] Thus, in the second embodiment, since a new HDR mode is provided, weak X-rays can be reliably detected, and even under strong X-ray irradiation, accurate detection can be performed in an unsaturated state, and the dynamic range can be further expanded.

[0151] Note that this technology can have the following structure.

[0152] (1) A camera device comprising:

[0153] A conversion unit that converts incident electromagnetic waves into electrical charges;

[0154] A first capacitor accumulates the charge when the voltage corresponding to the charge is equal to or lower than a predetermined threshold.

[0155] A second capacitor accumulates the charge when the voltage exceeds the threshold.

[0156] A voltage conversion circuit that converts the charge accumulated in the first capacitor and the second capacitor into voltage;

[0157] A first storage cell, after a first cycle since the first capacitor began accumulating charge, stores a voltage corresponding to the accumulated charge in the first capacitor; and

[0158] The second storage cell stores a voltage corresponding to the accumulated charge in the first capacitor and the second capacitor after a second period longer than the first period since the first capacitor began accumulating the charge.

[0159] (2) The camera device according to (1) further includes:

[0160] A third storage cell stores a voltage corresponding to the accumulated charge in the first capacitor after the first cycle has elapsed since the first capacitor began accumulating the charge; and

[0161] The fourth storage cell, after the second cycle has elapsed since the first capacitor began accumulating the charge, stores the voltage corresponding to the accumulated charge in the first capacitor and the second capacitor.

[0162] Specifically, during a predetermined frame period, corresponding voltages are stored in the first and second storage cells, respectively. Simultaneously, in the frame period immediately preceding the predetermined frame period, the voltages stored in the third and fourth storage cells are output to the signal line.

[0163] While storing corresponding voltages in the third and fourth storage cells in a frame period immediately following the predetermined frame period, the voltages stored in the first and second storage cells in the predetermined frame period are output to the signal line.

[0164] (3) The camera device according to (1) or (2) further includes:

[0165] A first reset circuit discharges the accumulated charge in the first and second capacitors to initialize them; and

[0166] The fifth storage unit stores the initialization voltage when the first capacitor and the second capacitor are initialized.

[0167] (4) The camera device according to (3) further includes a first transmission circuit, which outputs the differential voltage between the voltage stored in the second storage unit and the voltage stored in the fifth storage unit to the signal line in each frame period.

[0168] (5) The camera device according to (3) or (4) further includes a sixth storage unit, which stores the voltage of the path connected to the first reset circuit when the initialization performed by the first reset circuit is released.

[0169] (6) The camera device according to (5) further includes a second transmission circuit, which outputs the differential voltage between the voltage stored in the first storage unit and the voltage stored in the sixth storage unit to the signal line in each frame period.

[0170] (7) The camera device according to any one of (1) to (6) further includes a first voltage limiter that, when the voltage corresponding to the charge is equal to or lower than the threshold, the first voltage limiter cuts off the accumulation of the charge in the second capacitor, and when the voltage exceeds the threshold, the first voltage limiter accumulates the charge in the second capacitor.

[0171] (8) The camera device according to any one of (1) to (7) further includes a mode selection unit, the mode selection unit selecting whether to store a voltage corresponding to the accumulated charge of one of the first capacitor and the second capacitor in the second storage unit, or to store a voltage corresponding to the accumulated charge of the first capacitor and the second capacitor in the second storage unit.

[0172] (9) The camera device according to any one of (1) to (8), further comprising:

[0173] A sample-and-hold circuit samples and holds the voltage of a signal line at predetermined periods, the signal line sequentially transmitting voltages stored in the first and second memory cells; and

[0174] An AD converter converts the voltage sampled and held by the sample-and-hold circuit into a digital signal.

[0175] (10) The camera device according to (9) further includes:

[0176] A first holding circuit holds one of the voltages stored in the first storage cell and the voltages stored in the second storage cell; and

[0177] The second holding circuit holds another voltage between the voltage stored in the first storage cell and the voltage stored in the second storage cell.

[0178] (11) The camera device according to (10) further includes:

[0179] A judgment circuit, based on digital signals held in the first holding circuit and the second holding circuit, determines whether the accumulated charge in the first capacitor is saturated; and

[0180] The selection circuit selects and outputs the digital signal held in the first holding circuit or the second holding circuit based on the judgment result of the judgment circuit.

[0181] (12) The camera device according to any one of (9) to (11), wherein,

[0182] The AD converter includes:

[0183] A ramp selector selects a first ramp voltage when the voltage held in the sample-and-hold circuit is equal to or higher than a predetermined reference voltage, and selects a second ramp voltage when the voltage held in the sample-and-hold circuit is lower than the reference voltage. Compared with the first ramp voltage, the second ramp voltage has a smaller voltage amplitude variation width and a lower voltage change rate over time.

[0184] The comparison unit compares the voltage held in the sample-and-hold circuit with either the first ramp voltage or the second ramp voltage; and

[0185] A counter that generates the digital signal based on the comparison result of the comparison unit.

[0186] (13) The imaging device according to any one of (9) to (12), further comprising a plurality of pixel circuits connected to the signal line,

[0187] The pixel circuit includes the conversion unit, the first capacitor, the second capacitor, the first storage unit, and the second storage unit.

[0188] The sample-and-hold circuit sequentially holds the voltages output from the plurality of pixel circuits during a frame period.

[0189] (14) The camera device according to any one of (1) to (13) further includes a mode selection unit, the mode selection unit being capable of selecting a predetermined mode for expanding the dynamic range.

[0190] When the predetermined mode is selected, in one of two consecutive frame cycles, the length of the first cycle is shortened compared to the length of the first cycle in the other frame cycle, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage unit is limited.

[0191] (15) The camera device according to (14), wherein,

[0192] During one frame cycle, after the first and second capacitors begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first and second capacitors is temporarily discharged. Afterward, the accumulation of charge resumes.

[0193] The second storage unit stores, during the frame period, the voltage corresponding to the accumulated charge after the first capacitor and the second capacitor have restarted the accumulation of charge.

[0194] (16) The camera device according to (2) further includes a mode selection unit, the mode selection unit being capable of selecting a predetermined mode for expanding the dynamic range.

[0195] When the predetermined mode is selected, in one of two consecutive frame periods, the length of the first period is shortened compared to the length of the first period in the other frame period, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage unit and the fourth storage unit is limited.

[0196] (17) The camera device according to (16), wherein,

[0197] During one frame cycle, after the first and second capacitors begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first and second capacitors is temporarily discharged. Afterward, the accumulation of charge resumes.

[0198] The fourth storage unit stores, in one frame period, the voltage corresponding to the accumulated charge after the first capacitor and the second capacitor have restarted the accumulation of charge.

[0199] The aspects of this disclosure are not limited to the embodiments described above, but include various modifications that can be conceived by those skilled in the art, and the effects of this disclosure are not limited to the foregoing. That is, various additions, changes, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the content defined in the claims and their equivalents.

[0200] List of reference numerals

[0201] 1 camera device

[0202] 1a Pixel array unit

[0203] 1b Peripheral Circuit Unit

[0204] 2-pixel circuit

[0205] 4 Scan line drive circuit

[0206] 5. Pseudo-source follower circuit (DSF circuit)

[0207] 6. Sample-and-hold circuit (S / H circuit)

[0208] 7. Analog-to-Digital Converter (ADC) Circuit

[0209] 8 logic circuits

[0210] 9. Interface circuit (IF circuit)

[0211] 10 Grounding layer

[0212] 11 First substrate

[0213] 12 Second substrate

[0214] 13. Photoelectric conversion region (photodiode)

[0215] 14 Cathode

[0216] 15 Anode

[0217] 16 X-ray shields

[0218] 17 Wiring Layer

[0219] 18 Peripheral Circuits

[0220] 19. Protective Ring

[0221] 21 Conversion Unit

[0222] 22 Voltage buffer

[0223] 23 First storage unit

[0224] 24 Second storage unit

[0225] 25 Current Source

[0226] 26 First Voltage Limiter

[0227] 27 Third storage unit

[0228] 28 Fourth storage unit

[0229] 29 First System Unit

[0230] 30 Second System Unit

[0231] 31 First Reset Circuit

[0232] 32 Fifth storage unit

[0233] 33 First Transmission Circuit

[0234] 34 Sixth storage unit

[0235] 35 Second transmission circuit

[0236] 41 Comparator

[0237] 42. Ramp Wave Selector

[0238] 43 Counter

[0239] 44 First Multiplexer

[0240] 45. Determine the circuit

[0241] 46 First Holding Circuit

[0242] 47 Second Holding Circuit

[0243] 48 Second Multiplexer

[0244] 49HG / LG discriminator

[0245] C0 First Capacitor

[0246] C1 Second capacitor

Claims

1. A camera device, comprising: A conversion unit that converts incident electromagnetic waves into electrical charges; A first capacitor accumulates the charge when the voltage corresponding to the charge is equal to or lower than a predetermined threshold. A second capacitor accumulates the charge when the voltage exceeds the threshold. A voltage conversion circuit that converts the charge accumulated in the first capacitor and the second capacitor into voltage; The first storage cell stores a voltage corresponding to the accumulated charge in the first capacitor after a first cycle has elapsed since the first capacitor began accumulating the charge. The second storage cell stores a voltage corresponding to the accumulated charge in the first capacitor and the second capacitor after a second period longer than the first period since the first capacitor began to accumulate the charge. The third storage unit stores the voltage corresponding to the accumulated charge in the first capacitor after the first cycle has elapsed since the first capacitor began accumulating the charge. and The fourth storage cell, after the second cycle has elapsed since the first capacitor began accumulating the charge, stores the voltage corresponding to the accumulated charge in the first capacitor and the second capacitor. Specifically, during a predetermined frame period, corresponding voltages are stored in the first and second storage cells, respectively. Simultaneously, in the frame period immediately preceding the predetermined frame period, the voltages stored in the third and fourth storage cells are output to the signal line. While storing corresponding voltages in the third and fourth storage cells in a frame period immediately following the predetermined frame period, the voltages stored in the first and second storage cells in the predetermined frame period are output to the signal line.

2. The camera device according to claim 1, further comprising: A first reset circuit discharges the accumulated charge in the first capacitor and the second capacitor to initialize them; and The fifth storage unit stores the initialization voltage when the first capacitor and the second capacitor are initialized.

3. The camera device according to claim 2, further comprising a first transmission circuit, wherein the first transmission circuit outputs a differential voltage between the voltage stored in the second storage unit and the voltage stored in the fifth storage unit to a signal line each frame period.

4. The camera device according to claim 2, further comprising a sixth storage unit, wherein when the initialization performed by the first reset circuit is released, the sixth storage unit stores the voltage of the path connected to the first reset circuit.

5. The camera device according to claim 4, further comprising a second transmission circuit, wherein the second transmission circuit outputs a differential voltage between the voltage stored in the first storage unit and the voltage stored in the sixth storage unit to a signal line each frame period.

6. The camera device according to any one of claims 1 to 5, further comprising a first voltage limiter that, when the voltage corresponding to the charge is equal to or lower than the threshold, the first voltage limiter cuts off the accumulation of the charge in the second capacitor, and when the voltage exceeds the threshold, the first voltage limiter allows the charge to accumulate in the second capacitor.

7. The camera device according to any one of claims 1 to 5, further comprising a mode selection unit, the mode selection unit selecting whether to store a voltage corresponding to the accumulated charge of one of the first capacitor and the second capacitor in the second storage unit, or to store a voltage corresponding to the accumulated charge of the first capacitor and the second capacitor in the second storage unit.

8. The camera device according to any one of claims 1 to 5, further comprising: A sample-and-hold circuit samples and holds the voltage of a signal line at predetermined periods, the signal line sequentially transmitting voltages stored in the first and second memory cells; and An AD converter converts the voltage sampled and held by the sample-and-hold circuit into a digital signal.

9. The camera device according to claim 8, further comprising: A first holding circuit holds one of the voltages stored in the first storage cell and the voltages stored in the second storage cell; and The second holding circuit holds another voltage between the voltage stored in the first storage cell and the voltage stored in the second storage cell.

10. The camera device according to claim 9, further comprising: A judgment circuit determines whether the accumulated charge in the first capacitor is saturated based on digital signals held in the first holding circuit and the second holding circuit. and The selection circuit selects and outputs the digital signal held in the first holding circuit or the second holding circuit based on the judgment result of the judgment circuit.

11. The camera device according to claim 8, wherein, The AD converter includes: A ramp selector selects a first ramp voltage when the voltage held in the sample-and-hold circuit is equal to or higher than a predetermined reference voltage, and selects a second ramp voltage when the voltage held in the sample-and-hold circuit is lower than the reference voltage. Compared with the first ramp voltage, the second ramp voltage has a smaller voltage amplitude variation width and a lower voltage change rate over time. The comparison unit compares the voltage held in the sample-and-hold circuit with either the first ramp voltage or the second ramp voltage; and A counter that generates the digital signal based on the comparison result of the comparison unit.

12. The imaging device according to claim 8, further comprising a plurality of pixel circuits connected to the signal line. in, The pixel circuit includes the conversion unit, the first capacitor, the second capacitor, the first storage unit, and the second storage unit, and The sample-and-hold circuit sequentially holds the voltages output from the plurality of pixel circuits during a frame period.

13. The imaging apparatus according to any one of claims 1 to 5, further comprising a mode selection unit, the mode selection unit being capable of selecting a predetermined mode for expanding the dynamic range. in, When the predetermined mode is selected, in one of two consecutive frame cycles, the length of the first cycle is shortened compared to the length of the first cycle in the other frame cycle, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage cell is limited.

14. The camera device according to claim 13, wherein, During one frame cycle, after the first and second capacitors begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first and second capacitors is temporarily discharged. Afterward, the accumulation of charge resumes. The second storage unit stores, during the frame period, the voltage corresponding to the accumulated charge after the first capacitor and the second capacitor have restarted the accumulation of charge.

15. The imaging device according to claim 1, further comprising a mode selection unit, the mode selection unit being capable of selecting a predetermined mode for expanding the dynamic range. in, When the predetermined mode is selected, in one of two consecutive frame cycles, the length of the first cycle is shortened compared to the length of the first cycle in the other frame cycle, and the cumulative charge of the first capacitor and the second capacitor stored in the second storage unit and the fourth storage unit is limited.

16. The camera device according to claim 15, wherein, During one frame cycle, after the first and second capacitors begin accumulating charge and before the first cycle and the second cycle have elapsed, the accumulated charge in the first and second capacitors is temporarily discharged. Afterward, the accumulation of charge resumes. The fourth storage unit stores, in one frame period, the voltage corresponding to the accumulated charge after the first capacitor and the second capacitor have restarted the accumulation of charge.

Images