A data reading method, a solid state disk, a controller and a computer device

Abstract

A data reading method, a solid state disk, a controller and a computer device. The data reading method comprises: receiving a first instruction for reading data in a first storage unit; determining that a pre-reading trigger condition is met, and transferring target data to be read in the first storage unit to a pre-reading buffer area created in a second storage unit; and receiving a second instruction for reading the target data, and reading the target data from the pre-reading buffer area. Through the method, the cost budget of the solid state storage device can be reduced, the SRAM overhead of the storage controller can be reduced, and the data reading performance can be improved.

Description

Technical Field

[0001] This invention relates to, but is not limited to, the field of solid-state storage device control, and particularly to a data reading method, a solid-state drive, a controller, and a computer device. Background Technology

[0002] Existing technologies typically use SDRAM (Synchronous Dynamic Random-access Memory) or SRAM (Static Random-Access Memory) as a high-speed prefetch cache. This allows for the use of spare bandwidth in the backend to prefetch data into the cache in scenarios with low queue sequential reads, thereby improving read performance.

[0003] However, SDRAM or SRAM as a cache medium cannot leverage price advantages in cost-sensitive markets, and SRAM occupies a relatively high area inside the chip, resulting in increased power consumption and higher cost of the controller. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] To address the aforementioned technical problems, this disclosure provides a data reading method applied to a computer device including a first storage unit and a second storage unit, wherein both the first and second storage units are solid-state storage devices, and the read rate of the second storage unit is greater than the read rate of the first storage unit. The method may include:

[0006] Receive a first instruction to read data from the first storage unit;

[0007] If the pre-read triggering condition is met, the target data to be read in the first storage unit is transferred to the pre-read cache created in the second storage unit;

[0008] Upon receiving the second instruction to read the target data, the target data is read from the pre-read buffer.

[0009] One embodiment of this disclosure also provides a solid-state drive, including a main control chip and a first storage unit and a second storage unit connected to the main control chip, wherein the main control chip performs the data reading method as described in any embodiment of this disclosure.

[0010] One embodiment of this disclosure also provides a memory controller, including a processor and a memory storing a computer program, wherein the processor, when executing the computer program, is capable of implementing the data reading method as described in any embodiment of this disclosure.

[0011] One embodiment of this disclosure also provides a computer device, including a first storage unit, a second storage unit, and a memory controller as described in any embodiment of this disclosure, connected to the first storage unit and the second storage unit.

[0012] An embodiment of this disclosure also provides a non-transient computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, can implement the data reading method as described in any embodiment of this disclosure.

[0013] Compared with related technologies, the present disclosure provides a data reading method, a solid-state drive (SSD), a controller, and a computer device. By transferring data reading operations to a high-read-rate pre-fetch cache, the SRAM overhead of the SSD can be reduced while improving data reading performance.

[0014] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0015] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0016] Figure 1 This is a flowchart of a data reading method according to an embodiment of this disclosure;

[0017] Figure 2a This is a schematic diagram of an exemplary read instruction according to an embodiment of this disclosure;

[0018] Figure 2b This is a schematic diagram of yet another exemplary read instruction according to an embodiment of this disclosure;

[0019] Figure 3 This is a flowchart of host read and pseudo read according to an embodiment of this disclosure;

[0020] Figure 4 This is a schematic diagram of the pre-stored cache area before and after data migration according to an embodiment of this disclosure;

[0021] Figure 5 This is a flowchart illustrating data reading from a solid-state drive according to an embodiment of this disclosure;

[0022] Figure 6 This is a schematic diagram of a memory controller according to an embodiment of the present disclosure. Detailed Implementation

[0023] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0024] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0025] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0026] In the existing solid-state storage technology field, the read and write speeds of storage media are ranked from largest to smallest as follows: SRAM > SDRAM > SLC Block > TLC Block (SLC represents Single-Level Cell, and TLC represents Three-Level Cell). However, in consumer-grade solid-state storage devices, the presence of SRAM and SDRAM accounts for a relatively high proportion of the cost.

[0027] Consumer-grade solid-state storage devices play a mostly cost-sensitive role in the market. Therefore, major storage controller design manufacturers will try to reduce the capacity of the SRAM inside the chip as much as possible, and SDRAM components, as optional, will be directly abandoned. SRAM and SDRAM can no longer serve as caches in cost-sensitive solid-state storage devices.

[0028] Therefore, one embodiment of this disclosure provides a data reading method applied to a computer device including a first storage unit and a second storage unit, wherein both the first and second storage units are solid-state storage devices, and the read rate of the second storage unit is greater than the read rate of the first storage unit, such as... Figure 1 As shown, the data reading method can be performed according to the following steps:

[0029] Step S110: Receive a first instruction to read data from the first storage unit;

[0030] Step S120: If the pre-read triggering condition is met, the target data to be read in the first storage unit is transferred to the pre-read cache area created in the second storage unit;

[0031] Step S130: After receiving the second instruction to read the target data, read the target data from the pre-read buffer.

[0032] The first storage unit can be a TLC Block, and the second storage unit can be an SLC Block.

[0033] This embodiment addresses the issue of limited read cache size provided by the on-chip SRAM in DRAM-LESS solid-state storage solutions, which cannot meet the performance requirements of sequential reads in low queue depth scenarios. It uses SLC blocks instead of SRAM or SDRAM as the pre-read algorithm cache space and replaces some TLC blocks with SLC blocks, using these SLC blocks as the pre-read cache area. When the pre-read trigger condition is met, the storage controller utilizes the available backend bandwidth to transfer the user data to be read to the pre-read cache area. When the actual read command is received by the controller and processing begins, the data the user wants to read has already been pre-loaded into the high-read-rate pre-read cache area, allowing the user to directly read the data from the pre-read cache. This embodiment's technical solution can reduce the cost budget of solid-state storage devices, reduce the SRAM overhead of the storage controller, and improve data read performance.

[0034] In an exemplary embodiment of this disclosure, the first storage unit is one of a two-level storage unit (MLC), a three-level storage unit (TLC), and a four-level storage unit (QLC), and the second storage unit is one of a single-level storage unit (SLC), an MLC, and a TLC.

[0035] In an exemplary embodiment of this disclosure, the pre-read triggering condition includes: receiving N first instructions, wherein the logical addresses of the N first instructions are contiguous, and N is a set value greater than or equal to 3.

[0036] In one example of this embodiment, when the controller detects that the LCA (Logical Address) of three host read commands (i.e., the first command) are consecutive and do not overlap, see [link to example]. Figure 2a (In the diagram, lca3-lca11 represent logical address 3-logical address 11, and cmd0-cmd3 represent command 0-command 3), then it is determined that the current read operation meets the pre-read algorithm triggering condition;

[0037] When the controller detects overlapping LCAs of three host read commands, see Figure 2b (In the diagram, lca3-lca6 represent logical address 3-logical address 6, and cmd0-cmd3 represent command 0-command 3). Therefore, it is determined that the current read operation does not meet the triggering conditions of the pre-read algorithm.

[0038] This example determines whether multiple read commands are read sequentially based on whether the LCAs of read commands of a set length are consecutive, thereby determining whether prefetching can be triggered. Furthermore, if the LCAs of host read commands of a set length are not consecutive, an overlapping scenario is identified. In this case, the prefetched data cannot guarantee that all the data required by the actual read command will be overwritten, so the current prefetching must be stopped immediately.

[0039] In an exemplary embodiment of this disclosure, the pre-read triggering condition includes: the instruction depth of the front end is less than a set threshold, at which point the pressure on the back end data stream caused by the current read operation accounts for a small proportion of the total bandwidth of the back end data.

[0040] For example, when this data reading method is applied to a solid-state drive (SSD), the host sends a command, the SSD's FTL (Flash translation layer) collects the command, calculates the command depth, and determines whether to trigger a pre-read based on whether the received command depth is less than a set threshold.

[0041] This embodiment uses "the instruction depth of the front end is less than the set threshold" as the pre-read trigger condition, which ensures that the back end has sufficient spare bandwidth, so that the storage controller can use the spare bandwidth of the back end to transfer the user data that is about to be read to the pre-read cache area.

[0042] In one example of this embodiment, when it is determined that the pre-read triggering condition is met, transferring the target data to be read from the first storage unit to the pre-read cache created in the second storage unit includes:

[0043] When the pre-read trigger condition is met, the starting address of the target data to be read in the first storage unit is determined;

[0044] Starting from the starting address, read the target data of a first set length from the first storage unit and transfer it to the pre-read cache area;

[0045] Update the mapping table from logical address to physical address corresponding to the transferred data.

[0046] In one example of this embodiment, the starting address is the logical address following the last logical address in the last first instruction.

[0047] In one example of this embodiment, the step of reading target data of a first predetermined length from the starting address backward and transferring it to the pre-read cache includes:

[0048] Establish a logical address set for the target data of the first predetermined length, wherein the first address of the logical address set is the starting address;

[0049] Based on the logical addresses in the logical address set, a data transfer pseudo-instruction is constructed and executed to transfer the target data corresponding to the logical address set from the first storage unit to the pre-read cache area in sequence.

[0050] In one example of this embodiment, when the pre-read algorithm is successfully triggered (i.e., when the pre-read trigger condition is met), the firmware will construct a pseudo-read instruction. The pseudo-read instruction consists of 1024 LCAs sequentially stacked from the last LCA of the last read instruction that triggered the pre-read (i.e., the logical address following the last logical address in the last first instruction). The firmware will then transfer all the target user data in the first storage unit to the second storage unit SLC pre-cache based on the pseudo-read instruction. Figure 3 As shown, the execution process of the pseudo-read instruction is the process of transferring the target user data to the slc pre cache. After the transfer is completed, the mapping table corresponding to the transferred data is updated, and subsequent host read commands (i.e., the second instruction) will hit the slc pre cache in sequence.

[0051] The mapping table records the mapping relationship between the logical address of the transferred data and the physical address it is mapped to; the first storage unit can be a TLC Block and the second storage unit can be an SLC Block.

[0052] In this example, because the host read operation hits the SLC pre cache (i.e., SLC Block), and the read rate of SLC Block is higher than that of TLC Block, the read performance of the solid-state storage device under low queue sequential read conditions can be improved.

[0053] In one example of this embodiment, the method further includes: based on the reading status of the target data, each time it is determined that target data of a second predetermined length has been read, performing the following processing:

[0054] A predetermined number of consecutive logical addresses are appended to the set of logical addresses; the first logical address in the appended set is adjacent to the last logical address in the set of logical addresses before the append, and corresponds to new target data with a length of the second predetermined length.

[0055] Based on the logical addresses of the data already read in the logical address set, a data move-back pseudo-instruction is constructed and executed. The target data that has been read is moved from the pre-read cache back to the first storage unit in sequence, and the mapping table from logical address to physical address corresponding to the moved-back data is updated.

[0056] This example uses SLC Block as a pre-read cache and invents a unique cache tracking and cleanup scheme based on cache characteristics, which can improve the read performance of solid-state drives in low-queue sequential read scenarios.

[0057] For details, see Figure 4The hard drive storage controller's internal algorithm maintains a check range, recording the set of logical addresses corresponding to user data that will be read in the future. The firmware algorithm maintains the pre-read effect by continuously tracking the check range. Simultaneously, the storage controller maintains a valid map table, recording which data within the currently tracked check range is old data and which is new data. The storage controller also sets a message size as a threshold for accumulating old data (data that has already been read) to initiate the capture action. When invalid data reaches the number of message sizes plus 4KB (i.e., the second preset length), the storage controller will initiate the capture action, using the backend spare bandwidth to capture message sizes plus 4KB of data from the end of the check range to the SLC pre-cache for later use. The message size may be 256 LCAs. The valid map table records the old and new status of all 4KB data in the SLC pre-cache and updates it in real time. When the amount of old data reaches 256 LCAs, the firmware will construct a fake read instruction to initiate the capture action and also initiate a data back-shift operation. Based on the records in the valid map table, the old data will be moved back to the TLC Block. After the data is moved back, the mapping table will be updated, thus completing the data replacement of the SLC pre-cache.

[0058] This example periodically moves used data from the slc pre cache back to the TLC Block, which means that the cached data in the slc pre cache is cleaned up regularly to ensure hit rate.

[0059] In summary, this embodiment adopts a novel pre-read strategy, which differs from traditional strategies that use SRAM or SDRAM as the pre-read data cache. Instead, it uses SLC pre-cache as the cache space for the pre-read algorithm. By leveraging the larger backend bandwidth in low-queue sequential read scenarios, it transfers user data that will be read in the future to the SLC Block. Furthermore, it designs a set of tracking and recording control algorithms, which can improve read performance in low-queue sequential read scenarios and reduce the cost budget of solid-state storage devices.

[0060] In one example of this embodiment, the method further includes: stopping reading data from the pre-read buffer when the pre-read condition is not met.

[0061] The above data reading method will be explained with specific examples below.

[0062] In an exemplary embodiment of this disclosure, the data reading process of a cost-sensitive solid-state drive can be as follows: Figure 5 The data reading process may include the following steps:

[0063] S501, host read, that is, the first instruction to read data from the first storage unit is received.

[0064] S502, query mapping: The firmware will look up the physical address corresponding to the logical address in the host instruction based on the mapping table.

[0065] S503, trigger pre-read, determine the next operation based on whether the pre-read trigger condition is met; if the pre-read trigger condition is met, execute step S504, otherwise execute step 510.

[0066] S504, constructing a pseudo-read: Specifically, the firmware will construct a pseudo-read instruction. The pseudo-read instruction consists of 1024 LCAs (i.e., the first preset length) stacked sequentially from the last LCA of the last read instruction triggered by the pre-read decision. The firmware will transfer all target user data to the SLC pre-cache according to the pseudo-read instruction. The execution process of the pseudo-read instruction is the process of transferring target user data to the SLC pre-cache. After the transfer is completed, the mapping table corresponding to the transferred data is updated.

[0067] S505, Tracking: The storage controller also sets a message size (i.e., the second preset length) as a threshold for accumulating old data (data that has already been read) to initiate the tracking action; when invalid data reaches the number of messagesize 4k, the storage controller will initiate the tracking action and execute step S506; when invalid data does not reach the number of messagesize 4k, tracking will not be performed, and the S511 command will be executed to complete the process.

[0068] S506, data migration: After the storage controller initiates the capture action, it will start from the last logical address of the check range and capture 4KB of data into the SLC pre-cache for later use.

[0069] S507, Data Relocation: Based on the records in the valid map table, the old data is moved back from the SLC Block to the TLCBlock. After this is done, the mapping table is updated, thus completing the data replacement of the SLC pre-cache.

[0070] S508, determine whether the pre-read cache is hit. If it is hit, proceed to step S509 to read data directly from the pre-read cache at high speed. If it is not hit, proceed to step S510 to read data normally according to the original reading method.

[0071] S509, high-speed read, that is, reading data from the SLC pre cache, with a high read rate.

[0072] S510, regular read, that is, reading data from the TLC Block in the original reading method.

[0073] S511, the current command has been executed.

[0074] This embodiment employs a novel pre-read strategy, switching some TLC blocks to SLC blocks and using SLCBlock as an SLC pre-cache. When the firmware determines that pre-read caching is necessary, the storage controller utilizes spare backend bandwidth to transfer the data to be read to the SLC pre-cache and periodically moves used data from the SLC pre-cache back to the TLC blocks. When the actual read command is received and processed by the controller, the data to be read has already been pre-loaded into the SLC pre-cache, allowing for direct data reading and significantly improving read performance in low-queue sequential read scenarios for solid-state storage devices. Furthermore, using an SLC pre-cache instead of the traditional SRAM or SDRAM as the pre-read data cache reduces the cost of solid-state storage devices and the SRAM overhead of the storage controller.

[0075] One embodiment of this disclosure also provides a solid-state drive, including a main control chip and a first storage unit and a second storage unit connected to the main control chip, wherein the main control chip performs the data reading method as described in any embodiment of this disclosure.

[0076] An embodiment of this disclosure also provides a memory controller, see [link to relevant documentation] Figure 6 It includes a processor and a memory storing a computer program, wherein the processor is capable of reading the computer program and executing the data reading method as described in any embodiment of this disclosure.

[0077] The processor in the embodiments of this disclosure can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc., or other conventional processors. The processor can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), discrete logic or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other equivalent integrated or discrete logic circuits, or a combination of the above devices. That is, the processor in the embodiments described above can be any processing device or combination of devices that implements the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. If the embodiments of this disclosure are implemented in part in software, then instructions for software can be stored in a suitable non-volatile computer-readable storage medium, and one or more processors can be used to execute the instructions in hardware to implement the methods of the embodiments of this disclosure. The term "processor" as used herein can refer to the above-described structure or any other structure suitable for implementing the techniques described herein.

[0078] One embodiment of this disclosure also provides a computer device, including a first storage unit, a second storage unit, and a memory controller as described in the previous embodiment, connected to the first storage unit and the second storage unit.

[0079] An embodiment of this disclosure also provides a non-transient computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the data reading method as described in any embodiment of this disclosure when run.

[0080] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A data reading method, applied to a computer device including a first storage unit and a second storage unit, wherein both the first storage unit and the second storage unit are solid-state storage devices, and the read rate of the second storage unit is greater than the read rate of the first storage unit, the method comprising: Receive a first instruction to read data from the first storage unit; If the pre-read triggering condition is met, the target data to be read in the first storage unit is transferred to the pre-read cache created in the second storage unit, including: establishing a logical address set of the target data; wherein, the pre-read triggering condition includes: receiving N first instructions, and the logical addresses in the N first instructions are contiguous, N is a set value greater than or equal to 3; and the instruction depth of the front end is less than a set threshold. Upon receiving the second instruction to read the target data, the target data is read from the pre-read buffer. The method further includes: based on the reading status of the target data, each time it is determined that target data of a second predetermined length has become read data, performing the following processing: appending a predetermined number of consecutive logical addresses to the logical address set, wherein the first logical address in the appended logical address set is adjacent to the last logical address in the logical address set before the append, corresponding to new target data of the second predetermined length; sequentially moving the target data that has become read data from the pre-read cache back to the first storage unit, and updating the mapping table from logical address to physical address corresponding to the moved-back data.

2. The method as described in claim 1, characterized in that: The first storage unit is one of a two-level storage unit (MLC), a three-level storage unit (TLC), and a four-level storage unit (QLC), and the second storage unit is one of a single-level storage unit (SLC), an MLC, and a TLC.

3. The method as described in claim 1, characterized in that: When the pre-read triggering condition is determined to be met, the target data to be read in the first storage unit is transferred to the pre-read cache created in the second storage unit, including: When the pre-read trigger condition is met, the starting address of the target data to be read in the first storage unit is determined; Starting from the starting address, read the target data of a first set length from the first storage unit and transfer it to the pre-read cache area; Update the mapping table from logical address to physical address corresponding to the transferred data.

4. The method as described in claim 3, characterized in that: The starting address is the logical address following the last logical address in the last first instruction.

5. The method as described in claim 3, characterized in that: The step of reading target data of a first predetermined length from the first storage unit starting from the starting address and transferring it to the pre-read cache includes: Establish a logical address set for the target data of the first predetermined length, wherein the first address of the logical address set is the starting address; Based on the logical addresses in the logical address set, a data transfer pseudo-instruction is constructed and executed to transfer the target data corresponding to the logical address set from the first storage unit to the pre-read cache area in sequence.

6. The method as described in claim 1, characterized in that: The method further includes: stopping reading data from the pre-read buffer when the pre-read condition is not met.

7. A solid-state drive (SSD), comprising a controller chip and a first storage unit and a second storage unit connected to the controller chip, wherein, The main control chip performs the data reading method as described in any one of claims 1 to 6.

8. A memory controller, comprising a processor and a memory storing a computer program, characterized in that, The processor is capable of reading the computer program and executing the data reading method as described in any one of claims 1 to 6.

9. A computer device, characterized in that, It includes a first storage unit, a second storage unit, and a memory controller as described in claim 8, which is connected to the first storage unit and the second storage unit.

10. A non-transient computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the data reading method according to any one of claims 1 to 6 when it is run.

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