Method for processing data access error of chip and related product

Abstract

Embodiments of the present application provide a chip data access error processing method and related products, the method comprising: an MCM of a chip receiving a first access instruction of miscellaneous processing, the MCM identifying whether the first access instruction is a 32-bit access instruction; when the MCM determines that the first access instruction is not a 32-bit access instruction, the MCM sends a stop request instruction to a core, the stop request instruction being used to instruct the core to control a power module to be in a stop mode, the stop mode being a mode in which a clock signal of the power module of the MCM is in an off state; and when the MCM is in the off state, a register of the MCM does not work. The technical solution provided by the present application has the advantage of high safety.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a method for handling data access errors in a chip and related products. Background Technology

[0002] The Miscellaneous Control Module (MCM) in a chip provides miscellaneous control functions for the chip. However, the current chip's MCM only supports a 32-bit write data width. Non-32-bit access will result in errors, leading to register abnormalities. Summary of the Invention

[0003] This application discloses a method for handling data access errors in a chip and related products. This method can avoid register anomalies caused by non-32-bit access and improve chip security.

[0004] Firstly, a method for handling data access errors in a chip is provided, the method comprising the following steps: The chip's MCM receives the first access instruction for miscellaneous processing, and the MCM identifies whether the first access instruction is a 32-bit access instruction; When the chip's MCM is determined to be a non-32-bit access instruction, a stop request instruction is sent to the kernel. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working.

[0005] Secondly, a data access error handling system for a chip is provided. The system is applied to a chip, which includes: an MCM, a core, and a nested vector interrupt controller. The core is connected to both the MCM and the nested vector interrupt controller. The system includes: MCM is used to receive the first access instruction for miscellaneous processing. MCM identifies whether the first access instruction is a 32-bit access instruction. The MCM is also used to send a stop request instruction to the kernel when it is determined to be a non-32-bit access instruction. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working.

[0006] Thirdly, an electronic device is provided, including a processor, a memory, a communication interface, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs including instructions for performing the steps of the method described in the first aspect.

[0007] Fourthly, a computer-readable storage medium is provided for storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform the method described in the first aspect.

[0008] Fifthly, a computer program product is provided, comprising a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of the embodiments of this application. The computer program product may be a software installation package.

[0009] The technical solution provided in this application allows the MCM to receive a first access instruction for miscellaneous processing. The MCM identifies whether the first access instruction is a 32-bit access instruction. When the MCM determines that it is a non-32-bit access instruction, it sends a stop request instruction to the kernel. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM do not work. In this way, when a non-32-bit access instruction is received, the kernel controls the power module to be in the stop state by sending the corresponding stop request instruction, thereby shutting down the registers, avoiding register errors, preventing abnormalities of non-32-bit access registers, and improving the security of the chip. Attached Figure Description

[0010] The accompanying drawings used in the embodiments of this application are described below.

[0011] Figure 1 This is a schematic diagram of the chip structure in this application; Figure 2 This is a flowchart illustrating a method for handling data access errors in a chip, as provided in this application. Figure 3 This is a schematic diagram of the priority data structure provided in this application; Figure 4 A schematic diagram of a chip data access error handling system provided in this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The embodiments of this application are described below with reference to the accompanying drawings.

[0013] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects have an "or" relationship.

[0014] In this application's embodiments, "multiple" refers to two or more. The use of terms like "first," "second," etc., in this application's embodiments is merely illustrative and for distinguishing the described objects; it has no order and does not indicate a specific limitation on the number of devices in this application's embodiments, nor does it constitute any limitation on the embodiments of this application. The term "connection" in this application's embodiments refers to various connection methods, such as direct or indirect connections, to achieve communication between devices; this application's embodiments do not impose any limitations on this.

[0015] See Figure 1 , Figure 1 A schematic diagram of a chip structure is provided, such as... Figure 1 As shown, it includes: NVIC (Nested Vector Interrupt Controller), kernel processor, and peripheral devices. The NVIC is connected to the kernel processor via PPB (private periphery bus). The NVIC is also connected to peripheral devices via peripheral interfaces. The kernel is connected to the MCM via a bus.

[0016] See Figure 2 , Figure 2 This is a method for handling data access errors in a chip, and the method is as follows: Figure 1 The chip shown executes the method as follows: Figure 2 As shown, it includes the following steps: Step S201: The chip's MCM receives the first access instruction for miscellaneous processing, and the MCM identifies whether the first access instruction is a 32-bit access instruction. Step S202: When the chip's MCM is determined to be a non-32-bit access instruction, a stop request instruction is sent to the kernel. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working.

[0017] Specifically, the inoperability of the aforementioned MCM registers can be achieved by enabling the FPU interrupt, which can be done through the MCM_INT_EN instruction.

[0018] The technical solution provided in this application allows the MCM to receive a first access instruction for miscellaneous processing. The MCM identifies whether the first access instruction is a 32-bit access instruction. When the MCM determines that it is a non-32-bit access instruction, it sends a stop request instruction to the kernel. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM do not work. In this way, when a non-32-bit access instruction is received, the kernel controls the power module to be in the stop state by sending the corresponding stop request instruction, thereby shutting down the registers, avoiding register errors, preventing abnormalities of non-32-bit access registers, and improving the security of the chip.

[0019] For example, the above methods may also include: The chip's MCM receives the kernel's RUN command and controls the MCM state to change from a non-working state to a normal working state.

[0020] As shown in Table 1 below, the operating status and power mode of the MCM module are as follows.

[0021] Table 1:

[0022] For example, the above methods may also include: The chip's MCM receives front-door instructions from the core and back-door instructions from external devices, determining the execution order of these instructions based on arbitration configuration. This method uses arbitration configuration to control the execution order of front-door and back-door instructions, thereby avoiding conflicts between them that could affect the efficiency of the MCM.

[0023] For example, determining the execution order of front-door and back-door instructions based on the arbitration configuration mentioned above may specifically include: If the arbitration is configured as polling, the MCM will execute the front door instruction and the back door instruction in rotation. If the arbitration is configured with a fixed priority and front door priority, then the MCM will execute the front door instructions first. If the arbitration is configured with a fixed priority and backdoors take precedence, then the MCM will execute frontdoor instructions first.

[0024] Its specific arbitration configuration includes the following: Arbitration support for polling and fixed priority is provided when the front door (kernel) and back door (external device) access SRAML.

[0025] 00b: Polling; 01b: Polling; 10b: Fixed priority, front door first; 11b: Fixed priority, backdoors take precedence.

[0026] For example, the above methods may also include: The chip's nested vector interrupt controller receives an interrupt command sent by a peripheral device and obtains the first priority of the first task corresponding to the interrupt command. The nested vector interrupt controller obtains the second priority of the second task being processed by the kernel. When the kernel determines that the second task is a miscellaneous task, it obtains whether the access instruction corresponding to the second task is a 32-bit access instruction. If the access instruction corresponding to the second task is a nested 32-bit access instruction, the kernel sends an indication instruction to the nested vector interrupt controller to compare the first priority and the second priority to obtain a comparison result. Based on the comparison result, the kernel determines whether to send an interrupt nesting instruction to the kernel. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed.

[0027] For example, obtaining the first priority of the first task corresponding to the interrupt instruction mentioned above may specifically include: The chip's nested vector interrupt controller extracts the system memory map of the first task from the interrupt instruction. The memory map includes a memory space mapping table. Based on the memory space mapping table, the value of the IPR (interrupt priority register) corresponding to the first task is extracted, and the first priority corresponding to the first task is determined based on the value.

[0028] Example, Figure 3 This application provides a data structure diagram illustrating the priority settings. Taking IPR0 as an example, the priority arrangement is explained. This NVIC supports 16 interrupt priorities; therefore, in the NVIC, each source in the IPR register contains 4 bits. The specific data structure diagram is shown below. Figure 3 As shown.

[0029] Among them, 0-3; 8-11, 16-19, and 24-27 represent the priorities of the 16 interrupts, respectively.

[0030] For example, the implementation method of the nested vector interrupt controller obtaining the second priority of the second task being processed by the kernel may specifically include: The chip's nested vector interrupt controller sends a query request to the kernel via the PPB bus and receives a query response from the kernel via the PPB bus. The query response includes the second priority of the second task.

[0031] For example, the query request and query response described above can be implemented using general instructions, or they can be implemented using special instructions (i.e., custom instructions). This application does not limit the specific form of the above instructions.

[0032] For example, the comparison results above may specifically include: First priority > second priority, first priority < second priority, or first priority = second priority.

[0033] The technical solution provided in this application provides a nested vector interrupt controller that receives an interrupt command sent by a peripheral device and obtains the first priority of the first task corresponding to the terminal command; the nested vector interrupt controller obtains the second priority of the second task being processed by the kernel; the nested vector interrupt controller compares the first priority and the second priority to obtain a comparison result, and determines whether to send an interrupt nesting instruction to the kernel based on the comparison result. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the second task. In this way, the peripheral device can interrupt the task being executed in real time, which improves the timeliness of the task and the efficiency of interruption.

[0034] For example, determining whether to send a nested interrupt instruction to the kernel based on this comparison result may specifically include: If the comparison result is that the first priority is greater than the second priority, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel; If the comparison result is that the first priority is less than the second priority, the nested vector interrupt controller will immediately stop sending an interrupt nesting instruction to the kernel. The nested vector interrupt controller will receive the execution completion instruction sent by the kernel after the second task is completed, and obtain the third priority of the third task that the kernel will execute. If the first priority is greater than the third priority, the nested vector interrupt controller will immediately send an interrupt nesting instruction to the kernel. If the first priority is less than the third priority, the nested vector interrupt controller will discard the interrupt instruction. If the comparison result is that the first priority equals the second priority, the nested vector interrupt controller obtains the first value of the execution progress of the second task. If the first value is greater than the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel after the second task is completed. If the first value is less than or equal to the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel.

[0035] The aforementioned first threshold can be a value set by the user, such as 50%, 40%, etc. This application does not limit the specific value of the aforementioned first threshold.

[0036] The above solution can interrupt the execution of corresponding tasks according to different situations, which can flexibly handle task interruption and improve the flexibility of interruption.

[0037] For example, if the access instruction corresponding to the second task is a non-32-bit nested access instruction, the kernel changes the access instruction corresponding to the second task to a 32-bit access instruction. Then, the kernel sends an indication instruction to the nested vector interrupt controller to compare the first priority and the second priority to obtain the comparison result. Based on the comparison result, the kernel determines whether to send an interrupt nesting instruction to the kernel. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed.

[0038] See Figure 4 , Figure 4 This application provides a schematic diagram of a chip data access error handling system, which is applied to, for example... Figure 1 The chip shown includes: an MCM, a core, and a nested vector interrupt controller. The core is connected to both the MCM and the nested vector interrupt controller. The system includes: MCM is used to receive the first access instruction for miscellaneous processing. MCM identifies whether the first access instruction is a 32-bit access instruction. The MCM is also used to send a stop request instruction to the kernel when it is determined to be a non-32-bit access instruction. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working.

[0039] For example, the MCM is also used to receive the kernel's RUN command and control the MCM state to change from a non-working state to a normal working state.

[0040] For example, the MCM is also used to receive front-door instructions from the kernel and back-door instructions from external devices, determining the execution order of the front-door and back-door instructions based on arbitration configuration. This method uses arbitration configuration to determine the execution order of front-door and back-door instructions, thereby avoiding conflicts between front-door and back-door instructions that could affect the efficiency of the MCM.

[0041] For example, determining the execution order of front-door and back-door instructions based on the arbitration configuration specifically includes: If the arbitration is configured as polling, the MCM will execute the front door instruction and the back door instruction in rotation. If the arbitration is configured with a fixed priority and front door priority, then the MCM will execute the front door instructions first. If the arbitration is configured with a fixed priority and backdoors take precedence, then the MCM will execute frontdoor instructions first.

[0042] For example, a nested vector interrupt controller receives interrupt commands sent by peripheral devices and obtains the first priority of the first task corresponding to the interrupt command. The nested vector interrupt controller obtains the second priority of the second task being processed by the kernel. When the kernel determines that the second task is a miscellaneous task, it obtains whether the access instruction corresponding to the second task is a 32-bit access instruction. If the access instruction corresponding to the second task is a nested 32-bit access instruction, the kernel sends an indication instruction to the nested vector interrupt controller, instructing the nested vector interrupt controller to compare the first priority and the second priority to obtain a comparison result. Based on the comparison result, the kernel determines whether to send an interrupt nesting instruction to the kernel. This interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed.

[0043] For example, obtaining the first priority of the first task corresponding to the interrupt instruction specifically includes: The chip's nested vector interrupt controller extracts the system memory map of the first task from the interrupt instruction. The memory map includes a memory space mapping table. Based on the memory space mapping table, the IPR value corresponding to the first task is extracted, and the first priority corresponding to the first task is determined based on the value.

[0044] For example, determining whether to send an interrupt nesting instruction to the kernel based on the comparison result specifically includes: If the comparison result is that the first priority is greater than the second priority, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel; If the comparison result is that the first priority is less than the second priority, the nested vector interrupt controller will immediately stop sending an interrupt nesting instruction to the kernel. The nested vector interrupt controller will receive the execution completion instruction sent by the kernel after the second task is completed, and obtain the third priority of the third task that the kernel will execute. If the first priority is greater than the third priority, the nested vector interrupt controller will immediately send an interrupt nesting instruction to the kernel. If the first priority is less than the third priority, the nested vector interrupt controller will discard the interrupt instruction. If the comparison result is that the first priority equals the second priority, the nested vector interrupt controller obtains the first value of the execution progress of the second task. If the first value is greater than the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel after the second task is completed. If the first value is less than or equal to the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel.

[0045] It is understood that, in order to achieve the aforementioned functions, the above-described apparatus includes hardware and / or software modules corresponding to the execution of each function. Based on the algorithmic steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0046] This embodiment can divide the electronic device into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0047] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0048] When using integrated units, the user equipment may include a processing module and a storage module. The processing module can be used to control and manage the actions of the user equipment; for example, it can support the electronic device in executing the steps performed by the acquisition unit, communication unit, and processing unit described above. The storage module can support the electronic device in executing stored program code and data.

[0049] The processing module can be a processor or a controller. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.

[0050] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the user equipment. In other embodiments of this application, the user equipment may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0051] Please see Figure 5 , Figure 5This application provides an electronic device 50, which includes a processor 501, a memory 502, and a communication interface 503. The processor 501, memory 502, and communication interface 503 are interconnected via a bus. The specific structure within the processor of the above-mentioned electronic device can be as follows: Figure 1 The chip shown.

[0052] The memory 502 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and is used for related computer programs and data. The communication interface 503 is used for receiving and sending data.

[0053] Processor 501 can be one or more central processing units (CPUs). If processor 501 is a CPU, the CPU can be a single-core CPU or a multi-core CPU.

[0054] Processor 501 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). Different processing units may be independent components or integrated into one or more processors. In some embodiments, the user equipment may also include one or more processing units. The controller can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution. In other embodiments, the processing unit may also include a memory for storing instructions and data. For example, the memory in the processing unit may be a cache memory. This memory can store instructions or data that the processing unit has just used or that is repeatedly used. If the processing unit needs to reuse the instruction or data, it can directly retrieve it from the memory. This avoids repeated access, reduces the waiting time of the processing unit, and thus improves the efficiency of the user equipment in processing data or executing instructions.

[0055] In some embodiments, the processor 501 may include one or more interfaces. These interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM card interface, and / or a USB interface, etc. The USB interface is a USB standard-compliant interface, specifically a Mini USB interface, a Micro USB interface, a USB Type-C interface, etc. The USB interface can be used to connect a charger to charge the user device, and can also be used for data transfer between the user device and peripheral devices. The USB interface can also be used to connect headphones for audio playback.

[0056] If the electronic device 50 is a user device or terminal device, such as a smartphone, computer device, or server, the processor 501 in the electronic device 50 is used to read the computer program code stored in the memory 502 and control the nested vector interrupt controller to perform the following operations: The nested vector interrupt controller receives interrupt commands sent by peripheral devices and obtains the first priority of the first task corresponding to the terminal command; The nested vector interrupt controller acquires the second priority of the second task that the kernel is currently processing. The nested vector interrupt controller compares the first priority and the second priority to obtain a comparison result. Based on the comparison result, it determines whether to send an interrupt nesting instruction to the kernel. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed. The comparison results specifically include: First priority > second priority, first priority < second priority, or first priority = second priority.

[0057] Optionally, obtaining the first priority of the first task corresponding to the terminal instruction specifically includes: The nested vector interrupt controller extracts the system memory map of the first task from the interrupt instruction. The memory map includes a memory space mapping table. Based on the memory space mapping table, the value of the interrupt priority register corresponding to the first task is extracted, and the first priority corresponding to the first task is determined based on the value.

[0058] Optionally, the nested vector interrupt controller acquiring the second priority of the second task being processed by the kernel specifically includes: The nested vector interrupt controller sends a query request to the kernel via the dedicated peripheral bus (PPB) and receives the query response returned by the kernel via the PPB. The query response includes the second priority of the second task.

[0059] Optionally, determining whether to send an interrupt nesting instruction to the kernel based on the comparison result specifically includes: If the comparison result is that the first priority is greater than the second priority, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel.

[0060] Optionally, determining whether to send an interrupt nesting instruction to the kernel based on the comparison result specifically includes: If the comparison result is that the first priority is less than the second priority, the nested vector interrupt controller will immediately stop sending an interrupt nesting instruction to the kernel. The nested vector interrupt controller will receive the execution completion instruction sent by the kernel after the second task is completed, and obtain the third priority of the third task that the kernel will execute. If the first priority is greater than the third priority, the nested vector interrupt controller will immediately send an interrupt nesting instruction to the kernel. If the first priority is less than the third priority, the nested vector interrupt controller will discard the interrupt instruction.

[0061] Optionally, determining whether to send an interrupt nesting instruction to the kernel based on the comparison result specifically includes: If the comparison result is that the first priority equals the second priority, the nested vector interrupt controller obtains the first value of the execution progress of the second task. If the first value is greater than the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel after the second task is completed. If the first value is less than or equal to the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel.

[0062] All relevant content in each scenario involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0063] This application also provides a computer-readable storage medium storing a computer program that, when run on a network device,... Figure 2 The method and flow shown are thus implemented.

[0064] This application also provides a computer program product, which, when run on a terminal, provides a solution for... Figure 2 The method and flow shown are thus implemented.

[0065] The above primarily describes the solutions of the embodiments of this application from the perspective of the method execution process. It is understood that, in order to achieve the above functions, the electronic device includes the corresponding hardware structure and / or software template for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments provided herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0066] This application embodiment can divide the electronic device into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0067] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and templates involved are not necessarily essential to this application.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0070] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0072] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0073] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

Claims

1. A method for handling data access errors in a chip, characterized in that, The method includes the following steps: The chip's miscellaneous control module (MCM) receives the first access instruction for miscellaneous processing. The MCM identifies whether the first access instruction is a 32-bit access instruction. When the chip's MCM is determined to be a non-32-bit access instruction, a stop request instruction is sent to the kernel. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working. The chip's nested vector interrupt controller receives interrupt commands sent by peripheral devices and obtains the first priority of the first task corresponding to the interrupt command; The nested vector interrupt controller obtains the second priority of the second task being processed by the kernel. When the kernel determines that the second task is a miscellaneous task, it obtains whether the access instruction corresponding to the second task is a 32-bit access instruction. If the access instruction corresponding to the second task is a nested 32-bit access instruction, the kernel sends an indication instruction to the nested vector interrupt controller to instruct the nested vector interrupt controller to compare the first priority and the second priority to obtain the comparison result. Based on the comparison result, it determines whether to send an interrupt nesting instruction to the kernel. If the access instruction corresponding to the second task is a non-32-bit nested access instruction, the kernel changes the access instruction corresponding to the second task to a 32-bit access instruction. Then, the kernel sends an indication instruction to the nested vector interrupt controller to compare the first priority and the second priority to obtain the comparison result. Based on the comparison result, the kernel determines whether to send an interrupt nesting instruction to the kernel. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed.

2. The method according to claim 1, characterized in that, The method further includes: The chip's MCM receives the kernel's RUN command and controls the MCM state to change from a non-working state to a normal working state.

3. The method according to claim 1, characterized in that, The method further includes: The chip's MCM receives front-door instructions from the core and back-door instructions from external devices, and determines the execution order of the front-door and back-door instructions based on the arbitration configuration.

4. The method according to claim 3, characterized in that, The determination of the execution order of front-door and back-door instructions based on the arbitration configuration specifically includes: If the arbitration is configured as polling, the MCM will execute the front door instruction and the back door instruction in rotation. If the arbitration is configured with a fixed priority and front door priority, then the MCM will execute the front door instructions first. If the arbitration is configured with a fixed priority and backdoors take precedence, then the MCM will execute frontdoor instructions first.

5. The method according to claim 1, characterized in that, The specific steps of obtaining the first priority of the first task corresponding to the interrupt instruction include: The chip's nested vector interrupt controller extracts the system memory map of the first task from the interrupt instruction. The memory map includes a memory space mapping table. Based on the memory space mapping table, the IPR value corresponding to the first task is extracted, and the first priority corresponding to the first task is determined based on the value.

6. The method according to claim 1, characterized in that, The process of determining whether to send an interrupt nesting instruction to the kernel based on the comparison result specifically includes: If the comparison result is that the first priority is greater than the second priority, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel; If the comparison result is that the first priority is less than the second priority, the nested vector interrupt controller will immediately stop sending an interrupt nesting instruction to the kernel. The nested vector interrupt controller will receive the execution completion instruction sent by the kernel after the second task is completed, and obtain the third priority of the third task that the kernel will execute. If the first priority is greater than the third priority, the nested vector interrupt controller will immediately send an interrupt nesting instruction to the kernel. If the first priority is less than the third priority, the nested vector interrupt controller will discard the interrupt instruction. If the comparison result is that the first priority equals the second priority, the nested vector interrupt controller obtains the first value of the execution progress of the second task. If the first value is greater than the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel after the second task is completed. If the first value is less than or equal to the first threshold, the nested vector interrupt controller immediately sends an interrupt nesting instruction to the kernel.

7. A data access error handling system for a chip, the system being applied to a chip, characterized in that, The chip includes: a miscellaneous control module (MCM), a core, and a nested vector interrupt controller. The core is connected to both the MCM and the nested vector interrupt controller. The system includes: MCM is used to receive the first access instruction for miscellaneous processing. MCM identifies whether the first access instruction is a 32-bit access instruction. The MCM is also used to send a stop request instruction to the kernel when it is determined to be a non-32-bit access instruction. The stop request instruction is used to instruct the kernel to control the power module to be in stop mode. In stop mode, the clock signal of the power module of the MCM is in the off state. When the registers of the MCM are in the off state, the registers of the MCM are not working. The nested vector interrupt controller is used to receive interrupt commands sent by peripheral devices and obtain the first priority of the first task corresponding to the interrupt command; the nested vector interrupt controller obtains the second priority of the second task being processed by the kernel; when the kernel determines that the second task is a miscellaneous task, it obtains whether the access instruction corresponding to the second task is a 32-bit access instruction. If the access instruction corresponding to the second task is a nested 32-bit access instruction, the kernel sends an indication instruction to the nested vector interrupt controller to instruct the nested vector interrupt controller to compare the first priority and the second priority to obtain the comparison result, and determines whether to send an interrupt nesting instruction to the kernel based on the comparison result; If the access instruction corresponding to the second task is a non-32-bit nested access instruction, the kernel changes the access instruction corresponding to the second task to a 32-bit access instruction. Then, the kernel sends an indication instruction to the nested vector interrupt controller to compare the first priority and the second priority to obtain the comparison result. Based on the comparison result, the kernel determines whether to send an interrupt nesting instruction to the kernel. The interrupt nesting instruction is used to instruct the kernel to interrupt the execution of the task being processed.

8. An electronic device comprising a processor, a memory, a communication interface, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs comprising instructions for performing the steps of the method as claimed in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program that, when run on a computer device, performs the method as described in any one of claims 1-6.

Images