Method and apparatus for data access, electronic device, storage medium

Abstract

The application relates to the technical field of flash memory control, and discloses a method for data access, which comprises the following steps: obtaining a to-be-accessed mapping address of a chip, a mapping space starting address of the chip, a physical starting address of a flash memory, an expected mapping partition index value and a mapping space capacity of the chip; determining whether an index range is qualified according to the expected mapping partition index value; in the case that the index range is qualified, calculating the to-be-accessed mapping address, the mapping space starting address, the physical starting address, the expected mapping partition index value and the mapping space capacity according to a first preset algorithm to obtain a target physical address of the flash memory. In this way, by dynamically changing the mapping relationship between the to-be-accessed mapping address and the target physical address, all the physical addresses in the flash memory can be accessed. In the chip-in-execution mode of a serial flash memory controller, the space utilization rate of the flash memory can be improved. The application further discloses an apparatus for data access, an electronic device and a storage medium.

Description

Technical Field

[0001] This application relates to the field of flash memory control technology, such as a method and apparatus for data access, electronic devices, and storage media. Background Technology

[0002] Currently, there is a common need for communication between chips and flash memory. Based on the transmission characteristics of QSPI (Quad SPI), communication between chips and flash memory via QSPI is becoming increasingly widespread. For example, Chinese patent document CN112463651A discloses that in computer technology, communication with flash memory is often required. In accessing flash memory, the Serial Peripheral Interface (SPI) is typically used. However, because SPI is single-wire, data transmission speed is slow when accessing flash memory via SPI. The inventors discovered that QSPI is an extension of the SPI interface, with even wider applications. Based on the SPI protocol, QSPI enhances its functionality by adding a queued transmission mechanism, resulting in the Queued Serial Peripheral Interface protocol. Simultaneously, with the increasing application of QSPI, the application of QSPI Flash (Quad SPI Flash) is also becoming more widespread. For example, Chinese patent document CN115248790A discloses that QSPI Flash (Quad SPI Flash) has fewer pins, is simpler to operate, has a larger storage space, and is lower in cost. Its application is becoming increasingly widespread in SoC (System on Chip) chips and embedded systems. One application is software code storage, where the CPU or other processor can directly read instructions from Flash and run them, known as in-chip execution, or eXecute In Place (XIP). The second application is data storage, storing fixed initialization data or software code (the code needs to be copied to SRAM before it can run).

[0003] Serial flash memory controllers typically support XIP (execute-in-place) mode, allowing the CPU (central processing unit) or other processors to directly read and execute instructions from QSPI Flash. In related technologies, a contiguous, fixed address space is allocated within the chip's system memory as the QSPI mapping space. Once the chip design is completed, the QSPI mapping space allocated to users is fixed. This means that the size and address range of the QSPI mapping space cannot be modified, and users cannot adjust the translation between the mapping space address and the physical address of the QSPI Flash. However, chip designers often cannot predict the required QSPI Flash size during the design phase, which often results in a mismatch between the allocated QSPI mapping space capacity and the actual QSPI Flash capacity used by the user. Since the mapping space address typically corresponds to only one physical address, when the serial flash memory controller is in XIP mode, users can only access the physical address range that corresponds to the fixed mapping space address range, and cannot access physical addresses outside this fixed range. Figure 1 This is a schematic diagram of the first type of mapping relationship, such as... Figure 1 As shown, a QSPI mapping space 2 is set on the chip system memory space 1. The QSPI mapping space 2 corresponds to the mapping area on the QSPI Flash 3. That is, the serial flash memory controller can only access the mapping area on the QSPI Flash 3, but cannot access the part of the QSPI Flash 3 that is outside the mapping area.

[0004] In implementing the embodiments of this disclosure, it has been found that at least the following problem exists in the related art: the space utilization of flash memory is low in the on-chip execution mode of the serial flash memory controller. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a method, apparatus, electronic device, and storage medium for data access, which facilitates improved space utilization of flash memory in an in-chip execution mode of a serial flash memory controller.

[0007] In some embodiments, the data access method is applied to a serial flash memory controller, which is in an in-chip execution mode. The data access method includes: obtaining the chip's mapping address to be accessed, the chip's mapping space start address, the flash memory's physical start address, the desired mapping partition index value, and the chip's mapping space capacity; determining whether the index range is qualified based on the desired mapping partition index value; if the index range is qualified, calculating the target physical address of the flash memory using the mapping address to be accessed, the mapping space start address, the physical start address, the desired mapping partition index value, and the mapping space capacity according to a first preset algorithm.

[0008] In some embodiments, determining whether an index range is qualified based on the expected mapped partition index value includes: obtaining the expected flash memory capacity; calculating the maximum index value using the expected flash memory capacity and the mapped space capacity according to a second preset algorithm; comparing the maximum index value and the expected mapped partition index value, and determining whether the index range is qualified based on the comparison result.

[0009] In some embodiments, determining whether the index range is qualified based on the comparison result includes: determining that the index range is qualified when the expected mapping partition index value is less than the maximum index value; and / or, determining whether the mapping address to be accessed is within a preset spatial mapping address range when the expected mapping partition index value is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is within the spatial mapping address range.

[0010] In some embodiments, after obtaining the target physical address of the flash memory, the method further includes: reading the data stored at the target physical address of the flash memory.

[0011] In some embodiments, the data access apparatus is applied to a serial flash memory controller, the serial flash memory controller being in an in-chip execution mode; the data access apparatus includes: an acquisition module configured to acquire a target mapping address of the chip, a mapping space start address of the chip, a physical start address of the flash memory, a desired mapping partition index value, and a mapping space capacity of the chip; a determination module configured to determine whether an index range is qualified based on the desired mapping partition index value; and a calculation module configured to, if the index range is qualified, calculate using the target mapping address, the mapping space start address, the physical start address, the desired mapping partition index value, and the mapping space capacity according to a first preset algorithm to obtain the target physical address of the flash memory.

[0012] In some embodiments, the determining module is configured to determine whether the index range is qualified based on the expected mapped partition index value in the following manner: obtaining the expected flash memory capacity; calculating the maximum index value using the expected flash memory capacity and the mapped space capacity according to a second preset algorithm; comparing the maximum index value and the expected mapped partition index value, and determining whether the index range is qualified based on the comparison result.

[0013] In some embodiments, the determining module is configured to determine whether the index range is qualified based on the comparison result in the following manner: if the expected mapping partition index value is less than the maximum index value, the index range is determined to be qualified; and / or, if the expected mapping partition index value is equal to the maximum index value, the module determines whether the mapping address to be accessed is within a preset spatial mapping address range; if the mapping address to be accessed is within the spatial mapping address range, the index range is determined to be qualified.

[0014] In some embodiments, the apparatus for data access further includes a reading module configured to read data stored at the target physical address of the flash memory after obtaining the target physical address of the flash memory.

[0015] In some embodiments, the electronic device includes a processor and a memory storing program instructions, the processor being configured to perform the above-described method for data access when executing the program instructions.

[0016] In some embodiments, the storage medium stores program instructions that, when executed, perform the aforementioned data access method.

[0017] The data access method, apparatus, electronic device, and storage medium provided in this disclosure can achieve the following technical effects: By obtaining the chip's mapped address to be accessed, the chip's mapped space start address, the flash memory's physical start address, the desired mapped partition index value, and the chip's mapped space capacity, the index range is determined based on the desired mapped partition index value. If the index range is acceptable, the target physical address of the flash memory is obtained by calculating using the mapped address to be accessed, the mapped space start address, the physical start address, the desired mapped partition index value, and the mapped space capacity according to a first preset algorithm. This allows access to all physical addresses in the flash memory by dynamically changing the mapping relationship between the mapped address to be accessed and the target physical address in the on-chip execution mode of the serial flash memory controller. Therefore, in the on-chip execution mode of the serial flash memory controller, it is easier to improve the space utilization of the flash memory.

[0018] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0020] Figure 1 This is a schematic diagram of the first mapping relationship provided in the embodiments of this disclosure;

[0021] Figure 2 This is a schematic diagram of signal transmission for a serial flash memory controller provided in an embodiment of this disclosure;

[0022] Figure 3 This is a schematic diagram of the structure and signals of a mapping address translation module provided in an embodiment of this disclosure;

[0023] Figure 4 This is a schematic diagram of a data access method provided in an embodiment of this disclosure;

[0024] Figure 5 This is a schematic diagram of the second mapping relationship provided in the embodiments of this disclosure;

[0025] Figure 6 This is a schematic diagram of a data access apparatus provided in an embodiment of this disclosure;

[0026] Figure 7 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure.

[0027] Figure label:

[0028] 1: Chip system memory space; 2: QSPI mapping space; 3: QSPI Flash; 4: Serial flash controller; 5: XIP port; 6: Command port; 7: Status / control register group; 8: Data and control signal module; 9: Mapped address translation module; 10: SPI controller. Detailed Implementation

[0029] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0030] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] Unless otherwise stated, the term "multiple" means two or more.

[0032] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0033] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0034] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0035] In some embodiments, the serial flash memory controller of this application is, for example, a QSPI controller. The flash memory in this application is QSPI Flash (serial flash memory).

[0036] In some embodiments, Figure 2 This is a schematic diagram of the signal transmission of a serial flash memory controller. (Combined with...) Figure 2As shown, the serial flash controller 4 includes: a mapped address translation module 9, a command port 6, a status / control register group 7, a data and control signal module 8, an SPI controller 10, and an XIP port 5. The command port 6 includes the status / control register group 7. The SPI controller 10 accesses the QSPI Flash 3 via the serial bus. When the serial flash controller is in command mode, it reads data in command mode or writes data in command mode through the command port. In command mode, the user configures the status / control register group through the command port. The command port obtains the parameters of the user-configured status / control register group and then transmits status / control register signals to the SPI controller based on these parameters, enabling the SPI (Serial Peripheral Interface) controller to read, write, and erase data in the external QSPI Flash via the serial bus. Typically, reading, writing, and erasing data in the external QSPI Flash is based on the internal physical address of the QSPI Flash, which ranges from (FlsAddrStart, FlsAddrEnd). Where FlsAddrStart is the physical start address and FlsAddrEnd is the physical end address. Typically, FlsAddrStart = 0. The internal physical address of the QSPI Flash is independent of the chip system memory space, and the two do not interfere with each other. Before the serial flash controller executes the on-chip execution mode, it is usually necessary to configure the on-chip execution mode command parameters in command mode first, and then switch the serial flash controller's operating mode to on-chip execution mode. When the serial flash controller is in on-chip execution mode, the serial flash controller's mapping address translation module obtains the mapping address to be accessed (MemAddr) from the CPU's read command and converts the mapping address to be accessed into the target physical address of the QSPI Flash (FlsAddr). Where FlsAddrStart ≤ FlsAddr ≤ FlsAddrEnd. Then, the mapping address translation module sends the target physical address to the status / control register group of the command port. Simultaneously, the status / control register group of the command port also receives the on-chip execution mode command parameters. The command port obtains the parameters from the status / control register group and transmits data signals with the data and control signal module. At the same time, the command port receives status signals sent by the data and control signal module. The data and control signal module sends control signals and data to the SPI controller. The SPI controller reads the data from the target physical address FlsAddr via the serial bus and sends the data to the data and control signal module, enabling the data and control signal module to receive the data. The SPI controller also sends data to the XIP port in the form of data packets.Data is read from the chip's execution mode via the XIP port.

[0037] In some embodiments, when the serial flash controller is in XIP mode, the user can only access the physical address range that corresponds to a fixed range of mapped address space, and cannot access physical addresses outside this fixed range. Physical addresses outside the fixed range can only be accessed through command mode. Therefore, when the serial flash controller is in XIP mode, there is a situation where the space utilization of the serial flash memory is low. By improving the mapping address translation module, the space utilization of the flash memory can be improved in the on-chip execution mode of the serial flash controller. The serial flash controller includes a mapping address translation module, which is used to convert the mapped address to be accessed on the chip into the target physical address of the flash memory. Figure 3 This is a schematic diagram of the structure and signal of the address mapping module. (Combined with...) Figure 3 As shown, the mapping address translation module 9 includes: a mapping address translation calculation unit, a serial flash memory capacity register (FLSZ), a serial flash memory partition index value register (FPI), a memory mapping area highest address register (MADDR), a serial flash memory physical partition number register (FPN), and a serial flash memory partition status register (FPS). The serial flash memory capacity register, the serial flash memory partition index value register, and the mapping address to be accessed in the CPU's read command are input into the mapping address translation calculation unit for calculation. Based on the calculation results, the mapping address translation calculation unit writes data to the memory mapping area highest address register, the serial flash memory physical partition number register, and the serial flash memory partition status register, respectively. Simultaneously, the mapping address to be accessed is converted into a target physical address, and the target physical address is sent to the command port. The command port also receives on-chip execution mode command parameters. Specifically, the serial flash memory capacity register stores the user-inputted desired flash memory capacity; the serial flash memory partition index value register stores the user-inputted desired mapping partition index value; the memory mapping area highest address register stores the high address of the access address range of the XIP mapping partition; the serial flash memory physical partition number register stores the maximum index value; and the serial flash memory partition status register is used to set alarms. The user can read the value of the highest address register of the memory-mapped area to determine whether the CPU has accessed an illegal area. The maximum index value and the high address of the access address range of the XIP mapped partition are both calculated by the mapping address translation calculation unit. Whether the serial flash partition status register should be set to alarm is also determined by the mapping address translation calculation unit.

[0038] In some embodiments, before the serial flash controller accesses the QSPI Flash using XIP mode, the user needs to configure the serial flash capacity register and then the serial flash partition index value register to access the target mapping area. The target mapping area is the mapping area that the user expects to access. Next, the serial flash controller's operating mode is switched to XIP mode, and the CPU initiates an access to the target physical address mapping address. This mapping address is transmitted to the mapping address translation calculation unit for address translation, and the relevant status or calculated value is stored in the memory mapping area highest address register, the serial flash physical partition number register, and the serial flash partition status register. Then, the calculated output, along with the on-chip execution mode command parameters, is used to read the data at the target physical address through the command port and transmit the data to the CPU through the XIP port.

[0039] Combination Figure 4 As shown, this disclosure provides a method for data access, applied to a serial flash memory controller, the serial flash memory controller being in an on-chip execution mode; the method for data access includes:

[0040] In step S401, the serial flash controller obtains the chip's mapping address to be accessed, the chip's mapping space start address, the flash memory's physical start address, the expected mapping partition index value, and the chip's mapping space capacity.

[0041] In step S402, the serial flash controller determines whether the index range is qualified based on the expected mapped partition index value.

[0042] In step S403, if the index range is qualified, the serial flash controller calculates the target physical address of the flash memory using the address to be accessed, the starting address of the mapping space, the physical starting address, the expected mapping partition index value, and the mapping space capacity according to the first preset algorithm.

[0043] The data access method provided in this disclosure involves obtaining the chip's target mapped address, the chip's mapped space start address, the flash memory's physical start address, the desired mapped partition index value, and the chip's mapped space capacity. The validity of the index range is determined based on the desired mapped partition index value. If the index range is valid, the target physical address of the flash memory is obtained by calculating using the target mapped address, the mapped space start address, the physical start address, the desired mapped partition index value, and the mapped space capacity according to a first preset algorithm. This allows access to all internal physical addresses in the flash memory by dynamically changing the mapping relationship between the target mapped address and the target physical address in the on-chip execution mode of the serial flash memory controller. Therefore, in the on-chip execution mode of the serial flash memory controller, this facilitates improved flash memory space utilization.

[0044] In some embodiments, the desired mapped partition index value is obtained from the serial flash partition index value register.

[0045] Furthermore, the chip's mapping space capacity is obtained as follows: Calculate XIPMEMSZ = MemAddrEnd - MemAddrStart + 1 to obtain the mapping space capacity. Where XIPMEMSZ is the mapping space capacity. (MemAddrStart, MemAddrEnd) represents the address range of the QSPI mapping space. MemAddrStart is the starting address of the QSPI mapping space. MemAddrEnd is the ending address of the QSPI mapping space.

[0046] Furthermore, based on the first preset algorithm, the target physical address of the flash memory is obtained by calculating using the address to be accessed, the starting address of the mapping space, the physical starting address, the desired mapping partition index value, and the mapping space capacity. This includes calculating FlsAddr = (MemAddr - MemAddrStart) + (FlsAddrStart + FPI × XIPMEMSZ) to obtain the target physical address. Where FlsAddr is the target physical address; MemAddr is the address to be accessed; MemAddrStart is the starting address of the mapping space; FlsAddrStart is the physical starting address; FPI is the desired mapping partition index value; and XIPMEMSZ is the mapping space capacity. Thus, by obtaining the desired mapping partition index value, the address to be accessed can be mapped to the mapping area corresponding to the desired mapping partition index value in the XIP mode of the serial flash memory controller. For example, when FPI = 1, the address to be accessed can be mapped to the first mapping area using the above formula. Figure 5 This is a schematic diagram of the second type of mapping relationship, combined with... Figure 5 As shown, a QSPI mapping space 2 is provided on the chip system memory space 1. By changing the desired mapping partition index value, the mapping space address of QSPI mapping space 2 can be mapped to the first mapping area, second mapping area, or third mapping area of ​​QSPI Flash 3, etc. Traditional address mapping methods can only map the address to be accessed to the zeroth mapping area, and cannot access the first, second, or third mapping areas in higher address ranges. Therefore, the address translation scheme of this application can improve the access space of the serial flash memory controller to the flash memory in XIP mode.

[0047] Optionally, determining whether the index range is acceptable based on the expected mapped partition index value includes: obtaining the expected flash memory capacity; calculating the maximum index value using the expected flash memory capacity and the mapped space capacity according to a second preset algorithm; comparing the maximum index value with the expected mapped partition index value, and determining whether the index range is acceptable based on the comparison result. In this way, by comparing the maximum index value and the expected mapped partition index value, it is possible to quickly determine whether the user's configured expected mapped partition index value is incorrect, thereby facilitating reminders to the user to correctly configure the expected mapped partition index value and avoid the inability to access the internal physical address of the flash memory.

[0048] In some embodiments, the desired flash memory capacity is obtained from the serial flash memory capacity register.

[0049] Furthermore, according to the second preset algorithm, the maximum index value is obtained by calculating using the expected flash memory capacity and the mapped space capacity, including: calculating... Obtain the maximum index value. Here, FPImax is the maximum index value, FLSZ is the desired flash memory capacity, and XIPMEMSZ is the mapped space capacity. The rounding operator is: "=" for equals, "÷" for division, "+" for addition, "-" for subtraction, and "×" for multiplication.

[0050] Furthermore, the index range is determined to be valid based on the comparison results, including: if the expected mapped partition index value is less than the maximum index value, the index range is considered valid; and / or, if the expected mapped partition index value is equal to the maximum index value, it is determined whether the mapped address to be accessed is within the preset spatial mapping address range; if the mapped address to be accessed is within the spatial mapping address range, the index range is considered valid. The preset spatial mapping address range is (MemAddrStart, MemAddrStart + (FLSZ mod XIPMEMSZ) - 1), where mod represents the modulo operation. Therefore, the index range is only valid if 0 ≤ FPI ≤ FPImax. Thus, if the expected mapped partition index value is less than the maximum index value, the physical address of the flash memory can definitely be accessed. Therefore, if the expected mapped partition index value is less than the maximum index value, the index range is considered valid. If the expected mapped partition index value is equal to the maximum index value, since the capacity of the QSPI Flash may not be an integer multiple of the mapped space capacity, the mapped area corresponding to the maximum index value may include inaccessible out-of-range areas. Further determination is needed to determine whether the mapped address to be accessed is within the spatial mapping address range, thereby ensuring correct access to the flash memory. Combined with... Figure 5As shown, a QSPI mapping space 2 is set on the chip system memory space 1. Assume the maximum index value is three. If the expected mapping partition index value is also three, the mapping space address of QSPI mapping space 2 is mapped to the third mapping area of ​​QSPI Flash 3. However, there will be out-of-bounds areas within the third mapping area.

[0051] Optionally, determining whether the index range is qualified based on the comparison result also includes: displaying an error message to the user if the index range is determined to be unqualified.

[0052] In some embodiments, an error message is displayed to the user by setting the FPS status register. This is because when the FPN is configured as... At times, the CPU may access an out-of-range region. When this happens, the FPS status register is set to indicate an error. This alerts the user to promptly change configuration parameters, ensuring normal access to the physical address space of the flash memory.

[0053] Optionally, after determining whether the index range is qualified based on the comparison result, the method further includes: obtaining the highest address of the mapped region that can be accessed by each mapped region in XIP mode; and storing the highest address of the mapped region that can be accessed by each mapped region in the memory mapped region highest address register.

[0054] Furthermore, the highest address of the mapped region accessible in XIP mode is obtained through the following method: by calculating...

[0055]

[0056] Obtain the highest address of the mapped region accessible in XIP mode. Here, MADDR(FPI) is the highest address of the mapped region with the mapping region set to FPI.

[0057] Optionally, after obtaining the target physical address of the flash memory, the process further includes reading the data stored at the target physical address of the flash memory. This allows the accessed data to be easily transmitted back to the CPU, completing the CPU's access to the flash memory.

[0058] Optionally, before obtaining the chip's target mapped address, the chip's mapped space start address, the flash memory's physical start address, the desired mapped partition index value, and the chip's mapped space capacity, the method further includes: switching the serial flash memory controller to command mode, and in response to user input commands, storing different applications or configuration files in each mapped partition of the flash memory. This stores different applications or configuration files in different mapped areas, and because there is physical isolation between each mapped area, applications or configuration files stored in different mapped areas cannot access each other, ensuring the security of each application or configuration file. Simultaneously, in conjunction with the data access method of this application, applications or configuration files in each mapped area can be accessed separately. Therefore, while allowing normal access to each application or configuration file, the security of each application or configuration file is guaranteed.

[0059] In some embodiments, the data stored at the target physical address is the user program downloaded to the target physical address via command mode. The user program is stored in an external QSPI Flash, and the code corresponding to the user program stored in the external QSPI Flash is executed directly in XIP mode. To facilitate application upgrades, the capacity of the QSPI Flash is chosen to be twice the capacity of the QSPI mapping space, i.e., XIPMEMSZ = 2 × FLSZ. When the user program is stored in the zeroth mapping area, the desired mapping partition index value of the serial flash partition index register is configured to 0, mapping the chip system memory mapping space to the zeroth mapping area, allowing the CPU to directly execute the code in the zeroth mapping area. In the case of application upgrades, the user downloads the new version of the application to the first mapping area via command mode. After the download is complete, the desired mapping partition index value of the serial flash partition index register is configured to 1, mapping the chip system memory mapping space to the first mapping area. This maps the chip system memory mapping space to the first mapping area, allowing the CPU to access the new version of the application in the first mapping area when accessing the system memory mapping space. The next time the application is updated, the user only needs to download the new version of the application to the zeroth mapping area and configure the serial flash partition index value register to complete the application update. In this way, both the new and old versions of the application exist within the address range of the QSPI mapping space. Because the different mapping areas are physically isolated from each other, in XIP mode, it is impossible to corrupt inactive mapping areas, thus providing a higher level of protection for the integrity of the old application. In the event of accidental corruption of the new application, the system can immediately switch to the old application, thereby maintaining stable application operation.

[0060] In some embodiments, if the capacity of the QSPI Flash is selected to be N times the capacity of the QSPI mapping space, i.e., XIPMEMSZ = N × FLSZ, users can store different applications or configuration files in different mapping areas according to different needs. Since there is physical isolation between each mapping area, applications or configuration files stored in different mapping areas cannot access each other, thus ensuring the security of each application or configuration file.

[0061] Combination Figure 6 As shown, this embodiment of the disclosure provides a data access device 12, applied to a serial flash memory controller, the serial flash memory controller being in an in-chip execution mode; the data access device includes: an acquisition module 13, a determination module 14, and a calculation module 15. The acquisition module is configured to acquire the target mapped address of the chip, the starting address of the mapped space of the chip, the physical starting address of the flash memory, the desired mapped partition index value, and the mapped space capacity of the chip; the determination module is configured to determine whether the index range is qualified based on the desired mapped partition index value; the calculation module is configured to, if the index range is qualified, calculate the target physical address of the flash memory using the target mapped address, the starting address of the mapped space, the physical starting address, the desired mapped partition index value, and the mapped space capacity according to a first preset algorithm.

[0062] The data access apparatus provided in this disclosure acquires the chip's target mapped address, the chip's mapped space start address, the flash memory's physical start address, the desired mapped partition index value, and the chip's mapped space capacity via an acquisition module. A determination module determines whether the index range is acceptable based on the desired mapped partition index value. If the index range is acceptable, a calculation module performs calculations using the target mapped address, mapped space start address, physical start address, desired mapped partition index value, and mapped space capacity according to a first preset algorithm to obtain the target physical address of the flash memory. This allows access to all internal physical addresses in the flash memory by dynamically changing the mapping relationship between the target mapped address and the target physical address in the on-chip execution mode of the serial flash memory controller. Therefore, in the on-chip execution mode of the serial flash memory controller, it facilitates improved flash memory space utilization.

[0063] Optionally, the determining module is configured to determine whether the index range is qualified based on the expected mapped partition index value in the following manner: obtaining the expected flash memory capacity; calculating the maximum index value using the expected flash memory capacity and the mapped space capacity according to a second preset algorithm; comparing the maximum index value and the expected mapped partition index value, and determining whether the index range is qualified based on the comparison result.

[0064] Furthermore, the determination module is configured to determine whether the index range is qualified based on the comparison results in the following manner: if the expected mapped partition index value is less than the maximum index value, the index range is determined to be qualified; and / or, if the expected mapped partition index value is equal to the maximum index value, the mapping address to be accessed is determined to be within the preset spatial mapping address range; if the mapping address to be accessed is within the spatial mapping address range, the index range is determined to be qualified.

[0065] Optionally, the device for data access further includes a reading module configured to read data stored at the target physical address of the flash memory after obtaining the target physical address of the flash memory.

[0066] Combination Figure 7 As shown, this embodiment of the present disclosure provides an electronic device 11, including a processor 17 and a memory 18. Optionally, the device may further include a communication interface 19 and a bus 20. The processor 17, communication interface 19, and memory 18 can communicate with each other via the bus 20. The communication interface 19 can be used for information transmission. The processor 17 can invoke logical instructions in the memory 18 to execute the data access method described in the above embodiment.

[0067] The electronic device provided in this disclosure obtains the chip's target mapped address, the chip's mapped space start address, the flash memory's physical start address, the desired mapped partition index value, and the chip's mapped space capacity. It then determines whether the index range is acceptable based on the desired mapped partition index value. If the index range is acceptable, it calculates the target physical address of the flash memory using the target mapped address, the mapped space start address, the physical start address, the desired mapped partition index value, and the mapped space capacity according to a first preset algorithm. This allows access to all internal physical addresses in the flash memory by dynamically changing the mapping relationship between the target mapped address and the target physical address in the on-chip execution mode of the serial flash memory controller. Therefore, in the on-chip execution mode of the serial flash memory controller, it facilitates improved flash memory space utilization.

[0068] Furthermore, the logical instructions in the aforementioned memory 18 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0069] The memory 18, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 17 executes functional applications and data processing by running the program instructions / modules stored in the memory 18, that is, it implements the data access method in the above embodiments.

[0070] The memory 18 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 18 may include high-speed random access memory and may also include non-volatile memory.

[0071] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for data access.

[0072] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the above-described method for data access.

[0073] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0074] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0075] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0076] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0077] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A method for data access, characterized in that, Applied to a serial flash memory controller, wherein the serial flash memory controller is in on-chip execution mode; the method for data access includes: Obtain the chip's mapped address to be accessed, the chip's mapped space start address, the flash memory's physical start address, the expected mapped partition index value, and the chip's mapped space capacity; Determine whether the index range is acceptable based on the expected mapped partition index value; If the index range is acceptable, the target physical address of the flash memory is obtained by calculating using the address to be accessed, the starting address of the mapping space, the physical starting address, the expected mapping partition index value, and the mapping space capacity according to the first preset algorithm. Specifically, the target physical address of the flash memory is obtained by calculating the target physical address using the first preset algorithm, which utilizes the address to be accessed, the starting address of the mapping space, the physical starting address, the expected mapping partition index value, and the mapping space capacity. This includes calculating FlsAddr = (MemAddr - MemAddrStart) + (FlsAddrStart + FPI × XIPMEMSZ) to obtain the target physical address. Here, FlsAddr is the target physical address; MemAddr is the address to be accessed; MemAddrStart is the starting address of the mapping space; FlsAddrStart is the physical starting address; FPI is the expected mapping partition index value; and XIPMEMSZ is the mapping space capacity.

2. The method according to claim 1, characterized in that, Determining whether the index range is qualified based on the expected mapped partition index value includes: Obtain the desired flash memory capacity; The maximum index value is obtained by calculating using the expected flash memory capacity and the mapped space capacity according to the second preset algorithm; Compare the maximum index value with the expected mapped partition index value, and determine whether the index range is qualified based on the comparison result.

3. The method according to claim 2, characterized in that, The index range is determined based on the comparison results, including: If the expected mapped partition index value is less than the maximum index value, the index range is determined to be acceptable; and / or, If the expected mapping partition index value is equal to the maximum index value, determine whether the mapping address to be accessed is within the preset spatial mapping address range; if the mapping address to be accessed is within the spatial mapping address range, determine that the index range is qualified.

4. The method according to any one of claims 1 to 3, characterized in that, After obtaining the target physical address of the flash memory, the following is also included: Read the data stored at the target physical address in the flash memory.

5. An apparatus for data access, characterized in that, Applied to a serial flash memory controller, the serial flash memory controller being in an on-chip execution mode; the means for data access includes: The acquisition module is configured to acquire the chip's mapping address to be accessed, the chip's mapping space start address, the flash memory's physical start address, the expected mapping partition index value, and the chip's mapping space capacity. The determination module is configured to determine whether the index range is qualified based on the expected mapped partition index value; The calculation module is configured to, when the index range is qualified, calculate the target physical address of the flash memory using the address to be accessed, the starting address of the mapping space, the physical starting address, the expected mapping partition index value, and the mapping space capacity according to a first preset algorithm. Specifically, the target physical address of the flash memory is obtained by calculating the target physical address using the first preset algorithm, which utilizes the address to be accessed, the starting address of the mapping space, the physical starting address, the expected mapping partition index value, and the mapping space capacity. This includes calculating FlsAddr = (MemAddr - MemAddrStart) + (FlsAddrStart + FPI × XIPMEMSZ) to obtain the target physical address. Here, FlsAddr is the target physical address; MemAddr is the address to be accessed; MemAddrStart is the starting address of the mapping space; FlsAddrStart is the physical starting address; FPI is the expected mapping partition index value; and XIPMEMSZ is the mapping space capacity.

6. The apparatus according to claim 5, characterized in that, The module is configured to determine whether an index range is qualified based on the desired mapped partition index value in the following manner: Obtain the desired flash memory capacity; The maximum index value is obtained by calculating using the expected flash memory capacity and the mapped space capacity according to the second preset algorithm; Compare the maximum index value with the expected mapped partition index value, and determine whether the index range is qualified based on the comparison result.

7. The apparatus according to claim 6, characterized in that, The module is configured to determine whether an index range is valid based on the comparison results in the following manner: If the expected mapped partition index value is less than the maximum index value, the index range is determined to be acceptable; and / or, If the expected mapping partition index value is equal to the maximum index value, determine whether the mapping address to be accessed is within the preset spatial mapping address range; if the mapping address to be accessed is within the spatial mapping address range, determine that the index range is qualified.

8. The apparatus according to any one of claims 5 to 7, characterized in that, The device for data access also includes: The read module is configured to read the data stored at the target physical address of the flash memory after obtaining the target physical address of the flash memory.

9. An electronic device comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the method for data access as described in any one of claims 1 to 4 when executing the program instructions.

10. A storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the data access method as described in any one of claims 1 to 4.

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