Memory access methods, memory controllers, high-bandwidth memory and electronic devices

Abstract

This invention provides a memory access method, a memory controller, a high-bandwidth memory, and an electronic device. Before processing the current command, the memory controller determines whether multiple consecutive commands starting from the current command in the command queue hit the same pseudo-channel. If so, a synchronization signal is activated; the current command is then sent to the high-bandwidth memory. If the current command is a write command, the controller checks whether the synchronization signal is activated. If the synchronization signal is activated, all DQ buses are driven to transmit data to the high-bandwidth memory. If the current command is a read command, the controller checks whether the synchronization signal is activated. If the synchronization signal is activated, all data on the DQ buses is parsed and processed. This invention can fully utilize the DQ bus bandwidth of the high-bandwidth memory.

Description

Technical Field

[0001] This invention relates to the field of memory access technology, and in particular to a memory access method, a memory controller, a high-bandwidth memory, and an electronic device. Background Technology

[0002] Emerging applications such as neural networks require significant computing and memory capabilities to train diverse datasets, making memory bandwidth crucial. This has led to the development of HBM (High Bandwidth Memory), which stacks multiple DDR chips together and packages them with a GPU to achieve a high-capacity, high-bandwidth DDR array.

[0003] HBM achieves higher bus bandwidth performance compared to single-channel operation through a pseudo-channel mechanism. The existing pseudo-channel mechanism divides a 128-bit DQ bus into two 64-bit pseudo-channels. These two pseudo-channels share a command address (CA) bus. This mechanism allows other commands to be sent to pseudo-channel B using the CA bus during the waiting intervals for active pages, read commands, and data transmission / reception in pseudo-channel A. The two 64-bit DQ pseudo-channels transmit data independently, resulting in lower latency and improved memory access performance.

[0004] However, in the existing pseudo-channel working mechanism of HBM, when multiple consecutive commands in the memory controller command queue hit the same pseudo channel, data transmission will only use 64 bits of the 128-bit bus, and the remaining 64 bits of the bus will remain idle, resulting in bandwidth loss. Summary of the Invention

[0005] In view of this, the present invention provides a memory access method, a memory controller, a high-bandwidth memory, and an electronic device.

[0006] In a first aspect, the present invention provides a memory access method applied to a memory controller, the memory access method comprising:

[0007] Before processing the current command, check if multiple consecutive commands starting from the current command in the command queue hit the same pseudo channel. If so, set the synchronization signal.

[0008] Send the current command to high-bandwidth memory. If the current command is a write command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, drive all DQ buses to transmit data to high-bandwidth memory. If the current command is a read command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, parse and process the data on all DQ buses.

[0009] Optionally, the synchronization signal is a level signal, or the synchronization signal is an indicator bit of a register on the memory controller.

[0010] Optionally, the method further includes: after processing the current command, identifying whether the synchronization signal is activated, and releasing the synchronization signal when the synchronization signal is activated.

[0011] In a second aspect, the present invention provides a memory access method, the memory access method comprising:

[0012] Receive the current command sent by the memory controller. If the current command is a write command, identify whether the synchronization signal is set. If the synchronization signal is set, parse and process the data on all DQ buses. If the current command is a read command, identify whether the synchronization signal is set. If the synchronization signal is set, drive all DQ buses to transmit data to the memory controller.

[0013] The synchronization signal mentioned above is controlled by the memory controller and is used to indicate whether all DQ buses are active.

[0014] Optionally, the synchronization signal is a level signal, or the synchronization signal is an indicator bit of a register on the memory controller.

[0015] Thirdly, the present invention provides a memory controller, the memory controller comprising:

[0016] The synchronization module is used to determine whether multiple consecutive commands starting from the current command in the command queue have hit the same pseudo channel before processing the current command. If so, the synchronization signal is activated.

[0017] The command sending module is used to send the current command to high-bandwidth memory;

[0018] The first synchronization drive module is used to identify whether the synchronization signal is set if the current command is a write command, and drive all DQ buses to transmit data to high bandwidth memory after the synchronization signal is set.

[0019] The first synchronization parsing module is used to identify whether the synchronization signal is set if the current command is a read command, and to parse and process all data on the DQ bus when the synchronization signal is set.

[0020] Optionally, the synchronization signal is a level signal, or the synchronization signal is an indicator bit of a register on the memory controller.

[0021] Optionally, the synchronization module is further configured to, after processing the current command, identify whether the synchronization signal has been activated, and release the synchronization signal when the synchronization signal is activated.

[0022] Fourthly, the present invention provides a high-bandwidth memory, the high-bandwidth memory comprising:

[0023] The command receiving module is used to receive the current commands sent by the memory controller;

[0024] The second synchronization drive module is used to identify whether the synchronization signal is set if the current command is a read command, and drive all DQ buses to transmit data to the memory controller after the synchronization signal is set.

[0025] The second synchronization parsing module is used to identify whether the synchronization signal is set if the current command is a write command, and to parse and process all data on the DQ bus when the synchronization signal is set.

[0026] The synchronization signal mentioned above is controlled by the memory controller and is used to indicate whether all DQ buses are active.

[0027] Optionally, the synchronization signal is a level signal, or the synchronization signal is an indicator bit of a register on the memory controller.

[0028] Fifthly, the present invention provides a memory access system, comprising: a memory controller and high-bandwidth memory, wherein the memory controller and the high-bandwidth memory are connected via a CA bus and a DQ bus, wherein the CA bus is used to transmit commands and addresses, and the DQ bus is used to transmit data;

[0029] The memory controller is used to implement the memory access method provided in the first aspect above;

[0030] The high-bandwidth memory is used to implement the memory access method provided in the second aspect above.

[0031] In a sixth aspect, the present invention provides an electronic device comprising the memory access system described above.

[0032] The memory access method provided by this invention uses a synchronization signal to indicate whether all DQ buses of HBM are valid. When multiple consecutive commands in the command queue hit the same pseudo-channel, the synchronization signal is valid and data is transmitted using all DQ buses of HBM. This solves the problem of DQ bus bandwidth loss when multiple consecutive commands in the memory controller command queue hit the same pseudo-channel, making full use of HBM's DQ bus bandwidth and improving the data transmission efficiency of HBM access. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a memory access method provided in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of a memory access method provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of a memory controller provided according to an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of a high-bandwidth memory according to an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of a memory access system provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0041] This invention provides a memory access method applied to a memory controller, such as... Figure 1 As shown, the memory access method includes:

[0042] S101, Before processing the current command, determine whether multiple consecutive commands starting from the current command in the command queue hit the same pseudo channel. If so, set the synchronization signal.

[0043] S102: Send the current command to the high-bandwidth memory. If the current command is a write command, identify whether the synchronization signal is set. If the synchronization signal is set, drive all DQ buses to transmit data to the high-bandwidth memory. If the current command is a read command, identify whether the synchronization signal is set. If the synchronization signal is set, parse and process the data on all DQ buses.

[0044] In this embodiment of the invention, the description focuses on the memory controller accessing the high-bandwidth memory (HBM). Of course, this invention is applicable to any memory with a pseudo-channel operating mode. The synchronization signal is an indicator signal used to indicate whether all DQ buses are active. The synchronization signal is controlled by the memory controller and can be recognized by both the memory controller and the high-bandwidth memory. When the synchronization signal is set, it indicates that all DQ buses are active; when the synchronization signal is released, it indicates that all DQ buses are split into pseudo-channel modes and transmit data independently.

[0045] In one implementation, the synchronization signal can be a low-level signal, indicating that the DQ bus is in pseudo-channel mode, and the two pseudo-channels transmit independently. When multiple consecutive commands in the command queue, starting from the current command, hit the same pseudo-channel, the synchronization signal is activated by changing it to a high level, indicating that synchronous mode has been entered, and the two pseudo-channels transmit data synchronously. Alternatively, the synchronization signal can be implemented using a bit in a register on the memory controller, such as a synchronization indicator bit. The synchronization indicator bit defaults to 0, indicating that the DQ bus is in pseudo-channel mode, and the two pseudo-channels transmit independently. When multiple consecutive commands in the command queue, starting from the current command, hit the same pseudo-channel, the synchronization signal is activated by changing the synchronization indicator bit to 1, indicating that synchronous mode has been entered, and the two pseudo-channels transmit data synchronously.

[0046] Furthermore, the memory access method also includes: after the memory controller finishes processing the current command, it identifies whether the synchronization signal has been set, and when it identifies that the synchronization signal has been set, it releases the synchronization signal.

[0047] It is understandable that releasing the synchronization signal means restoring the synchronization signal to its default state, for example, setting a high-level synchronization signal to a low level, or setting the synchronization indicator in the register to 0.

[0048] To illustrate with a specific example, the memory controller starts processing from the first command in the command queue. Before processing the first command, it first determines whether multiple consecutive commands (two or more) starting from the first command hit the same pseudo-channel. Taking two commands as an example, if the first command hits pseudo-channel A, and the second command also hits pseudo-channel A, then the synchronization signal is activated. Processing the first command begins. If the first command is a write command, it is sent to the high-bandwidth memory, and the synchronization signal is checked for activation. If the synchronization signal is activated, all DQ buses are driven to transfer data to the high-bandwidth memory. If the first command is a read command, it is sent to the high-bandwidth memory, and the synchronization signal is checked for activation. If the synchronization signal is activated, all data on the DQ buses is parsed and processed.

[0049] After processing the first command, the memory controller checks whether the synchronization signal has been set. If the synchronization signal is set, it is released.

[0050] Subsequent commands in the command queue are processed in the same way as the first command mentioned above, and will not be described further.

[0051] After each command is processed, the synchronization signal is released. When processing the next command, the system re-evaluates whether multiple consecutive commands in the command queue have hit the same pseudo-channel, and then determines whether to reactivate the synchronization signal. In this way, the memory controller can accurately switch to the appropriate operating mode when processing each command, improving data transfer efficiency and enhancing the performance of the high-bandwidth memory pseudo-channel.

[0052] On the other hand, embodiments of the present invention provide a memory access method, such as... Figure 2 As shown, the memory access method includes:

[0053] Step S201: Receive the current command sent by the memory controller. If the current command is a write command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, parse and process the data on all DQ buses. If the current command is a read command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, drive all DQ buses to transmit data to the memory controller. The synchronization signal is controlled by the memory controller and is used to indicate whether all DQ buses are valid.

[0054] In one implementation, the synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

[0055] It is easy to understand that the memory access method in this embodiment of the invention is implemented from the HBM side, and can achieve the same technical effect as the memory access method implemented by the memory controller in the aforementioned embodiment.

[0056] On the other hand, embodiments of the present invention provide a memory controller, such as Figure 3 As shown, the memory controller includes:

[0057] Synchronization module 301 is used to determine, before processing the current command, whether multiple consecutive commands starting from the current command in the command queue hit the same pseudo channel. If so, it sets the synchronization signal.

[0058] Command sending module 302 is used to send the current command to high-bandwidth memory;

[0059] The first synchronization drive module 303 is used to identify whether the synchronization signal is set if the current command is a write command. When the synchronization signal is set, it drives all DQ buses to transmit data to the high bandwidth memory.

[0060] The first synchronization parsing module 304 is used to identify whether the synchronization signal is set if the current command is a read command. When the synchronization signal is set, it parses and processes all the data on the DQ bus.

[0061] Furthermore, the synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

[0062] Furthermore, the synchronization module 301 is also used to identify whether the synchronization signal has been activated after processing the current command, and to release the synchronization signal when it is detected that the synchronization signal has been activated.

[0063] The memory controller provided in this embodiment of the invention is used to execute the memory access method embodiment applied to the memory controller described above. The specific process and details can be referred to the above method embodiment, and will not be repeated here.

[0064] On the other hand, embodiments of the present invention provide a high-bandwidth memory, such as... Figure 4 As shown, this high-bandwidth memory includes:

[0065] Command receiving module 401 is used to receive the current command sent by the memory controller;

[0066] The second synchronization drive module 402 is used to identify whether the synchronization signal is set if the current command is a read command. When the synchronization signal is set, it drives all DQ buses to transmit data to the memory controller.

[0067] The second synchronization parsing module 403 is used to identify whether the synchronization signal is set if the current command is a write command. When the synchronization signal is set, it parses and processes all data on the DQ bus.

[0068] The synchronization signal is controlled by the memory controller and is used to indicate whether all DQ buses are active.

[0069] Furthermore, the synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

[0070] The high-bandwidth memory provided in this embodiment of the invention is used to execute the memory access method embodiment on the HBM side described above. Its specific process and details can be found in the above method embodiment, and will not be repeated here.

[0071] On the other hand, embodiments of the present invention provide a memory access system, such as Figure 5 As shown, the system includes a memory controller and a high-bandwidth memory (HBM). The memory controller and the HBM are connected via a CA bus and a DQ bus. The CA bus is used to transmit commands and addresses, and the DQ bus is used to transmit data. The memory controller implements a memory access method, specifically including: before processing the current command, determining whether multiple consecutive commands starting from the current command in the command queue have hit the same pseudo-channel; if so, activating a synchronization signal, which indicates whether all DQ buses are valid; sending the current command to the HBM; if the current command is a write command, identifying whether the synchronization signal is activated; and driving all DQ buses to transmit data to the HBM after the synchronization signal is activated; if the current command is a read command, identifying whether the synchronization signal is activated; and parsing and processing the data on all DQ buses after the synchronization signal is activated. High-bandwidth memory is used to implement a memory access method, specifically including: receiving the current command sent by the memory controller; if the current command is a write command, identifying whether the synchronization signal is set; if the synchronization signal is set, parsing and processing the data on all DQ buses; if the current command is a read command, identifying whether the synchronization signal is set; if the synchronization signal is set, driving all DQ buses to transmit data to the memory controller; wherein the synchronization signal is controlled by the memory controller and is used to indicate whether all DQ buses are valid.

[0072] On the other hand, embodiments of the present invention provide an electronic device, such as... Figure 6 As shown, the system includes a processor and the memory access system of the above embodiments. The processor can send commands to the memory controller, and the memory controller and high-bandwidth memory execute the memory access method provided in the embodiments of this application.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A memory access method, characterized in that, Applied to a memory controller, the memory access method includes: Before processing the current command, check if multiple consecutive commands starting from the current command in the command queue hit the same pseudo channel. If so, set the synchronization signal. Send the current command to high-bandwidth memory. If the current command is a write command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, drive all DQ buses to transmit data to high-bandwidth memory. If the current command is a read command, identify whether the synchronization signal is enabled. If the synchronization signal is enabled, parse and process the data on all DQ buses.

2. The memory access method according to claim 1, characterized in that, The synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

3. The memory access method according to claim 1, characterized in that, The method further includes: after processing the current command, identifying whether the synchronization signal is activated, and releasing the synchronization signal after identifying that the synchronization signal is activated.

4. A memory access method, characterized in that, The memory access method includes: Receive the current command sent by the memory controller. If the current command is a write command, identify whether the synchronization signal is set. If the synchronization signal is set, parse and process the data on all DQ buses. If the current command is a read command, identify whether the synchronization signal is set. If the synchronization signal is set, drive all DQ buses to transmit data to the memory controller. The synchronization signal is controlled by the memory controller and is used to indicate whether all DQ buses are valid. If the memory controller determines that multiple consecutive commands in the command queue, starting from the current command, hit the same pseudo channel, the synchronization signal is activated. When the synchronization signal is activated, all DQ buses are valid.

5. The memory access method according to claim 4, characterized in that, The synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

6. A memory controller, characterized in that, The memory controller includes: The synchronization module is used to determine whether multiple consecutive commands starting from the current command in the command queue have hit the same pseudo channel before processing the current command. If so, the synchronization signal is activated. The command sending module is used to send the current command to high-bandwidth memory; The first synchronization drive module is used to identify whether the synchronization signal is set if the current command is a write command, and drive all DQ buses to transmit data to high bandwidth memory after the synchronization signal is set. The first synchronization parsing module is used to identify whether the synchronization signal is set if the current command is a read command, and to parse and process all data on the DQ bus when the synchronization signal is set.

7. The memory controller according to claim 6, characterized in that, The synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

8. The memory controller according to claim 6, characterized in that, The synchronization module is also used to identify whether the synchronization signal has been activated after processing the current command, and to release the synchronization signal when the synchronization signal is activated.

9. A high-bandwidth memory, characterized in that, The high-bandwidth memory includes: The command receiving module is used to receive the current commands sent by the memory controller; The second synchronization drive module is used to identify whether the synchronization signal is set if the current command is a read command, and drive all DQ buses to transmit data to the memory controller after the synchronization signal is set. The second synchronization parsing module is used to identify whether the synchronization signal is set if the current command is a write command, and to parse and process all data on the DQ bus when the synchronization signal is set. The synchronization signal is controlled by the memory controller and is used to indicate whether all DQ buses are valid. If the memory controller determines that multiple consecutive commands in the command queue, starting from the current command, hit the same pseudo channel, the synchronization signal is activated. When the synchronization signal is activated, all DQ buses are valid.

10. The high-bandwidth memory according to claim 9, characterized in that, The synchronization signal is a level signal, or the synchronization signal is an indicator bit in a register on the memory controller.

11. A memory access system, characterized in that, include: A memory controller and high-bandwidth memory are connected via a CA bus and a DQ bus, wherein the CA bus is used to transmit commands and addresses, and the DQ bus is used to transmit data; The memory controller is used to implement the memory access method as described in any one of claims 1-3; The high-bandwidth memory is used to implement the memory access method as described in claim 4 or 5.

12. An electronic device, characterized in that, The electronic device includes the memory access system as described in claim 11.

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