Data reading method and related apparatus

Abstract

Embodiments of the present application provide a data reading method and related device, which are suitable for read data access of AXI bus protocol, and include: obtaining a first reading request satisfying the AXI bus protocol, wherein the first reading request includes a data address of data to be read and data transmission control information; when it is determined that the data address is a non-aligned address, adjusting the data address and the data transmission control information to obtain a second reading request requesting data of the non-aligned address and data of a next address of the non-aligned address, and the data address of the second reading request is an aligned address; and sending the second reading request. The data reading method and related device provided by the embodiments of the present application can solve the problem of non-adaptation of read access of non-aligned address in read data access of the AXI bus protocol.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data reading method and related apparatus. Background Technology

[0002] As the complexity of system-on-chip (SoC) design increases and processor capabilities improve, bus architecture becomes increasingly important to the performance requirements of the system. Among them, the AXI (Advanced eXtensible Interface) bus protocol, with its high performance, high bandwidth, and low latency, can meet the needs of ultra-high performance and complex SoC designs and has been widely adopted.

[0003] In the AXI bus protocol, read address, write address, read data, write data, and handshake signals are sent in different channels. The AXI bus can optimize each channel individually, control the timing channel as needed, maximize the clock frequency, minimize latency, and support unaligned data transmission, meaning that the address of the first byte of data access can be misaligned with the address boundary.

[0004] However, in unaligned read access, since the AXI bus protocol does not provide detailed specifications, there are two possible interpretations of the unaligned read data returned by the AXI bus protocol. Different third-party IPs and processors may have different interpretations of the AXI bus protocol, which may lead to incompatibility, data loss, and serious software errors.

[0005] Therefore, how to solve the incompatibility problem of unaligned read access in the AXI bus protocol has become an urgent technical problem to be solved. Summary of the Invention

[0006] The technical problem addressed by the embodiments of this application is how to improve the adaptability of non-aligned read access in the AXI bus protocol.

[0007] To address the aforementioned problems, embodiments of this application provide a data reading method and related apparatus, including:

[0008] In a first aspect, embodiments of this application provide a data reading method applicable to read data access using the AXI bus protocol, including:

[0009] Obtain a first read request that conforms to the AXI bus protocol, wherein the first read request includes the data address of the data to be read and data transmission control information;

[0010] When the data address is determined to be an unaligned address, the data address and the data transmission control information are adjusted to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address, and the data address of the second read request is an aligned address;

[0011] Send the second read request.

[0012] Secondly, embodiments of this application also provide a data reading device, the device comprising:

[0013] The acquisition module is adapted to acquire a first read request that conforms to the AXI bus protocol, wherein the first read request includes the data address of the data to be read and data transmission control information;

[0014] The adjustment module is adapted to adjust the data address and the data transmission control information when it is determined that the data address is an unaligned address, so as to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address, wherein the data address of the second read request is an aligned address;

[0015] The sending module is adapted to send the second read request.

[0016] Thirdly, embodiments of this application also provide a storage medium storing a program suitable for data reading to implement the data reading method as described in any of the first aspects.

[0017] Fourthly, embodiments of this application also provide an electronic device, including at least one memory and at least one processor; the memory stores a program, and the processor invokes the program to perform the data reading method as described in any of the first aspects.

[0018] Compared with the prior art, the technical solution of this application has the following advantages:

[0019] The data reading method provided in this application embodiment determines whether the data address of the first read request satisfying the AXI bus protocol is an unaligned data address that would cause a read error during AXI bus protocol processing by judging its data address. The first read request containing the unaligned address is then converted into a second read request containing an aligned address that will not cause a read error during AXI bus protocol processing. The second read request requests at least the data at the unaligned address and the data at the address immediately following the unaligned address. Thus, by adjusting the unaligned data address to an aligned data address in the second read request, when returning data based on the second read request, both the data at the unaligned address and the data at the address immediately following the unaligned address can be returned, ensuring that even if the data address in the first read request satisfying the AXI bus protocol is an unaligned address, the requesting end can still obtain the required data. As can be seen, the data reading method provided in this application embodiment can simultaneously satisfy the needs of both the requesting sender and the requesting receiver, even if the requesting sender and the requesting receiver have different understandings of the first read request for the unaligned address that meets the AXI bus protocol. This allows the requesting sender to read the required data, thereby improving the compatibility between the requesting sender and the requesting receiver when using the AXI bus protocol for data transmission and solving the incompatibility problem of unaligned read access in the AXI bus protocol. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an architecture for reading data access in the AXI bus protocol;

[0022] Figure 2 This is a schematic diagram of the AXI bus protocol for unaligned write data access;

[0023] Figure 3 This is a schematic diagram illustrating the processing result of non-aligned read data access in the AXI bus protocol;

[0024] Figure 4 This is a flowchart illustrating the data reading method provided in an embodiment of this application;

[0025] Figure 5 This is another flowchart illustrating the data reading method provided in this application embodiment;

[0026] Figure 6 This is a schematic diagram illustrating an implementation result of the data reading method provided in an embodiment of this application;

[0027] Figure 7 This is an optional structural block diagram of the data reading device provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The AXI bus has five independent transmission channels to handle data read and write requests. According to the AXI bus protocol, the AXI bus supports unaligned data transmission, which means that the address of the first byte of data accessed after AXI bus conversion can be misaligned with the address boundary of the transmission channel.

[0030] To make it easier to understand unaligned addresses, the following example is provided:

[0031] For example, the address boundaries corresponding to a 32-bit wide transmission channel are 0x00, 0x04, 0x08, etc. However, after a 32-bit wide data is converted by the AXI bus, the address of the first byte accessed by the data starts from the address 0x01 of the transmission channel. The address 0x01 is not the aforementioned address boundary. Therefore, the address 0x01 is not aligned with the 32-bit wide address boundary and is an unaligned address.

[0032] To facilitate understanding of data read / write processing in the AXI bus protocol, this application uses read data access in the AXI bus protocol as an example for illustration. Please refer to [link / reference needed]. Figure 1 , Figure 1 This is a schematic diagram of an architecture for reading data access in the AXI bus protocol.

[0033] As shown in the figure, when the AXI bus protocol processes read data access, the master interface 102 sends a first read request that satisfies the AXI bus protocol. The AXI bus transmits the address information and control information 104 corresponding to the read data address of the first read request to the slave interface 103 through the read address channel 100. After receiving the address information and control information 104, the slave interface 103 obtains the data corresponding to the address information and control information 104 and returns the corresponding read data 105 to the master interface 102 through the read data channel 101 of the AXI bus. This completes one read data access under the AXI bus protocol.

[0034] As can be seen, the read address channel 100 and read data channel 101 of the AXI bus are separate; at the same time, in burst-based transmission, the address information and control information 104 of the read address channel 100 represent the information of the starting access address of the read data after being converted by the AXI bus and the information of the byte path used to transmit the data. In this way, when the other end connected to the AXI bus receives the data request information, it can obtain the actual data required for the data request based on the starting address in the address information and the subsequent data address information included in the control information.

[0035] Burst transmission typically refers to transmission between two devices, such as... Figure 1 The mode shown is a data transfer between the master device 102 and the slave device 103, which can also be called data transfer in burst mode. The byte path is a byte used to transfer data on the data bus. One byte path is 8 bits wide. The aforementioned AXI bus protocol supports unaligned data transfer by using byte path gating.

[0036] Based on the above, further explanation of the implementation of unaligned data transmission is provided below. Please refer to [link / reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the AXI bus protocol for unaligned write data access.

[0037] As shown in the figure, the width of the write data 201 to be transmitted is 32 bits, and the length of a single burst transmission is 5 ( Figure 2As shown in steps 1-5, the starting write address 202 corresponding to the write data converted by the AXI bus protocol is 0x01, not address 0x00. Therefore, the transmission of this 32-bit wide write data is unaligned address data transmission. Thus, the master device will write 19 bytes of data starting from address 0x01, where each write address includes 8 bits, i.e., one byte. Figure 2 In the unaligned transmission shown, data is written starting from address 0x01, and it takes 5 clock cycles to write a total of 3 (bytes) + 4 (clock cycles) * 4 (bytes), which is 19 bytes of data, instead of 20 bytes (the bytes written starting from address 0x00).

[0038] exist Figure 2 When writing data, since it is written sequentially, there will be no data writing errors, and when storing data from device 103, no incorrect written data will be stored.

[0039] However, in the AXI bus protocol, there is a different interpretation of unaligned read data access:

[0040] For example, when the read address channel transmits a read data request as shown below:

[0041] ARSIZE = 0x1 (data transfer width, used to calculate the number of bytes that can be transferred in one clock cycle), ARADDR = 0x1 (unaligned transfer).

[0042] ARLEN = 0x0 (burst length is 1)

[0043] When device 103 retrieves data from the unaligned address converted by the AXI bus protocol and returns read data 105 to master device 102, there are two possible interpretations of the returned read data 105:

[0044] (1) Understanding 1: Reading the 1 byte of data corresponding to address 0x1 is considered valid;

[0045] (2) Understanding 2: The 2 bytes of data corresponding to addresses 0x1 and 0x2 are considered valid.

[0046] Thus, when reading the returned read data 105, different understandings of the AXI bus protocol may lead to incompatibility.

[0047] Below, we will use the A5 processor as an example. Figure 1 The main device 102, with bus IP Nic400 as... Figure 1 Taking device 103 as an example, we will introduce unaligned transmission.

[0048] The Nic400 bus IP is an interconnect IP from ARM that can be automatically generated using EDA tools such as AMBADesigner or ARM Socrates, based on user-defined requirements.

[0049] For the non-aligned read access of the AXI bus IP nic400, the first interpretation mentioned above applies: only the 1 byte of read data 105 corresponding to 0x01 is considered valid, and the remaining bytes of read data 105 are masked to 0 before the data is returned to the master device 102. Figure 1 When reading data 105 is returned through reading data channel 101, only the reading data 105 corresponding to the reading address 0x01 is valid.

[0050] The ARM Cortex A5 processor is a processor based on the ARM V7-A architecture, which supports unaligned transfers when accessing normal, non-cacheable memory space.

[0051] In practical use, the A5 processor interprets the unaligned read access of the AXI bus protocol as the second one mentioned above, that is, the 2 bytes of read data corresponding to 0x01 and 0x02 are considered valid.

[0052] Thus, when the A5 processor and the bus IP nic400 are used together to obtain read data from an unaligned address, the read data returned by the bus IP nic400 will not be the read data required by the A5 processor and will not meet the needs of the A5 processor.

[0053] To facilitate understanding, let's continue with... Figure 2 and Figure 3 To explain, Figure 3 This is a schematic diagram illustrating the processing result of non-aligned read data access in the AXI bus protocol.

[0054] As shown in the figure, where:

[0055] The read request address is represented as: the read address corresponding to the read request obtained by the A5 processor.

[0056] The AXI bus behavior is represented as: the first read request issued by the A5 processor, which is converted to meet the AXI bus protocol.

[0057] As can be seen, the first read request that satisfies the AXI bus protocol includes:

[0058] The starting address for reading data is araddr, for example: 0x1;

[0059] Data transfer width arsize, for example: 0x1;

[0060] Data transmission length arlen, for example: 0x0.

[0061] The meaning of the information after AXI bus behavior conversion is as follows:

[0062] Starting from the initial access address 0x1, only one data cycle is transmitted based on the data transmission length 0x0, and the number of data bytes transmitted in each cycle is 2^arsize.

[0063] One shot can be Figure 2 In a given timeframe, the selectable byte path on the transmission channel of that timeframe is determined based on the data transmission width arsize. This determines which bytes can transmit data on the transmission channel of that timeframe. For example, ... Figure 2 As shown, a byte path includes 8 bits in width, such as Figure 2 In the diagram, [7:0], [8:15], [16:23], and [24:31] each represent a byte path. The specific formula for calculating the selectable byte path is: 2^arsize, which is 2 1 It is a 2-byte path.

[0064] In summary, Figure 3 The read data information obtained from the first AXI bus action (sequence number 0) is as follows:

[0065] Based on the A5 processor's understanding of unaligned data transmission in the AXI bus protocol, starting from the initial access address 0x1, the data of two optional byte paths of the one-time transmittable channel is read, namely the read data contained in address 0x1 corresponding to byte path [15:8] and address 0x2 corresponding to byte path [23:16].

[0066] However, based on the understanding of unaligned data transmission in the AXI bus protocol by the bus IP nic400, the returned read data includes read data from the valid 0x1 address and read data from other addresses that have been masked.

[0067] As can be seen, the valid read data returned by the bus IP nic400 at address 0x1 does not match the read data required by the A5 processor at addresses 0x1 and 0x2, resulting in a data read error.

[0068] Therefore, when the A5 processor and the bus IP nic400 are used together, a mismatch in the transmitted read data will occur, resulting in incompatibility between the A5 processor and the bus IP nic400, causing data loss and serious errors in the software program.

[0069] To address the device incompatibility issues caused by differing understandings of non-aligned read access in the AXI bus protocol, this application provides a data reading method. Please refer to... Figure 4 , Figure 4 This is a flowchart illustrating the data reading method provided in an embodiment of this application.

[0070] like Figure 4 As shown, the process may include the following steps:

[0071] Step S10: Obtain a first read request that satisfies the AXI bus protocol. The first read request includes the data address of the data to be read and data transmission control information.

[0072] As can be seen from the foregoing, the master device connected to the AXI bus will issue a first read request that conforms to the AXI bus protocol. The data reading method provided in this application embodiment first obtains the first read request that conforms to the AXI bus protocol.

[0073] The first read request that satisfies the AXI bus protocol contains the data address as the starting access address corresponding to the read data, and the data transmission control information is the specific information of the data to be transmitted, such as how many bytes the data is transmitted through each clock cycle.

[0074] It should be noted that the first read request that satisfies the AXI bus protocol as described in this document refers to an access request for data transmission using the AXI bus protocol (including read requests and write requests; this application refers to a non-aligned address read request under the AXI bus protocol, which is the first read request), while data transmission operations performed under non-AXI bus protocols are not within the scope of this application.

[0075] In one specific implementation, the data transmission control information may include the number of data bytes per clock cycle, where the number of data bytes per clock cycle represents the maximum number of data bytes that can be transmitted in each data transmission cycle, i.e. Figure 2 The maximum number of data bytes that can be transmitted in each clock cycle (i.e., the number of selectable byte paths) can also be understood as the number of read addresses that can be transmitted starting from the starting address of the read data.

[0076] As can be seen from the foregoing, due to different understandings of the non-aligned read data access of the AXI bus protocol, incompatibility occurs between the two devices connected to the AXI bus, resulting in data loss and serious errors in the software program.

[0077] Therefore, the data reading method provided in this application embodiment can first determine the data address included in the first read request after obtaining the first read request that satisfies the AXI bus protocol.

[0078] Specifically, this may include the following steps:

[0079] Step S11: Determine whether the data address is an unaligned address. If yes, proceed to step S13; otherwise, proceed to step S12.

[0080] As described above, a mismatch only occurs when the data address is an unaligned address. Therefore, after receiving the first read request, it is first determined whether the data address in the first read request is an unaligned address.

[0081] Of course, based on the description of unaligned addresses, it can be determined using data addresses and data transmission control information.

[0082] When the data address is an aligned read data address (i.e., when step S11 is determined to be no), step S12 can be executed directly to send the first read request and return the read data required by the sender of the first read request. When the data address is a non-aligned read data address, the returned read data may not match the read data required by the sender. The non-aligned read data address can be adjusted according to the data reading method provided in the embodiments of this application to obtain an aligned read data address that will not cause misunderstanding.

[0083] Specifically, the data transmission control information may include the number of data bytes per frame, which represents the maximum number of read data bytes that can be transmitted in one frame. Of course, the number of data bytes per frame can be directly included in the data transmission control information or indirectly included in the data transmission control information.

[0084] Based on the current AXI bus protocol, the data transmission control information directly includes the data transmission width. The data transmission width represents the number of data bytes per clock cycle. That is, the number of data bytes per clock cycle can include the data transmission width ARSIZE. The number of data bytes per clock cycle is obtained based on the data transmission width, which can be specifically obtained using the following formula:

[0085] Number of data bytes per shot = 2^ARSIZE.

[0086] Of course, whether the data transmission control information directly includes the number of data bytes per frame or indirectly includes the number of data bytes per frame, it all falls under the category of "data transmission control information including the number of data bytes per frame" as described in this article.

[0087] Specifically, the step of determining whether the data address is an unaligned address may include:

[0088] Determine whether the data address is divisible by the number of data bytes per beat. If the data address is divisible by the number of data bytes per beat, it is considered an aligned data address. If the data address is not divisible by the number of data bytes per beat, it is considered an unaligned data address.

[0089] When the number of data bytes per clock cycle is not divisible by the data address, it is determined to be an unaligned read data address in the AXI bus protocol, for example... Figure 3 The data addresses shown that satisfy the AXI bus protocol are 0x1 and 0x5. The number of data bytes per clock cycle is 2^1 = 2, which is not divisible. Therefore, they are unaligned addresses in the AXI bus protocol. At this time, the unaligned address conversion step of the data reading method provided in this application embodiment, namely step S13, is used to convert the unaligned address read data transmission into an aligned address read data transmission, and then the converted aligned read data address is executed.

[0090] Specifically, the formula for determining that the data address of the first read request is an unaligned address can be expressed as:

[0091] ARADDR%(2^ARSIZE)! = 0,

[0092] Where ARADDR represents the data address, ARSIZE represents the data transmission width of the data transmission control information, 2^ARSIZE represents the number of data bytes per frame, and % represents the remainder.

[0093] The above-mentioned judgment formula means that when the data address cannot be divided evenly by the data transmission width, it is an unaligned address; when it is divisible, the data address is an aligned address. For example, when the data addresses satisfying the AXI bus protocol are 0x1 and 0x5, the number of data bytes per clock cycle is 2^1 = 2, which is not divisible, therefore it is an unaligned address in the AXI bus protocol. Of course, in some embodiments, it is possible to determine whether the data address is unaligned as needed. Therefore, the execution of the data reading method provided in this application embodiment can be controlled by obtaining an enable signal for determining whether the data address is unaligned, in order to execute the data address adjustment step of the first read request.

[0094] This allows for flexibility in program execution. When the data read method provided in this embodiment needs to be executed, the enable signal controls the program to enter the data read method provided in this embodiment for unaligned address translation. When unaligned address translation is not required, the program is executed according to the original AXI bus protocol program flow sequence, reducing unnecessary program conversion power consumption.

[0095] Step S12: Send the first read request.

[0096] If the data address is not an unaligned address, then you can directly send the first read request.

[0097] Step S13: Adjust the data address and the data transmission control information to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address, wherein the data address of the second read request is an aligned address.

[0098] When the data address is determined to be an unaligned address, step S13 is executed to adjust the first read request so that the data address of the adjusted second read request is an aligned address. The requested data must include the data at the unaligned address before adjustment, as well as the data at the address following the unaligned address. Thus, based on the second read request, the correct data required by the requesting end can be returned.

[0099] In one specific implementation, for ease of adjusting the first read request, please refer to... Figure 5 , Figure 5 This is another flowchart illustrating the data reading method provided in an embodiment of this application.

[0100] like Figure 5 As shown, the data reading method provided in this application embodiment, specifically adjusting the first read request, may include the following steps:

[0101] Step S13: Adjust the data address and data transmission control information of the first read request to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address, wherein the data address of the second read request is an aligned address. Specifically, this may include the following steps:

[0102] Step S130: Adjust the data address to the aligned address that is located before the unaligned address and is closest to the unaligned address.

[0103] To ensure that the second read request can ultimately obtain the read data corresponding to the unaligned address, the data address can only be adjusted forward when adjusting the data address. Furthermore, to reduce the amount of adjustment and the amount of unnecessary data transmitted, and to avoid excessive power consumption, the data address can be adjusted to the aligned address that is before the unaligned address and is closest to the unaligned address.

[0104] For example, when the unaligned address is 0x01, it can be adjusted to 0x00.

[0105] Step S131: Adjust the number of data bytes per frame to increase by at least 2 times once to obtain the second read request.

[0106] If only the data address is adjusted to an aligned address, but the original number of data bytes per frame is maintained, the final data obtained will definitely not meet the requirements. In order to ensure that the obtained data includes the data at the non-aligned address and the data at the address following the non-aligned address, it is also necessary to adjust the number of bytes transmitted per frame. The number of data bytes per frame should be increased by at least 2 times, specifically by 2 times or 4 times.

[0107] As mentioned earlier, if the number of data bytes per beat is directly expressed, then the number of data bytes per beat can be directly increased.

[0108] Based on the existing AXI bus protocol, the number of data bytes per frame is expressed by the data transmission width ARSIZE. Therefore, the step of adjusting the number of data bytes per frame by at least twice once includes:

[0109] By adjusting the data transmission width by at least one at a time, the number of data bytes per frame is increased by at least twice at a time.

[0110] For example, if ARSIZE is 1 before adjustment and ARSIZE is 2 after adjustment, then the number of data bytes per frame before adjustment is 2^1 = 2, and the number of data bytes per frame after adjustment is 2^2 = 4.

[0111] Of course, it's easy to understand that the maximum number of data bytes per frame after adjustment is equal to the data width.

[0112] In the AXI bus protocol, the data transmission width is a variable. The number of data bytes per clock cycle can be adjusted by changing the data transmission width, thereby increasing the number of data bytes that can be transmitted per clock cycle. This allows the third-party IP to increase the effective read data per clock cycle when interpreting the second read request obtained by the data reading method provided in this application within the AXI bus protocol. In this way, read data corresponding to other addresses that are transmitted during non-aligned read access due to insufficient data bytes per clock cycle will not be invalidated.

[0113] In one specific implementation, to facilitate the adjustment of the data address, the step of adjusting the data address to the aligned address that is located before the unaligned address and is closest to the unaligned address may include: setting the lower two bits of the data address to 0.

[0114] In this way, it is very simple and convenient to adjust unaligned addresses to aligned addresses.

[0115] Continuing with the above formula for determining unaligned addresses, the corresponding steps for adjusting unaligned addresses can be expressed as follows:

[0116] (1) ARADDR_new = ARADDR;

[0117] (2)ARADDR_new[ARSIZE:0]=0;

[0118] (3) ARSIZE_new = ARSIZE + 1.

[0119] Step (1) means assigning the data address ARADDR of the first read request, which is determined to be an unaligned address, to the new address ARADDR_new;

[0120] Step (2) means that the lower bits of the new data address ARADDR_new are set to 0, so that the new data address ARADDR_new is an aligned address (an address that can be divided by 2^ARSIZE). This means that the above "the step of adjusting the data address to the aligned address that is before the unaligned address and closest to the unaligned address: adjusting the lower two bits of the data address to 0" is described above.

[0121] Step (3) means expanding the optional byte path used for data transmission (corresponding to step S131 above). According to the principle of minimum modification, the original ARSIZE value can be increased by 1 to obtain ARSIZE_new, and the number of data bytes per shot is doubled accordingly.

[0122] This achieves the adjustment of unaligned data addresses to aligned data addresses, preventing data return errors during data reading and improving the adaptability of the AXI bus protocol to unaligned read access.

[0123] To facilitate understanding of the implementation structure of the data reading method provided in the embodiments of this application, please refer to... Figure 3 refer to Figure 6 , Figure 6 This is a schematic diagram illustrating an implementation result of the data reading method provided in the embodiments of this application.

[0124] Figure 3 The read request information after AXI bus behavior conversion shown is the first read request that satisfies the AXI bus protocol. Figure 6 The results shown are for Figure 3 The first read request is compared with the data reading method provided in the embodiments of this application.

[0125] according to Figure 3 The results shown indicate that the AXI bus sends a first read request to the A5 processor that satisfies the AXI bus protocol:

[0126] (1) Only when the A5 processor issues a half-word read request (a half-word is equal to 2 bytes, that is, the number of data bytes per clock cycle is 2 bytes or arsize = 0x1), and the address offset, that is, the starting access address, is 0x1, 0x5 (that is, the address after conversion by the AXI bus protocol is an unaligned address read request), after the bus IP nic400 processes the read request converted by the AXI bus and returns the corresponding read data, some read data will be shielded by the bus IP nic400, and only 1 byte of read data will be returned, resulting in read data loss and an error.

[0127] Of course, experiments have shown that when the read request address is 0x9, 0xd, 0x11, 0x15, 0x19, 0x1d, the address after conversion by the AXI bus protocol is also an unaligned address. If the number of data bytes per clock cycle is also 2 bytes, then it will also lead to data loss and errors.

[0128] (2) No error will occur in the following situations:

[0129] 1) The A5 processor sends an unaligned half-word read with a read start address of 0x3, 0x7, 0xb, 0xf, 0x13, 0x17, 0x1b, 0x1f. After the address is converted by the AXI bus behavior translation, it will be automatically converted into an aligned address and sent to the other end connected to the AXI bus. Among them, 0xb, 0xf, 0x13, 0x17, 0x1b are not shown in the figure.

[0130] 2) When the A5 processor sends an unaligned read full word (one full word equals 4 bytes), the read start address after conversion by the AXI bus is an aligned address;

[0131] 3) When the A5 processor sends an unaligned read double word (one double word equals 8 bytes), the read start address will not have an alignment problem after the AXI bus behavior conversion.

[0132] Therefore, regarding the handling of unaligned address translation in the A5 processor, the specific processing procedure of the data reading method provided in this application embodiment is as follows:

[0133] like Figure 6 As shown, for Figure 3 The first read request, with sequence number 0 and read request address 0x1, is represented by the following after AXI bus conversion: read address araddr = 0x0, data transfer width arsize = 0x2, data transfer length arlen = 0x0.

[0134] Specifically, according to the data reading method provided in the embodiments of this application, for Figure 3The read data request with sequence number 0 (i.e., the first one) shown is converted as follows:

[0135] First, adjust Figure 3 Under the Nakahara AXI bus behavior, the read start address is: the lower two bits of arcadr = 0x1 are set to 0, resulting in... Figure 6 The starting read address under the AXI bus behavior shown is: artadr = 0x0, which can adjust the original unaligned read data address to an aligned read data address.

[0136] Then, the original data transmission width Figure 3 arsize = 0x1 plus one, adjust to Figure 6 The arsize shown is 0x2.

[0137] Since the number of data bytes per frame = 2^data transmission width, therefore, when the data transmission width is Figure 6 When the value is 0x2, the number of data bytes per clock cycle is 2. 2 That is, 4 bytes.

[0138] Step S14: Send the second read request.

[0139] After adjustments, a revised second read request is issued.

[0140] At this point, the data required by the requesting end can be obtained. It is easy to understand that the second read request includes the adjusted and aligned starting access data address and the expanded data transmission control information.

[0141] Based on the aforementioned case, it can be seen that this expands the number of selectable byte paths in the first-phase transmittable data channel. When IP nic400 receives a read data request with a converted aligned address, the returned read data includes data from 0x0 to 0x3, which can include the data corresponding to addresses 0x1 and 0x2 that the A5 processor originally needed, without masking it out. In this way, the read data returned from IP nic400 is the read data that meets the needs of the A5 processor. The data sent and returned by the A5 processor and IP nic400 connected to the AXI bus can be matched, solving the incompatibility problem of non-aligned access in the AXI bus protocol.

[0142] Thus, the data reading method provided in this application embodiment determines whether the data address of the first read request satisfying the AXI bus protocol is an unaligned data address that would cause a read error in AXI bus protocol processing by judging the data address. The first read request containing the unaligned address is then converted into a second read request containing an aligned address that will not cause a read error in AXI bus protocol processing. The second read request requests at least the data at the unaligned address and the data at the address immediately following the unaligned address. By adjusting the unaligned data address to an aligned data address in the second read request, when returning data based on the second read request, both the data at the unaligned address and the data at the address immediately following the unaligned address can be returned, ensuring that even if the data address in the first read request satisfying the AXI bus protocol is an unaligned address, the requesting end can still obtain the required data.

[0143] As can be seen, the data reading method provided in this application embodiment can simultaneously satisfy the needs of both the requesting sender and the requesting receiver, even if the requesting sender and the requesting receiver have different understandings of the first read request for the unaligned address that meets the AXI bus protocol. This allows the requesting sender to read the required data, thereby improving the compatibility between the requesting sender and the requesting receiver when using the AXI bus protocol for data transmission and solving the incompatibility problem of unaligned read access in the AXI bus protocol.

[0144] To address the aforementioned problems, this application also provides a data transmission and reading device, which can be considered as a functional module required to implement the data reading method provided in this application. The device described below can be referred to in correspondence with the method described above.

[0145] As an optional implementation, Figure 7 An optional structural block diagram of the data reading device provided in an embodiment of this application is shown.

[0146] like Figure 7 As shown, the data reading device may include:

[0147] The acquisition module 70 is adapted to acquire a first read request that meets the AXI bus protocol, wherein the first read request includes the data address of the data to be read and data transmission control information;

[0148] The adjustment module 73 is adapted to adjust the data address and the data transmission control information when it is determined that the data address is an unaligned address, so as to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address, and the data address of the second read request is an aligned address;

[0149] Sending module 74 is adapted to send the second read request.

[0150] Thus, the data reading device provided in this application embodiment first determines whether the data address of the acquired first read request is an aligned address, and then adjusts the unaligned data address to convert it into an aligned address, so that it can adapt to two devices with different understandings of unalignment in the AXI bus protocol, thereby obtaining the correct read data.

[0151] In one specific embodiment, the data transmission control information acquired by the acquisition module 70 includes the number of data bytes per clock cycle. The adjustment module 73 is adapted to adjust the data address of the first read request and the data transmission control information to obtain a second read request that requests at least the data at the unaligned address and the data at the address following the unaligned address. The data address of the second read request is an aligned address, including:

[0152] The data address is adjusted to the aligned address that is before the unaligned address and closest to the unaligned address, and the number of data bytes per frame is increased by at least 2 times once to obtain the second read request.

[0153] In another specific implementation, the number of data bytes per frame is determined based on the data transmission width;

[0154] For example, when the data transmission width is 0x1, the number of data bytes per frame is 2^1, which is 2 bytes.

[0155] At this time, the adjustment module 73 is also adapted to:

[0156] By adjusting the data transmission width by at least one time, the number of data bytes per frame is increased by at least two times.

[0157] The adjustment module 73 is executed based on the determination result of the unaligned address determination module 72. The unaligned address determination module is adapted to determine that the data address is an unaligned address, including:

[0158] When the data address cannot be divided by the number of data bytes per beat, the data address is determined to be an unaligned address.

[0159] In some specific embodiments, the execution of the unaligned address determination module 72 can be implemented by the enable signal acquisition module 71, which is adapted to acquire the enable signal for determining whether the data address is an unaligned address.

[0160] In order to enable the conversion of unaligned read addresses to aligned read addresses, in one specific embodiment, the adjustment module 73 is adapted to adjust the data address to an aligned address that is located before the unaligned address and is closest to the unaligned address, including:

[0161] Adjust the lower two bits of the data address and assign them a value of 0.

[0162] This application embodiment also provides a storage medium storing a program suitable for data analysis to implement the data reading method as described above.

[0163] This application also provides an electronic device, including at least one memory and at least one processor; the memory stores a program, and the processor calls the program to execute the data reading method as described above.

[0164] The storage medium and electronic device provided in this application embodiment can execute the data reading method provided in this application embodiment, so that even if the requesting end and the requesting end have different understandings of the first read request for the unaligned address that meets the AXI bus protocol, the second read request obtained after adjustment can simultaneously meet the needs of the requesting end and the requesting end, and ultimately enable the requesting end to read the data that meets the requirements, thereby improving the compatibility between the requesting end and the requesting end for data transmission using the AXI bus protocol, and solving the incompatibility problem of unaligned read access in the AXI bus protocol.

[0165] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A data reading method, characterized in that, Read data access applicable to the AXI bus protocol includes: Obtain a first read request that satisfies the AXI bus protocol. The first read request includes the data address of the data to be read and data transmission control information. The data transmission control information includes the number of data bytes per cycle, which represents the maximum number of read data bytes transmitted in one cycle. When the data address is determined to be an unaligned address, the data address of the first read request and the data transmission control information are adjusted to obtain a second read request; the data address of the second read request is an aligned address, and is used at least to request the data at the unaligned address and the data at the address following the unaligned address; wherein, adjusting the data address of the first read request and the data transmission control information includes: adjusting the data address of the first read request to the aligned address located before the unaligned address and closest to the unaligned address; and increasing the number of data bytes per frame in the data transmission control information by at least 2 times once; Send the second read request.

2. The data reading method as described in claim 1, characterized in that, The step of determining that the data address is an unaligned address includes: When the data address cannot be divided by the number of data bytes per beat, the data address is determined to be an unaligned address.

3. The data reading method as described in claim 1, characterized in that, The number of data bytes per frame includes the data transmission width, and the step of adjusting the number of data bytes per frame by at least twice once includes: By adjusting the data transmission width by at least one at a time, the number of data bytes per frame is increased by at least twice at a time.

4. The data reading method as described in claim 1, characterized in that, The step of adjusting the data address to the aligned address that is located before the unaligned address and is closest to the unaligned address includes: Adjust the lower two bits of the data address and assign them a value of 0.

5. The data reading method as described in claim 1, characterized in that, Before the step of adjusting the data address and the data transmission control information when the data address is determined to be an unaligned address, the method further includes: Obtain and execute an enable signal to determine whether the data address is an unaligned address.

6. A data reading device, characterized in that, include: The acquisition module is adapted to acquire a first read request that satisfies the AXI bus protocol. The first read request includes the data address of the data to be read and data transmission control information. The data transmission control information includes the number of data bytes per clock cycle, which represents the maximum number of read data bytes transmitted in one clock cycle. The adjustment module is adapted to adjust the data address of the first read request and the data transmission control information to obtain a second read request when it is determined that the data address is an unaligned address. The data address of the second read request is an aligned address, and is used at least to request data at the unaligned address and data at the address following the unaligned address; wherein, adjusting the data address of the first read request and the data transmission control information includes: adjusting the data address of the first read request to the aligned address that is before the unaligned address and closest to the unaligned address; and increasing the number of data bytes per frame in the data transmission control information by at least 2 times once; The sending module is adapted to send the second read request.

7. The data reading device as described in claim 6, characterized in that, Also includes: An unaligned address determination module, adapted to determine that the data address is an unaligned address, includes: When the data address cannot be divided by the number of data bytes per beat, the data address is determined to be an unaligned address.

8. The data reading device as described in claim 6, characterized in that, The number of data bytes per frame includes the data transmission width. The adjustment module is adapted to adjust the number of data bytes per frame by at least twice at one time, including: By adjusting the data transmission width by at least one at a time, the number of data bytes per frame is increased by at least twice at a time.

9. The data reading device as described in claim 6, characterized in that, The adjustment module is adapted to adjust the data address to an aligned address that is located before the unaligned address and is closest to the unaligned address, including: Adjust the lower two bits of the data address and assign them a value of 0.

10. The data reading device as described in claim 6, characterized in that, Also includes: The enable signal acquisition module is adapted to acquire an enable signal for determining whether the data address is an unaligned address.

11. A storage medium, characterized in that, The storage medium stores a program suitable for data reading to implement the data reading method as described in any one of claims 1-5.

12. An electronic device, characterized in that, It includes at least one memory and at least one processor; the memory stores a program, and the processor invokes the program to perform the data reading method as described in any one of claims 1-5.

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