A device and method for improving stability of a slave of an audio bus built-in an integrated circuit

Abstract

The application discloses a device and method for improving stability of a slave of an integrated circuit built-in audio bus. The device comprises a frame synchronization module, a bit counter, an error frame detection module, a shift register, a data control module and a receiving / sending data buffer module; wherein the frame synchronization module receives a clock signal and left and right channel signals sent by a host, and sends a frame synchronization signal to the bit counter; the bit counter receives the clock signal sent by the host and the frame synchronization signal sent by the frame synchronization module, and sends counting data to the error frame detection module and the data control module; the error frame detection module receives the left and right channel signals sent by the host and the counting data sent by the bit counter, and sends an error frame signal to the outside. The application resets the bit counter through the frame synchronization signal, ensures that each frame of data is independent of each other and is not affected by the previous frame error, thereby greatly improving the stability of the slave in receiving data.

Description

Technical Field

[0001] This invention relates to a device and a corresponding method for improving the stability of a slave device with an integrated circuit's built-in audio bus, belonging to the field of digital audio equipment technology. Background Technology

[0002] The Inter-IC Sound (I2S) bus is a standard bus for audio data transmission between digital audio devices. It defines both the hardware interface specifications and the format of digital audio data. The I2S bus is widely used in various multimedia systems, which include at least clock channels, data channels, and left and right audio channels.

[0003] Chinese utility model patent CN213213843U discloses a digital audio mute control circuit and a digital audio system. The control circuit includes a clock module and a control module. The control module determines whether there is no DATA signal on the I2S bus for a preset time based on the reference clock signal output by the clock module. If no DATA signal is detected, the I2S receiving module is controlled to operate normally. If no DATA signal is detected, it indicates that the I2S data source has shut down the I2S bus signal output, and the I2S receiving module is controlled to stop working. This ensures that the I2S receiving module is not affected by the I2S bus after the interrupt signal output, guaranteeing the subsequent normal operation of the I2S receiving module and improving its reliability and stability.

[0004] When I2S is used as a slave device, the clock channel and left and right audio channels are provided by the master device. Therefore, interference may occur during transmission, causing glitches in the clock signal or left and right audio channel signals. These glitches can affect the slave device's data reception or transmission. However, current technology only ensures that the I2S receiver module is unaffected by I2S bus signal interruptions, but does not address the impact caused by glitches. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a device for improving the stability of the built-in audio bus slave device of an integrated circuit.

[0006] Another technical problem to be solved by the present invention is to provide a method for improving the stability of the slave device of the built-in audio bus of an integrated circuit.

[0007] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0008] According to a first aspect of the present invention, an apparatus for improving the stability of a slave device on an integrated circuit's built-in audio bus is provided, comprising a frame synchronization module, a bit counter, an error frame detection module, a shift register, a data control module, and a receive / transmit data buffer module; wherein,

[0009] The frame synchronization module receives the clock signal and left and right channel signals sent by the host, and sends the frame synchronization signal to the bit counter.

[0010] The bit counter receives the clock signal sent by the host and the frame synchronization signal sent by the frame synchronization module, and sends counting data to the error frame detection module and the data control module;

[0011] The error frame detection module receives the left and right channel signals sent by the host and the counting data sent by the bit counter, and sends the frame error signal outward.

[0012] The shift register receives the clock signal sent by the host, the data configured in the register, and the data sent by the receive / transmit data buffer module, and sends data to the receive / transmit data buffer module;

[0013] The receive / transmit data buffer module receives data sent by the data control module and the shift register, and sends the data to the shift register after buffering.

[0014] Preferably, the frame synchronization module includes a register, a first NOT gate N1, a second NOT gate N2, a first AND gate A1, a second AND gate A2, and a mode selection unit; wherein, the left and right channel signals input from the external audio channel are divided into a first channel signal WS1 and a second channel signal WS2; the first channel signal WS1 is further divided into two paths, one of which is connected to the input terminal of the first NOT gate N1, and the output terminal of the first NOT gate N1 is connected to one input terminal of the first AND gate A1; the other path is connected to one input terminal of the second AND gate A2; the second channel signal WS2 is connected to the D terminal of the register.

[0015] Preferably, the clock signal is divided into a first clock signal CK1 and a second clock signal CK2. The first clock signal CK1 is connected to the CK terminal of the register; the second clock signal CK2 is connected to one input terminal of the bit counter; the Q terminal of the register outputs the left and right channel sampling signals, which are then divided into two paths. One path is connected to the other input terminal of the first AND gate A1; the other path is connected to the input terminal of the second NOT gate N2. The output terminal of the second NOT gate N2 is connected to the other input terminal of the second AND gate A2; the output terminals of the first AND gate A1 and the second AND gate A2 are both connected to the input terminal of the mode selection unit; the output terminal of the mode selection unit is connected to the other input terminal of the bit counter.

[0016] Preferably, the mode selection unit uses rising edge pulses and / or falling edge pulses generated when the audio channel signal changes, according to the mode selected by the register.

[0017] Preferably, when the left and right audio channels change, the frame synchronization module generates a frame synchronization signal to reset the bit counter; the bit counter synchronizes the recorded value to the data control module.

[0018] Preferably, the error frame detection module uses a standard format as a reference. When the left and right channels are reversed prematurely in the current frame and / or the clock signal has glitches, the internal counter of the error frame detection module will overcount or undercount, thus generating an error frame signal.

[0019] Preferably, the shift register latches the data sent by the host into the shift register at the clock sampling edge, and sends the entire frame of data into the data register at the end of the frame.

[0020] Preferably, the shift register temporarily latches the data to be sent into the shift register and sends the data to the host on the previous changing edge of the clock sampling edge.

[0021] Preferably, when the bit counter counts to 1, the data control module sends a transmit permission signal to the transmit data buffer, allowing the transmit data buffer to send the next data to the shift register; when the bit counter counts to 15, the data control module sends a receive permission signal to the receive data buffer, allowing the receive data buffer to receive the data in the current shift register.

[0022] According to a second aspect of the present invention, a method for improving the stability of a slave device on an integrated circuit's built-in audio bus is provided, comprising the following steps:

[0023] S1: Acquire left and right channel signals and left and right channel sampling signals;

[0024] S2: Invert the left and right channel signals through the first NOT gate N1; invert the left and right channel sampled signals through the second NOT gate N2;

[0025] S3: Perform a logical AND operation on the left and right channel signals and the left and right channel sampled inverse signals to obtain the first logic signal S1; perform a logical AND operation on the left and right channel inverse signals and the left and right channel sampled signals to obtain the second logic signal S2;

[0026] S4: Select the first logic signal S1 and / or the second logic signal S2 according to the current mode to obtain the frame synchronization signal;

[0027] S5: The frame synchronization signal clears the bit counter to zero, thus achieving frame synchronization.

[0028] Compared with the prior art, the present invention resets the bit counter by using a frame synchronization signal, that is, clears the bit counter to zero, thereby isolating each frame of data. In other words, each frame is independent of the others. Therefore, if there is no glitch interference in the next frame of data, the next frame will resume normal data reception. This solves the problem in the prior art where errors in the previous frame of data lead to continuous errors in subsequent data, and greatly improves the stability of the slave device receiving data. Attached Figure Description

[0029] Figure 1(a) is a simplified structural diagram of a device for improving the stability of a slave device with an integrated circuit built-in audio bus according to an embodiment of the present invention;

[0030] Figure 1(b) is a detailed structural diagram of a device for improving the stability of a slave device with an integrated circuit built-in audio bus according to an embodiment of the present invention;

[0031] Figure 2 A flowchart illustrating a method for improving the stability of a slave device with an integrated circuit's built-in audio bus, provided by an embodiment of the present invention;

[0032] Figure 3 This is a timing diagram of the generation of the frame synchronization signal in an embodiment of the present invention;

[0033] Figure 4 This is an error timing diagram of clock glitch in an embodiment of the present invention. Detailed Implementation

[0034] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0035] As shown in Figure 1(a), the first embodiment of the present invention discloses a device for improving the stability of a slave device on an integrated circuit's built-in audio bus, including a frame synchronization module, a bit counter, an error frame detection module, a shift register, a data control module, and a receive / transmit data buffer module. The frame synchronization module receives a clock signal and left / right channel signals sent by the host, and then sends the frame synchronization signal to the bit counter. The bit counter receives the clock signal sent by the host and the frame synchronization signal sent by the frame synchronization module, and sends counting data to the error frame detection module and the data control module. The error frame detection module receives the left / right channel signals sent by the host and the counting data sent by the bit counter, and sends a frame error signal. The shift register receives the clock signal sent by the host, register configuration data, and data sent by the receive / transmit data buffer module, and sends data to the receive / transmit data buffer module. The receive / transmit data buffer module receives data sent by the data control module and the shift register, buffers it, and then sends the data to the shift register. Additionally, the data control module also sends data to the receive / transmit data buffer module.

[0036] As shown in Figure 1(b), in one embodiment of the present invention, the frame synchronization module includes a register, a first NOT gate N1, a second NOT gate N2, a first AND gate A1, a second AND gate A2, and a mode selection unit. The left and right channel signals input from the external audio channel are divided into a first channel signal WS1 and a second channel signal WS2. The first channel signal WS1 is split into two paths. One path is connected to the input of the first NOT gate N1, and the output of the first NOT gate N1 is connected to one input of the first AND gate A1. The other path is connected to one input of the second AND gate A2. The second channel signal WS2 is connected to the D terminal of the register. The clock signal is split into a first clock signal CK1 and a second clock signal CK2. The first clock signal CK1 is connected to the CK (clock signal) terminal of the register. The second clock signal CK2 is connected to one input of the bit counter. The Q terminal of the register outputs the left and right channel sampling (WS_R) signals, which are split into two paths. One path is connected to the other input of the first AND gate A1. The other path is connected to the input of the second NOT gate N2, and the output of the second NOT gate N2 is connected to the other input of the second AND gate A2. The outputs of the first AND gate A1 and the second AND gate A2 are both connected to the inputs of the mode selection unit. The output of the mode selection unit is connected to the other input of the bit counter. Here, the mode selection unit uses rising edge pulses and / or falling edge pulses generated when the channel signal changes, according to the mode selected by the register.

[0037] In one embodiment of the present invention, the frame synchronization module generates a frame synchronization signal and resets the bit counter when the left and right audio channels change, i.e., clears the bit counter to zero, ensuring that each frame of data is independent and that errors in the current frame do not affect the next frame. The bit counter synchronizes the recorded value to the data control module. The bit counter records values ​​ranging from 0 to 15, and these values ​​are positive integers.

[0038] In one embodiment of the present invention, the error frame detection module is used as a reference to generate an error frame (frame_err) signal when the left and right channels are reversed prematurely and / or the clock signal is punctured in the current frame, with reference to a standard format.

[0039] In one embodiment of the invention, one function of the shift register is to latch the data sent by the host into the shift register at the clock sampling edge, and to send the entire frame of data into the data register at the end of the frame. Another function of the shift register is to temporarily latch the data to be sent into the shift register, and to send the data to the host on the previous changing edge of the clock sampling edge.

[0040] In one embodiment of the present invention, the receive / transmit data buffer module includes a receive data buffer and a transmit data buffer. This data buffer module is a conventional technique well-known to those skilled in the art, and will not be described in detail here.

[0041] In one embodiment of the present invention, when the bit counter counts to 1, the data control module sends a transmit permission (tx_pop) signal to the transmit data buffer, allowing the transmit data buffer to send the next data to the shift register; when the bit counter counts to 15, the data control module sends a receive permission (rx_push) signal to the receive data buffer, allowing the receive data buffer to receive the data in the current shift register.

[0042] Based on the aforementioned apparatus for improving the stability of integrated circuit built-in audio bus slave devices, the second embodiment of the present invention further provides a method for improving the stability of integrated circuit built-in audio bus slave devices. For example... Figure 2 As shown, the method includes at least the following steps:

[0043] S1: Acquire left and right channel signals and left and right channel sampling signals.

[0044] As shown in Figure 1, the left and right channel signals are obtained from the external audio channel input. The left and right channel sampled signals can be obtained by sampling one beat on the falling edge of the clock signal sent by the host using a register.

[0045] S2: Invert the left and right channel signals through NOT gate N1; invert the left and right channel sampled signals through NOT gate N2.

[0046] S3: Perform a logical AND operation on the left and right channel signals and the left and right channel sampled inverse signals to obtain the first logic signal S1; perform a logical AND operation on the left and right channel inverse signals and the left and right channel sampled signals to obtain the second logic signal S2.

[0047] S4: Select the first logic signal S1 and / or the second logic signal S2 according to the current mode to obtain the SYN signal. The SYN signal here is the frame synchronization signal used internally by the integrated circuit's built-in audio bus.

[0048] S5: The frame synchronization signal clears the bit counter to zero, thus achieving frame synchronization.

[0049] Among them, such as Figure 3 As shown, when the left and right channels switch, the left and right channel signals and the left and right channel sampling signals will output a level edge through combinational logic, that is, a pulse edge of a frame synchronization signal will appear. This pulse edge will clear the bit counter to zero, thereby achieving frame synchronization.

[0050] It should be noted that the above method does not restrict the frame format of the audio signal during implementation. For example, commonly used frame formats such as MSB, LSB, PCM, and TI can all be applied to the method provided in the embodiments of this invention.

[0051] like Figure 4 As shown, the RX_PUSH signal is the control signal for sending serial data into the receive data buffer. When the clock is spiked by external interference, the internal counter of the error frame detection module will count one more time, causing the RX_PUSH signal to be generated one clock cycle earlier. At this time, the slave device may receive erroneous data. This invention resets the bit counter through the frame synchronization signal, that is, clears the bit counter to zero, thereby isolating each frame of data. That is, each frame is independent of the others. Therefore, if the next frame of data is free from spike interference, the next frame will resume normal data reception. This solves the problem in the prior art where errors in the previous frame of data lead to continuous errors in subsequent data, and greatly improves the stability of the slave device's data reception.

[0052] The apparatus and method for improving the stability of integrated circuit built-in audio bus slave devices provided by the present invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of the present invention will constitute an infringement of the patent rights of the present invention and will incur corresponding legal liability.

Claims

1. A device for improving the stability of a slave device with an integrated circuit's built-in audio bus, characterized in that... It includes a frame synchronization module, a bit counter, an error frame detection module, a shift register, a data control module, and a receive / transmit data buffer module; among which, The frame synchronization module includes a first register, a first NOT gate (N1), a second NOT gate (N2), a first AND gate (A1), a second AND gate (A2), and a mode selection unit. The left and right channel signals input from the external audio channel are divided into a first channel signal (WS1) and a second channel signal (WS2). The first channel signal (WS1) is further divided into two paths: one path is connected to the input of the first NOT gate (N1), and the output of the first NOT gate (N1) is connected to one input of the first AND gate (A1); the other path is connected to one input of the second AND gate (A2). The second channel signal (WS2) is connected to the D terminal of the first register. The frame synchronization module receives the clock signal and left and right channel signals sent by the host, and sends the frame synchronization signal to the bit counter. The bit counter receives the clock signal sent by the host and the frame synchronization signal sent by the frame synchronization module, and sends counting data to the error frame detection module and the data control module; The clock signal is divided into a first clock signal (CK1) and a second clock signal (CK2). The first clock signal (CK1) is connected to the CK terminal of the first register; the second clock signal (CK2) is connected to one input terminal of the bit counter; the Q terminal of the first register outputs the left and right channel sampling signals, which are then divided into two paths. One path is connected to the other input terminal of the first AND gate (A1); the other path is connected to the input terminal of the second NOT gate (N2). The output terminal of the second NOT gate (N2) is connected to the other input terminal of the second AND gate (A2); the output terminals of the first AND gate (A1) and the second AND gate (A2) are both connected to the input terminal of the mode selection unit; the output terminal of the mode selection unit is connected to the other input terminal of the bit counter. When the left and right audio channels change, the frame synchronization module generates a frame synchronization signal and clears the bit counter to zero; the bit counter synchronizes the recorded value to the data control module. The error frame detection module receives the left and right channel signals sent by the host and the counting data sent by the bit counter, and sends the frame error signal outward. The error frame detection module uses a standard format as a reference. When the left and right audio channels are reversed prematurely and / or the clock signal has glitches in the current frame, the internal counter of the error frame detection module will overcount or undercount, thus generating an error frame signal. The shift register receives the clock signal sent by the host, the data configured in the second register, and the data sent by the receive / transmit data buffer module, and sends data to the receive / transmit data buffer module; The receive / send data buffer module includes a send data buffer and a receive data buffer; When the bit counter counts to 1, the data control module sends a transmit permission signal to the transmit data buffer, allowing the transmit data buffer to send the next data to the shift register; when the bit counter counts to 15, the data control module sends a receive permission signal to the receive data buffer, allowing the receive data buffer to receive the data currently in the shift register. The receive / transmit data buffer module receives data sent by the data control module and the shift register.

2. The apparatus as described in claim 1, characterized in that: The mode selection unit uses rising edge pulses and / or falling edge pulses generated when the audio channel signal changes, according to the mode selected by the second register.

3. The apparatus as described in claim 1, characterized in that: The shift register latches the data sent by the host into the shift register at the clock sampling edge, and sends the entire frame of data into the data register at the end of the frame.

4. The apparatus as claimed in claim 1, characterized in that: The shift register temporarily latches the data to be sent and sends the data to the host on the previous edge of the clock sampling edge.

5. A method for improving the stability of a slave device on an integrated circuit's built-in audio bus, implemented using the apparatus described in any one of claims 1 to 4, characterized in that... Includes the following steps: S1: Acquire left and right channel signals and left and right channel sampling signals; S2: Invert the left and right channel signals through the first NOT gate (N1); invert the left and right channel sampled signals through the second NOT gate (N2); S3: Perform a logical AND operation on the left and right channel signals and the left and right channel sampled inverse signals to obtain the first logic signal; perform a logical AND operation on the left and right channel inverse signals and the left and right channel sampled signals to obtain the second logic signal; S4: Select the first logic signal S1 and / or the second logic signal S2 according to the current mode to obtain the frame synchronization signal; S5: The frame synchronization signal clears the bit counter to zero, thus achieving frame synchronization.

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