A many-core intelligent processor communication architecture design method based on a network on chip

Abstract

The application provides a many-core intelligent processor communication architecture design method based on a network on chip, the many-core intelligent processor comprises resource nodes, communication nodes, network interfaces and network paths, and the method comprises the following steps: step 1, a wormhole router supporting end-to-end data continuous transmission is used to constitute the communication nodes; step 2, the network interfaces are optimized and designed. The application proposes a wormhole routing network architecture supporting end-to-end data continuous (burst) transmission, and large-scale data can be efficiently transmitted; the application proposes a high-bandwidth cross-node Ruche channel, and the overall bandwidth of the network is further improved; and the application proposes a tensor instruction sharing scheme, so as to reduce the network load caused by different tensor calculation cores reading the same instruction.

Description

Technical Field

[0001] This invention relates to a design method for a communication architecture of many-core intelligent processors based on on-chip networks. Background Technology

[0002] Improving the performance of a single processor core to enhance overall system performance has become extremely difficult. Increasing the number of processor cores on a single chip has become an inevitable trend for further improving computer performance. Traditional on-chip multi-core systems typically employ dedicated buses or crossbar interconnects, but as the number of processor cores integrated onto a single chip increases, traditional interconnect architectures suffer from low communication efficiency and poor scalability. This limits the number of processors that can be integrated onto a single chip.

[0003] To further increase the number of processor cores on a single chip, the paper "S. Davidson et al., 'The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips,'" in IEEE Micro, vol. 38, no. 2, pp. 30-41, Mar. / Apr. 2018, doi: 10.1109 / MM.2018.022071133" employs a two-dimensional mesh network to implement a many-core processor. However, the routing network it uses requires arbitration by an arbitrator every time data is transmitted, which affects the bandwidth of a large amount of data transmitted in the network. The paper "A. Kurth et al., 'An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication,'" in IEEE Transactions on... The paper "Computers, vol.71, no.8, pp.1794-1809, 1 Aug.2022, doi:10.1109 / TC.2021.3107726" uses an improved fully connected crossbar switch to implement a tree topology architecture to integrate a large number of processor cores. Based on this architecture, the performance of a loaded neural network was evaluated and the corresponding algorithm was improved. The long crossbar switch used in this architecture has problems such as increased latency due to excessive wiring, which limits the expansion of processor cores. Summary of the Invention

[0004] Purpose of the Invention: To address the problems of poor scalability due to limited address space in traditional bus architectures, low communication efficiency caused by time-sharing communication, and power consumption and area issues caused by global clock synchronization, this invention proposes a many-core intelligent processor architecture based on on-chip networks. The proposed on-chip network many-core interconnect architecture mainly draws on the communication methods of distributed computing systems, using data routing and packet switching technologies to replace the traditional bus structure, thereby improving communication efficiency and scalability. Furthermore, this on-chip network architecture has been optimized to address the characteristic of algorithms such as convolutional neural networks that require the transfer of large amounts of data from memory, further enhancing the overall network communication efficiency.

[0005] This invention specifically provides a method for designing a many-core intelligent processor architecture based on on-chip networks. The many-core intelligent processor includes resource nodes, communication nodes, network interfaces, and network paths. The method of this invention specifically includes the following steps:

[0006] Step 1: Use a wormhole router that supports continuous end-to-end data transmission to form communication nodes;

[0007] Step 2: Optimize the design of the network interface.

[0008] In step 1, the wormhole router includes an input channel and an output channel. The input channel includes a decoder, an input control module, a counter, and a FIFO memory. The output channel includes an output control module, an arbitrator, and a multiplexer.

[0009] In step 1, when a valid data packet is input to a link of the input channel, it is first buffered by the FIFO memory, and then the target coordinate information in the header of the data packet is sent to the decoder. The decoder compares the target coordinate information with the current coordinate information and sends the target direction signal to the input control module. Subsequently, the input control module broadcasts a request signal to the polling arbitrator in the output control module. The output control module sends a selection signal to the multiplexer according to the arbitration result to control the output of the data packet of the output channel link.

[0010] In step 1, the header of the data packet also contains a length information that is sent to a decrementing counter in the input control module. The decrementing counter sets the initial count value to the data packet length and decrements it according to the handshake signals between the input and output channels until it reaches zero. The input control module also sends a release signal to the output control module according to the count value to maintain data transmission on the output channel until the entire data packet transmission is complete.

[0011] In step 2, the network interface is the interface between the communication node and the resource node, which is used to encapsulate and decapsulate data packets. In the resource network interface of the source node, the source address information and the destination address information are encapsulated into the header of the data packet, and in the resource network interface of the destination node, the source address information and the destination address information are deleted.

[0012] In step 2, the network interface includes an adapter and an endpoint module. The adapter includes a transmitting adapter and a receiving adapter. The transmitting adapter acts as the master, completing the initial packaging of the computing node signals and converting the endpoint virtual address (EVA) directly used by the processor core of each computing node into a network physical address (NPA).

[0013] In step 2, the receiving adapter acts as a slave, responsible for distributing externally received signals to the processor core or cache, and transmitting the response data from the processor core or cache to the endpoint module.

[0014] In step 2, the endpoint module packages all signals into a data packet based on the adapter and sends it to the target node through the routing link, as well as decapsulating incoming data packets from outside.

[0015] In step 2, the endpoint module also has a credit counter to track the number of untransmitted data packets and the FIFO buffer capacity in the network. The credit counter starts from the maximum number of untransmitted data packets and decrements once for each packet sent. The endpoint module at the target coordinates of the data packet transmission will return the loaded data response or the stored credit data packet. After the source router receives the data response, it will restart the counter.

[0016] Furthermore, the method of the present invention also includes step 3: the resource node includes a computing node and a storage node. The computing node adopts a highly programmable sparse tensor computing kernel. The tensor computing kernel instruction sharing structure is designed as follows: when different computing kernels perform convolution operations, except for the first computing kernel which needs to fetch instructions, the other computing kernels directly skip the instruction fetch stage and turn off the instruction cache. The computing kernel that needs to fetch instructions passes the address PC of the next instruction to the instruction cache. After completing the instruction fetch, the instruction is passed to the pipeline register for decoding. In addition, the instruction is also transmitted through the instruction network INET. The other computing kernels directly receive instructions from the instruction network INET, buffer them in the FIFO memory, and then pass them through the multiplexer to the instruction cache and pipeline register for decoding.

[0017] The present invention has the following beneficial effects: (1) The present invention proposes a wormhole routing network architecture that supports continuous (burst) transmission of end-to-end data, which can efficiently transmit large-scale data;

[0018] (2) This invention proposes a high-bandwidth cross-node Ruche channel to further improve the overall network bandwidth;

[0019] (3) This invention proposes a tensor instruction sharing scheme to reduce the network load caused by different tensor computation cores reading the same instructions. Attached Figure Description

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0021] Figure 1 This is a schematic diagram of the overall design of a two-dimensional mesh routing network.

[0022] Figure 2 This is a schematic diagram of the wormhole routing structure.

[0023] Figure 3 This is a schematic diagram illustrating the working principle of a credit counter.

[0024] Figure 4 This is a schematic diagram of a two-dimensional mesh network with Ruche channels (Ruche coefficients X=3, Y=2).

[0025] Figure 5 This is a horizontal metal wiring diagram of the Ruche channel.

[0026] Figure 6 This is a schematic diagram of the core instruction sharing architecture.

[0027] Figure 7 It is a transaction transfer path diagram between the master and slave processor cores.

[0028] Figure 8 It is a transaction transfer path diagram between the processor core and the LLC.

[0029] Figure 9 This is a data transfer path diagram between two adjacent final-level cache LLCs. Detailed Implementation

[0030] This invention provides a design method for a communication architecture of a many-core intelligent processor based on an on-chip network, specifically including:

[0031] Overall design of on-chip network communication architecture for many-core processors:

[0032] The many-core processor consists of four types of modules: resource nodes, communication nodes (mainly composed of routers), network interfaces (mainly composed of endpoints and adapters), and network pathways. This invention mainly relates to the communication nodes and network interfaces, specifically the innovative design and optimization of routers, endpoint modules, and adapters. The overall design of the two-dimensional mesh routing network is as follows: Figure 1 As shown.

[0033] Resource nodes primarily consist of two categories: compute nodes and storage nodes. Compute nodes can be composed of processors and various accelerators, while storage nodes typically use DRAM and SDRAM as memory. Furthermore, resource nodes can also serve as I / O interfaces to connect external devices. Compute nodes can utilize highly programmable sparse tensor kernels to support various deep neural network (DNN) models.

[0034] Communication nodes, also known as routing nodes or routers, are primarily responsible for data communication between resource nodes. When a resource node in a Network-on-Chip (NoC) generates a data packet, it sends it to the source router through a specific interface. The source router reads the address information in the packet header and selects the optimal routing path using algorithms such as round-robin arbitration, quickly transmitting the data packet sent by the source node (usually the computing core initiating the read / write command) to the target node, thus achieving end-to-end data communication within the chip (between processors, accelerators, and memory). This invention primarily uses wormhole routers that support continuous end-to-end data transmission to construct the communication nodes.

[0035] A network interface is the interface between a communication node and a resource node. Its main function is to encapsulate and decapsulate data packets. In the resource network interface of the source node, source address information and destination address information are encapsulated into the header of the data packet, and in the resource network interface of the destination node, the source address information and destination address information are deleted. In this invention, the network interface is mainly divided into two parts: an adapter and an endpoint module. The adapter is mainly divided into two types: transmitting and receiving. The transmitting adapter acts as the master, performing the initial packaging of signals from the computing node (processor or cache) and converting the endpoint virtual address (EVA) to the network physical address (NPA). The receiving adapter acts as the slave, responsible for distributing incoming signals to the processor core or cache, and transmitting the response data from the core or cache to the endpoint.

[0036] A network path is essentially a bidirectional metal link used to ensure data transmission between nodes. It is divided into internal channels and external channels. Internal channels are metal links between resource nodes and communication nodes, while external channels are metal links between communication nodes.

[0037] Wormhole Router Module Design:

[0038] Before performing calculations, algorithms like CNNs often require transmitting large amounts of data, such as reading a complete feature map from DDR. Conventional routers arbitrate based on the target node's coordinates for each data transmission. When continuously transmitting large amounts of data with the same or adjacent addresses to the same target node, according to the round-robin arbitration algorithm, if an input channel has already sent data to an output channel, its priority will decrease. If another input channel then requests data from this output channel, the data transmission between the two channels will be interrupted, leading to increased routing network latency and power consumption. The wormhole router used in this solution effectively solves this problem.

[0039] like Figure 2 As shown, the wormhole router includes an input channel and an output channel. The input channel includes a decoder, an input control module, a counter, and a first-in-first-out (FIFO) memory. The output channel includes an output control module, an arbitrator, and a multiplexer.

[0040] When a valid data packet is input to a link of the input channel, it is first buffered by the FIFO memory, and then the target coordinate information in the header of the data packet is sent to the decoder. The decoder compares the target coordinate information with the current coordinate information (comparing the horizontal coordinate first, and then the vertical coordinate) and sends the target direction (output channel) signal to the input control module. Subsequently, the input control module broadcasts a request signal to the polling arbitrator in the output control module. The output control module sends a selection signal to the multiplexer according to the arbitration result to control the output of data packets of the output channel link.

[0041] In addition, the data packet header contains a length information that is sent to a decrementing counter in the input control module. The decrementing counter sets its initial value to the data packet length and decreases according to the handshake signals between the input and output channels (a successful handshake between any two channels indicates a successful data transmission cycle), until it reaches zero. The input control module also sends a release signal to the output control module based on the count value to maintain data transmission on the output channel until the entire data packet transmission is complete (the count value returns to zero).

[0042] The number of input and output channels and the corresponding number of functional modules of the router can be adjusted according to different network topologies. In the two-dimensional mesh network used in this invention, it is generally set to 7 pairs of input and output channels (5 pairs of conventional channels and 2 pairs of Ruche channels).

[0043] Endpoint module design:

[0044] The endpoint module, building upon the adapter, encapsulates all signals into a single data packet and sends it to the target node via the routing link. It also decapsulates incoming data packets. Furthermore, such as... Figure 3 As shown, the endpoint module also contains a credit counter to track the number of packets with incomplete transmissions and the FIFO buffer capacity in the network. The credit counter starts at the maximum number of packets with incomplete transmissions and decrements with each transmitted packet. The endpoint module at the destination coordinates returns either the loaded data response or the stored credit data packet. Upon receiving these responses, the source router resets the counter. This credit counter can be used to implement memory barriers to prevent FIFO overflows within the network.

[0045] Ruche passage design:

[0046] Communication between nodes that are far apart can result in significant latency. Algorithms such as convolutional neural networks often require the transmission of large amounts of data between different computing cores, which places very high demands on the overall network bandwidth. Therefore, this solution adds an extra set of routers to each communication node to achieve parallel high-bandwidth link channels across nodes. Figure 4 , Figure 5 This demonstrates a two-dimensional mesh network and horizontal metallic cabling for implementing Ruche (ribbon) channels (Ruche coefficients X=3, Y=2). From Figure 5 As can be seen, each TILE node block not only has a Local Router that makes up the regular routing network, but also a set of Ruche Router routers used to implement the Ruche channel. INV stands for inverter.

[0047] Tensor computation kernel instruction sharing architecture design:

[0048] Different computational cores use essentially the same instructions when performing convolution operations. Therefore, except for the first core which needs to fetch instructions, the other cores (within the same row or column) can directly skip the instruction fetch stage and disable the instruction cache. For example... Figure 6 As shown, the core that needs to fetch instructions passes the address of the next instruction (NPC) to the instruction cache. After fetching, it passes the instruction to the pipeline register for decoding. In addition, instructions are also transmitted through the instruction network (INET). Other cores receive instructions directly from the INET (including those from the four directions: North (N), East (E), South (S), and West (W), buffer them in the FIFO memory, and then pass them through a multiplexer to the instruction cache (the enable signal en needs to be high) and pipeline register for decoding. This structure speeds up instruction fetching and reduces the network load caused by each core updating its instruction cache.

[0049] Data packet transmission instructions:

[0050] Data packet transmission between processor cores and adjacent processor cores:

[0051] Figure 7 It demonstrates the transaction transfer path (load or store instructions) between a pair of master and slave processor cores.

[0052] As can be seen from the figure, the remote request signal is sent out from the load / store unit (LSU) module of the host-side tensor computation core and sent to the host-side adapter along the corresponding channel.

[0053] The address translation unit within the adapter converts the endpoint virtual address in the remote request signal from the tensor computation core into a network physical address (i.e., the target node's network coordinates and its endpoint physical address) through memory mapping. Subsequently, the adapter packages the request signal, address information, etc., into a data packet and sends it to the endpoint module.

[0054] The endpoint further packages and encapsulates the request packet and its valid signals, and sends it along the forward link to the wormhole router. Additionally, the endpoint has an internal credit counter to record information about the sent request packets and received response packets.

[0055] After receiving a request data packet, the forward wormhole router on the host side will select the appropriate output link by comparing the target node coordinates with the current node coordinates and send the data packet to the next routing node.

[0056] exist Figure 7 In the example, the next routing node is the target node, so the forward wormhole router in that node will transmit this request packet to the node endpoint (if the current node is not the target node, the router will continue to forward the packet to the next routing node based on the comparison result between the target node coordinates and the current node coordinates, until the target node is reached).

[0057] When the endpoint module receives a request data packet, it first caches it in its internal FIFO memory. Once the processor core has finished processing the previously arrived requests and is ready, the endpoint will decapsulate the request data packet and pass it to the slave adapter.

[0058] The slave adapter then sends this request to the data storage or instruction cache inside the computing core based on information such as instructions and addresses.

[0059] Subsequently, the data memory within the slave computing core will return the data requested by the master to the slave adapter based on the address information in the request signal.

[0060] When the slave adapter receives the returned data, it generates a corresponding valid signal and sends the data requested by the master end and its valid signal to the endpoint.

[0061] The endpoint then packages and encapsulates the data and its valid signals into a response data packet and sends it to the reverse wormhole router via the reverse link.

[0062] The reverse router returns the response packet to the requesting source node along the original path. If the packet contains more than one data unit, the reverse wormhole router maintains the link along this path, allowing all data units within the entire packet to be continuously transmitted from the target node back to the source node without repeated arbitration by an arbitrator (if other data packets need to pass through this link during transmission, they must wait for the transmission to complete).

[0063] After receiving the response packet, the reverse router at the source node forwards it along the reverse link to the endpoint, buffers it in the endpoint's FIFO, and raises the valid signal high. Once the host adapter handshake is successful, the packet is decapsulated at the endpoint and forwarded to the adapter.

[0064] The adapter transmits the received response data and valid signals to the register file inside the processor core. This completes a full core-to-core remote data transfer transaction.

[0065] Data packet transmission between the processor core and adjacent LLC:

[0066] Figure 8 It demonstrates the transaction transfer path (load or store instructions) between the processor core and the LLC.

[0067] from Figure 8 As can be seen, the remote request signal is sent out from the LSU module of the tensor computation core and sent to the host adapter along the corresponding channel.

[0068] The address translation unit within the host adapter converts the endpoint virtual address in the remote request signal from the tensor computation core into a network physical address (i.e., the target node's network coordinates and its endpoint physical address) through memory mapping. Subsequently, the host adapter packages the request signal, address information, etc., into a data packet and sends it to the endpoint.

[0069] The endpoint further packages and encapsulates the request packet and its valid signals, and sends it along the forward link to the wormhole router. Additionally, the endpoint has an internal credit counter to record information about the sent request packets and received response packets.

[0070] After receiving a request data packet, the forward wormhole router of the computing node selects the appropriate output link by comparing the target node coordinates with the current node coordinates and sends the data packet to the next routing node.

[0071] In this Figure 8In the example, the next routing node is the target node, so the forward wormhole router in the host node will transmit this request packet to the node endpoint (if the current node is not the target node, the forward wormhole router will continue to forward the packet to the next routing node based on the comparison result between the target node coordinates and the current node coordinates, until the target node is reached).

[0072] When a node endpoint receives a request packet, it first caches it in its internal FIFO memory. Once the last-level cache LLC has finished processing the previously arrived requests and is ready, the endpoint will decapsulate the request packet and pass it to the last-level cache LLC.

[0073] Subsequently, the last-level cache LLC will return the relevant data and valid signals to the endpoint based on the address information in the request signal.

[0074] The endpoint will package and encapsulate the data and its valid signals into a data packet, and send the data packet to the reverse wormhole router via the reverse link.

[0075] The reverse router then returns the response packet to the requesting source node along the original path. If the data packet contains more than one frame, the reverse wormhole router will maintain the link along this path, allowing all frames of data within the entire packet to be continuously transmitted from the target node back to the source node without the need for repeated arbitration by an arbitrator (if other data packets need to pass through this link during transmission, they must wait for the transmission to complete).

[0076] After receiving the response packet, the reverse router at the source node forwards it along the reverse link to the endpoint, first buffering it in the endpoint's FIFO memory and then activating the valid signal. Once the adapter handshake on the host side is successful, the packet is decapsulated at the endpoint and then forwarded to the adapter.

[0077] The adapter transmits the received response data and valid signals to the register file inside the processor core. At this point, a complete remote transfer transaction from the core to the final cache (LLC) is completed.

[0078] Data transfer between the last-level cache LLC and adjacent last-level cache LLCs:

[0079] The last-level cache LLC can actively send data to other last-level cache LLCs through its internal DMA direct storage access module. Figure 9 The diagram illustrates the path for transferring data from the last-level buffer LLC to another adjacent LLC.

[0080] like Figure 9As shown, the DMA routing module (i.e., the DMA adapter) has a send state machine. By default, it will automatically jump to the SEND_READY (i.e., send ready) state after reset. In this state, the endpoint module of another cache will send the coordinates and other information of the target cache to its own wormhole router (path ①) in order to try to establish a transmission channel with the wormhole router of the target cache.

[0081] At the same time, the DMA will send a write enable signal and address information to the DMA routing module (which is first buffered by the FIFO memory) through the DMA packet output signal.

[0082] When the handshake is successful with the Ready signal (which will go high if the FIFO for receiving data is not full) from the target wormhole route, the sending state machine will enter the SEND_ADDR (i.e., sending address) state, and then send the address information in the DMA packet output signal to the target cache through the cache route output link (②).

[0083] Subsequently, if the handshake is still successful, the sending state machine will jump to the SEND_DATA state, and the DMA will continue to send data to the target cache through the DMA data output signal and the cache route output link (③).

[0084] During the transmission of address and data, the receive state machine in the DMA routing module of the target cache will always be in the RECV_DATA state to maintain the smooth flow of the data channel.

[0085] This solution proposes a two-dimensional mesh network architecture based on wormhole routers and adds an additional Ruche channel to improve network performance under heavy data transmission loads. Furthermore, since different tensor computation kernels use highly repetitive instructions for convolution operations, the network also implements an instruction-sharing structure to reduce the network load caused by multiple different tensor computation kernels reading the same instructions.

[0086] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding a many-core intelligent processor communication architecture design method based on an on-chip network, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0087] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MUU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0088] This invention provides a design method for a communication architecture of a many-core intelligent processor based on on-chip network. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A method for designing a communication architecture for a many-core intelligent processor based on on-chip networks, wherein the many-core intelligent processor includes resource nodes, communication nodes, network interfaces, and network paths, characterized in that, Includes the following steps: Step 1: Use a wormhole router that supports continuous end-to-end data transmission to form communication nodes; In step 1, when a valid data packet is input to one of the input channels, it is first buffered by a FIFO memory, and then the target coordinate information in the packet header is sent to the decoder. The packet header also contains length information, which is sent to a decrementing counter in the input control module. The decrementing counter sets its initial count value to the packet length and decreases according to the handshake signals between the input and output channels until it reaches zero. The input control module also sends a release signal to the output control module based on the count value to maintain data transmission in the output channel until the entire data packet transmission is complete. Step 2: Optimize the design of the network interface. The network interface includes an adapter and an endpoint module. The endpoint module also contains a credit counter to track the number of uncompleted data packets and the FIFO buffer capacity in the network. The credit counter starts from the maximum number of uncompleted data packets and decrements once for each packet sent. The endpoint module at the target coordinates of the data packet transmission will return the loaded data response or the stored credit data packet. After the source router receives the data response, it will restart the counter. Step 3: The resource nodes include computing nodes and storage nodes. The computing nodes adopt highly programmable sparse tensor computing kernels. The tensor computing kernel instruction sharing structure is designed as follows: When different computing kernels perform convolution operations, except for the first computing kernel which needs to fetch instructions, the other computing kernels directly skip the instruction fetch stage and turn off the instruction cache. The computing kernel that needs to fetch instructions passes the address PC of the next instruction to the instruction cache. After completing the instruction fetch, the instruction is passed to the pipeline register for decoding. The instruction is also transmitted through the instruction network INET. The other computing kernels directly receive instructions from the instruction network INET, buffer them in the FIFO memory, and then pass them through the multiplexer to the instruction cache and pipeline register for decoding.

2. The method according to claim 1, characterized in that, In step 1, the wormhole router includes an input channel and an output channel. The input channel includes a decoder, an input control module, a counter, and a FIFO memory. The output channel includes an output control module, an arbitrator, and a multiplexer.

3. The method according to claim 2, characterized in that, In step 1, the decoder compares the target coordinate information with the current coordinate information and sends the target direction signal to the input control module. Then, the input control module broadcasts a request signal to the polling arbitrator in the output control module. The output control module sends a selection signal to the multiplexer according to the arbitration result to control the output of the output channel link data packets.

4. The method according to claim 3, characterized in that, In step 2, the network interface is the interface between the communication node and the resource node, used to complete the encapsulation and decapsulation of data packets. In the resource network interface of the source node, the source address information and the destination address information are encapsulated into the header of the data packet, and in the resource network interface of the destination node, the source address information and the destination address information are deleted.

5. The method according to claim 4, characterized in that, In step 2, the adapter includes a transmitting adapter and a receiving adapter. The transmitting adapter acts as the master, performs the initial packaging of the computing node signals, and converts the endpoint virtual address (EVA) directly used by the processor core of each computing node into a network physical address (NPA).

6. The method according to claim 5, characterized in that, In step 2, the receiving adapter acts as a slave, responsible for distributing externally received signals to the processor core or cache, and transmitting the response data from the processor core or cache to the endpoint module.

7. The method according to claim 6, characterized in that, In step 2, the endpoint module packages all signals into a data packet based on the adapter and sends it to the target node through the routing link, as well as decapsulating incoming data packets from outside.

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