串联快速加载位流实现方法、装置、设备和计算机可读介质
By separating the PCIe serial bit stream data, the problem of excessively long PCIe link configuration time caused by the increasing size of FPGA devices or the complexity of engineering is solved, and a method for fast bit stream loading is realized, which is suitable for rapid PCIe link establishment of programmable logic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PANGO MICROSYST CO LTD
- Filing Date
- 2022-12-09
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies struggle to load or compress bitstream data within a specified timeframe, especially as FPGA devices become larger or engineering complex, leading to excessively long PCIe link configuration times.
By reading the netlist to obtain layout and routing information, generating calibration information, and converting it into configuration point information for hardware circuits, complete bit stream data and PCIe serial bit stream data are generated. The PCIe serial bit stream data is then separated to achieve fast link establishment.
It enables rapid configuration of the PCIe link when the FPGA device size increases or the engineering complexity increases, reducing loading time and taking into account the compatibility and flexibility of the overall data flow.
Smart Images
Figure CN116050329B_ABST