Method and apparatus for static timing analysis of perceivable dynamic power noise
By using a deformed Weber distribution and a multilayer perceptron neural network model, the timing performance of standard circuit cells under dynamic power supply noise is accurately predicted. This solves the problem that the impact of dynamic power supply noise is not accurately measured in static timing analysis, and improves the accuracy of circuit timing analysis and chip performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2022-12-08
- Publication Date
- 2026-08-04
AI Technical Summary
Existing static timing analysis methods cannot accurately measure the impact of dynamic power supply noise on circuit timing, which may lead to timing errors or wasted operating frequency in actual circuit operation.
Dynamic power supply noise is modeled using the cumulative probability distribution function of the deformed Weber distribution. By combining the time misalignment factor and the noise shape factor, a multilayer perceptron neural network model is used to predict the time delay and output signal transformation time of the standard circuit unit under different dynamic noise conditions.
It achieves accurate measurement of dynamic power supply noise, improves the accuracy of timing analysis, ensures correct circuit timing and improves chip performance, with an average relative error of 6.43% for critical path delay prediction results.
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Figure CN116050332B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit verification technology, and in particular to a static timing analysis method and apparatus capable of sensing dynamic power supply noise. Background Technology
[0002] With the advancement of VLSI (Very Large Scale Integration) technology, chip operating voltages are decreasing, leading to lower system noise margins. Simultaneously, the increasing transistor density results in continuously rising current density in integrated circuits; shrinking process dimensions lead to thinner power supply metal layers, resulting in higher sheet resistance in the power supply network. These two factors make power integrity issues increasingly prominent in advanced processes. Furthermore, traditional static timing analysis does not consider the impact of power supply noise, causing designers to have growing concerns about the accuracy of their analysis results in real-world scenarios.
[0003] To improve this situation, foundries provide library files that record the timing information of standard circuit cells under different power supply voltages at various process nodes. Based on the results of static power supply noise simulation, the static voltage drop of each standard cell can be marked during simulation, and the estimated timing results can be calculated by interpolation from multiple library files based on this voltage drop. In older process designs, the power supply network has sufficient decoupling capacitors to filter out all high-frequency components of noise, and the noise does not change much within a clock cycle, so the average noise value is highly representative. Therefore, this method based on static power supply simulation has good accuracy on older processes. However, as process nodes shrink, the decoupling capacitors on the power supply network become increasingly insufficient to filter out high-frequency noise, leading to a decrease in the accuracy of the static power supply noise simulation method.
[0004] In reality, power supply noise is dynamic, not static. Static power supply noise analysis focuses on the average voltage drop of the power grid, while dynamic power supply noise analysis is based on the circuit's switching behavior, and its results are highly correlated with the input vector. Furthermore, dynamic power supply noise depends on the logic switching time, unlike static power supply voltage drops which are significantly affected by the circuit clock cycle. Therefore, one class of methods eliminates the problem of a large difference between the actual voltage at the time of a standard cell switch and the voltage over a clock cycle by calculating the actual equivalent supply voltage at the time of standard cell switch. These methods provide a very accurate estimate of the average supply voltage of each standard cell during actual operation, thus improving the accuracy of timing predictions compared to methods based on static simulation. However, these methods essentially use the integral value of dynamic noise over a period of time to represent the entire dynamic noise waveform, thus ignoring other important features, and their predictions are often more pessimistic than reality.
[0005] Accurate timing estimation is crucial for determining the operating frequency of a circuit. Overly optimistic timing estimates can lead to timing errors during actual operation, while overly pessimistic estimates may restrict the circuit to operating at lower frequencies, wasting its performance. For the reasons described earlier, the impact of power supply noise on timing analysis is becoming increasingly significant. Designers urgently need to accurately measure the influence of dynamic power supply noise on the timing of standard circuit cells to determine a reasonable operating frequency.
[0006] However, to the applicant's knowledge, there is currently no static timing analysis algorithm that can accurately measure the impact of dynamic noise. Designers rely more on their experience to determine a relatively reasonable operating frequency. This underscores the need to develop a timing analysis algorithm that can accurately estimate the impact of dynamic noise.
[0007] In summary, this paper presents a static timing analysis method and apparatus that can detect dynamic power supply noise, which is key to better determine the operating frequency of a chip, ensuring correct timing while maximizing chip performance. Summary of the Invention
[0008] The purpose of this invention is to address the problem that current power supply timing analysis methods cannot accurately measure the impact of dynamic power supply noise on timing, and to provide a static timing analysis method and apparatus that can sense dynamic power supply noise. During static timing analysis, this invention can sense the dynamic noise of the circuit's power supply network and accurately provide the timing prediction results for each standard cell in the circuit under the current noise level.
[0009] A static timing analysis method capable of sensing dynamic power supply noise, the method comprising the following steps:
[0010] Step 1: The rising and falling edges of the dynamic power supply noise are modeled using the cumulative probability distribution function of the deformed Weiber distribution. An edge is modeled by the noise transformation time and the noise shape factor.
[0011] Step 2: Use the time misalignment factor and the noise transition time and noise shape factor used to model the edge to model the dynamic power supply noise. The time misalignment factor represents the time difference between the noise edge start time and the start time of the state flip of the standard cell of the circuit.
[0012] Step 3: Based on SPICE simulation, calculate the time delay and output signal transition time of each basic circuit unit under different conditions. Use the obtained time delay and output signal transition time to generate a dataset for training the neural network. The output signal transition time is the time required for the output signal to rise from a lower amplitude of the peak to a higher amplitude or fall from a higher amplitude of the peak to a lower amplitude. The lower amplitude of the peak ranges from 10% to 30% of the peak value, and the higher amplitude of the peak ranges from 70% to 90% of the peak value.
[0013] Step 4: Construct a multilayer perceptron, whose input is a vector containing the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor of the standard circuit unit. Then, use the dataset generated in Step 3 to train the neural network model.
[0014] Step 5: Use the neural network model trained in Step 4 to predict the delay and output signal transformation time of the standard circuit unit under different dynamic noise, different input conversion time and different output load capacitance to obtain timing analysis results.
[0015] Furthermore, in step 1, taking the rising edge as an example, the original expression using the Weber distribution is:
[0016]
[0017] In the formula, α represents the noise shape factor, β represents another factor of the original Weiber distribution, t represents the time starting from the signal rise, and T(t, α, β) represents the rising edge of the modeled signal.
[0018] The transition time of a noise rising edge is the time required from its starting point to its ending point. The starting and ending points of the rising edge are the moments when the noise amplitude reaches a given percentage of its peak value. Assuming the starting point of the rising edge is when the noise amplitude reaches S% of the peak value, and the ending point is when the noise amplitude reaches E% of the peak value, then the starting point, ending point, and transition time of the noise rising edge can be expressed as follows:
[0019]
[0020]
[0021]
[0022] In the formula, τ represents the noise transformation time, t end and t start These represent the two moments when the signal reaches its peak value S% and E%, respectively.
[0023] Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ yields the rising edge expressed in terms of noise transformation time and noise shape factor:
[0024]
[0025] Furthermore, in step 1, the process of fitting the noise transformation time and the noise shape factor can be transformed into a linear regression problem. Taking the rising edge as an example, after appropriately transforming the rising edge expressed by the noise transformation time and the noise shape factor, we can obtain:
[0026]
[0027] In the formula, T represents the rising edge expressed using noise transformation time and noise shape factor.
[0028] The noise transformation time and noise shape factor are obtained using the least squares method:
[0029] y = a·x + b
[0030] In the formula, y=ln(t), x=ln(-ln(1-f)), T represents the rising edge represented using noise transformation time and noise shape factor.
[0031] Furthermore, in step 1, the original expression of the descent of the noise along the Weiber distribution, fitted using the Weiber distribution, is as follows:
[0032]
[0033] In the formula, α represents the noise shape factor, β represents the scaling parameter of the original Weiber distribution, t represents the time starting from the signal rise, e is a constant, and T′(t, α, β) represents the falling edge of the modeled signal;
[0034] The transition time of the falling edge is the time required from the start of the falling edge to the end of the falling edge. The start and end of the falling edge are the moments when the noise amplitude reaches a given percentage of the peak value. Assuming that the start of the falling edge is when the noise amplitude reaches S′% of the peak value and the end of the falling edge is when the noise amplitude reaches E′% of the peak value, then the start time, end time, and transition time of the falling edge can be expressed as follows:
[0035]
[0036]
[0037]
[0038] In the formula, τ represents the noise transformation time, t′ end and t′ star t represents the two moments when the signal reaches its peak value E′% and S′%, respectively;
[0039] Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ, we obtain the falling edge expressed in terms of noise transformation time and noise shape factor:
[0040]
[0041] Further, in step 1, after deforming the falling edge represented by the noise transformation time and noise shape factor, we obtain:
[0042]
[0043] In the formula, T′ represents the falling edge expressed using noise transformation time and noise shape factor;
[0044] The noise transformation time and noise shape factor are obtained using the least squares method:
[0045] y = a·x + b
[0046] In the formula, y=ln(t), x=ln(-ln(1-T′)),
[0047] Further, step 3 specifically involves: the dataset consists of a vector containing the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor of a standard circuit cell; the dataset is labeled with either the delay or the output signal transition time of the standard circuit cell. In SPICE simulation, the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor are varied within reasonable ranges, and the delay and output signal transition time of the standard circuit cell are measured under different conditions. The delay of the standard circuit cell is the time difference between the output response and the input signal.
[0048] Furthermore, in step 4, the constructed multilayer perceptron has four fully connected layers. After layers 1-3, a batch normalization operation unit and a sigmoid activation layer are sequentially connected. This perceptron is trained using the following loss function:
[0049]
[0050] In the formula, L represents the loss function, B represents the batch size during training, i represents the index of the element in each batch, and P represents the prediction result of a training batch using the output of the neural network. i G represents the prediction result of the neural network for the i-th data in the training batch. i ε represents the label value of the i-th data in the training batch, eps represents a very small positive number to prevent division by zero error, and θ1 and θ2 are hyperparameters.
[0051] The present invention also provides a static timing analysis device for sensing dynamic power supply noise based on a neural network, comprising one or more processors for implementing the above-described static timing analysis method for sensing dynamic power supply noise.
[0052] The present invention also provides a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the above-described static timing analysis method for sensing dynamic power supply noise.
[0053] The beneficial effects of this invention are:
[0054] This invention, based on the cumulative probability distribution function of the Weiber distribution and considering the potential asynchrony between noise and standard cells, rationally models dynamic power supply noise using noise transformation time, noise shape factor, and time misalignment factor. This invention utilizes a trained neural network to accurately estimate the timing performance of each standard cell in the circuit under the influence of power supply noise. For a typical chip circuit, the average relative error of the predicted critical path delay compared to the actual value is 6.43%. This method can accurately measure the impact of dynamic power supply noise on circuit timing, which is of great significance for determining the reasonable operating frequency of the chip, ensuring correct circuit timing, and improving chip performance. Attached Figure Description
[0055] Figure 1 This is a flowchart illustrating the static timing analysis method for sensing dynamic power supply noise according to the present invention.
[0056] Figure 2 This is a comparison chart of the fitting dynamic noise concavity and convexity changes when the noise shape factor is changed in a specific scenario while keeping the noise transformation time constant.
[0057] Figure 3 This is a schematic diagram of the present invention, which uses noise transformation time, noise shape factor and time misalignment factor to fit dynamic noise in a specific scenario.
[0058] Figure 4 This is a schematic diagram of the structure of a multilayer perceptron designed for a specific scenario according to the present invention;
[0059] Figure 5 This invention provides an average relative error distribution diagram for predicting the timing of standard circuit units using a trained neural network model in a specific scenario.
[0060] Figure 6 This is a comparison chart of the prediction of critical path delay of the circuit using a trained neural network in a specific scenario. The comparison objects are the original static timing analysis results, SPICE simulation results, worst process corner static timing simulation results, and the prediction results of this invention without using the time misalignment factor.
[0061] Figure 7 This is a schematic diagram of a static timing analysis device based on a neural network that can sense dynamic power supply noise according to the present invention. Detailed Implementation
[0062] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0063] like Figure 1 As shown, the present invention provides a static timing analysis method for sensing dynamic power supply noise, comprising the following steps:
[0064] Step 1: Model the rising and falling edges of dynamic power supply noise using the cumulative probability distribution function of the deformed Weiper distribution. An edge is modeled by the noise transition time and the noise shape factor. The noise transition time represents the time required for the noise to rise and fall, while the noise shape factor describes the concavity / convexity of the noise edge. Taking the modeling of the rising edge as an example, the rising edge is represented using the original Weiper distribution as follows:
[0065]
[0066] In the formula, α represents the noise shape factor, β represents another factor of the original Weiber distribution, t represents the time starting from the signal rise, and T(t, α, β) represents the rising edge of the modeled signal.
[0067] The transition time of a noise rising edge is the time required from its starting point to its ending point. The starting and ending points of the rising edge are the moments when the noise amplitude reaches a given percentage of its peak value. Assuming the starting point of the rising edge is when the noise amplitude reaches S% of the peak value, and the ending point is when the noise amplitude reaches E% of the peak value, then the starting point, ending point, and transition time of the noise rising edge can be expressed as follows:
[0068]
[0069]
[0070]
[0071] In the formula, τ represents the noise transformation time, t end and t start These represent the two moments when the signal reaches its peak value S% and E%, respectively.
[0072] Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ yields the rising edge expressed in terms of noise transformation time and noise shape factor:
[0073]
[0074] The noise transition time determines the rise or fall time of the noise, while the noise shape factor determines the convexity or concavity of the rise or fall edge. For example... Figure 2As shown, when the noise transformation time is the same, increasing the noise shape factor from 0.1 to 3 will significantly change the convexity of the rising edge shown in the figure.
[0075] The process of fitting the noise transformation time and noise shape factor can be transformed into a linear regression problem. After appropriately transforming the rising edge expressed by the noise transformation time and noise shape factor, we can obtain:
[0076]
[0077] In the formula, T represents the rising edge expressed using noise transformation time and noise shape factor.
[0078] The noise transformation time and noise shape factor are obtained using the least squares method:
[0079] y = a·x + b
[0080] In the formula, y=ln(t), x=ln(-ln(1-T)), T represents the rising edge represented using noise transformation time and noise shape factor.
[0081] Furthermore, in step 1, the original expression of the descent of the noise along the Weiber distribution, fitted using the Weiber distribution, is as follows:
[0082]
[0083] In the formula, α represents the noise shape factor, β represents the scaling parameter of the original Weiber distribution, t represents the time starting from the signal rise, e is a constant, and T′(t, α, β) represents the falling edge of the modeled signal;
[0084] The transition time of the falling edge is the time required from the start of the falling edge to the end of the falling edge. The start and end of the falling edge are the moments when the noise amplitude reaches a given percentage of the peak value. Assuming that the start of the falling edge is when the noise amplitude reaches S′% of the peak value and the end of the falling edge is when the noise amplitude reaches E′% of the peak value, then the start time, end time, and transition time of the falling edge can be expressed as follows:
[0085]
[0086]
[0087]
[0088] In the formula, τ represents the noise transformation time, t′ end and t′ start These represent the two moments when the signal reaches its peak value E′% and S′%, respectively.
[0089] Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ, we obtain the falling edge expressed in terms of noise transformation time and noise shape factor:
[0090]
[0091] Further, in step 1, after deforming the falling edge represented by the noise transformation time and noise shape factor, we obtain:
[0092]
[0093] In the formula, T′ represents the falling edge expressed using noise transformation time and noise shape factor;
[0094] The noise transformation time and noise shape factor are obtained using the least squares method:
[0095] y = a·x + b
[0096] In the formula, y=ln(t), x=ln(-ln(1-f′)),
[0097] Step 2: Dynamic power supply noise is modeled using a time misalignment factor, noise transition time used to model the edge, and noise shape factor. The time misalignment factor represents the time difference between the noise edge start time and the start time of the state transition of the standard circuit cell. When there is a time misalignment between the power grid noise and the transition of the standard circuit cell, the impact of noise on the timing of the standard cell is very complex, varying depending on the type of standard cell and often nonlinear. Therefore, this invention introduces a time misalignment factor and uses a neural network to fit this impact cell by cell. Dynamic power supply noise is thus modeled by noise transition time, noise shape factor, and time misalignment factor, such as... Figure 3 As shown.
[0098] Step 3: Based on SPICE simulation, calculate the time delay and output signal transition time of each basic circuit unit under different conditions, thereby generating a dataset for training the neural network. The dataset consists of vectors containing the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor of the standard circuit unit. The dataset is labeled with either the time delay or the output signal transition time of the standard circuit unit. In the SPICE simulation, the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor are varied within reasonable ranges. The time difference between when the input signal transitions to 50% of the power supply voltage and when the output signal transitions to 50% is measured as the time delay. The time difference between when the output signal reaches 10% (90%) of the power supply voltage and when it reaches 90% (10%) of the power supply voltage is measured as the transition time of the output signal as the rising edge (falling edge). Generally, the input signal transition time and output load capacitance range are determined by the library files provided by the foundry; the noise transition time range can be determined to be between 10ps and 1ns to cover high-frequency noise from 1GHz to hundreds of GHz; the noise shape factor range can be determined to be between 0.1 and 3, which is sufficient to cover most edges; the timing misalignment factor range can be determined to be between -0.5ns and 2ns, and the impact of noise outside this range on the timing of standard cells is negligible.
[0099] Step 4: Construct a multilayer perceptron. Its input is a vector containing the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor of a standard circuit unit. The neural network is trained using the dataset generated in Step 3. The constructed multilayer perceptron has four fully connected layers. Layers 1-3 are followed by a batch normalization operation unit and a sigmoid activation layer. The perceptron is trained using the following loss function:
[0100]
[0101] In the formula, L represents the loss function, B represents the batch size during training, i represents the index of the element in each batch, and P represents the prediction result of a training batch using the output of the neural network. i G represents the prediction result of the neural network for the i-th data in the training batch. i ε represents the label value of the i-th data in the training batch, eps represents a small positive number to prevent division by zero errors, and θ1 and θ2 are hyperparameters. A typical neural network structure is as follows: Figure 4 As shown.
[0102] Step 5: Using the neural network model trained in Step 4, predict the time delay and output signal transformation time of the standard circuit cell under different dynamic noise, different input transition times, and different output load capacitances to obtain timing analysis results. The average relative error distribution of the neural network for the timing prediction of a single standard cell is as follows: Figure 5 As shown, the average error of the predictions for all standard cells is 4.95%, and more than 75% of the model predictions have an average error of less than 6% compared to the actual values. Using a neural network model instead of the lookup table in the original static time series analysis enables the perception of power supply noise. Figure 6 This paper compares the critical path delay calculation results on the ISPD2012 benchmark dataset (a dataset of a reference circuit) using the original static timing analysis, worst-case process corner static timing analysis, the present invention, SPICE, and the present invention without using a timing misalignment factor. SPICE results can be considered as realistic; the original static analysis, because it does not consider the influence of power supply noise, may cause timing misalignments; the results of worst-case process corner timing analysis and the present invention without using a timing misalignment factor are too pessimistic and will limit the chip's operating frequency; while the method proposed in this invention is closest to reality, with an average error of 6.43%. This invention can accurately estimate the actual timing performance of a circuit under power supply noise conditions, which is of great significance for determining a reasonable operating frequency for the chip, ensuring correct circuit timing, and improving chip performance.
[0103] Corresponding to the aforementioned embodiments of the static timing analysis method for sensing dynamic power supply noise, the present invention also provides an embodiment of a static timing analysis device for sensing dynamic power supply noise based on a neural network.
[0104] See Figure 7 The present invention provides a static timing analysis device for sensing dynamic power supply noise based on a neural network, comprising one or more processors for implementing the static timing analysis method for sensing dynamic power supply noise in the above embodiments.
[0105] An embodiment of the present invention, a static timing analysis device based on a neural network capable of sensing dynamic power supply noise, can be applied to any device with data processing capabilities, such as a computer. The device embodiment can be implemented in software, hardware, or a combination of both. Taking software implementation as an example, as a logical device, it is formed by the processor of any data processing device loading the corresponding computer program instructions from non-volatile memory into memory for execution. From a hardware perspective, such as... Figure 7The diagram shown is a hardware structure diagram of any device with data processing capabilities, in which the present invention, a static timing analysis device based on a neural network capable of sensing dynamic power supply noise, is located. (Except for...) Figure 7 In addition to the processor, memory, network interface, and non-volatile memory shown, any data processing device in the embodiment may also include other hardware depending on the actual function of the data processing device, which will not be described in detail here.
[0106] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.
[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method of static timing analysis that is aware of dynamic power noise, characterized in that, The method includes the following steps: Step 1: Model the rising and falling edges of dynamic power supply noise using the cumulative probability distribution function of the deformed Weiber distribution; The original expression of the rising edge Weibull distribution for fitting noise using the Weibull distribution is as follows: In the formula, α represents the noise shape factor, β represents the scaling parameter of the original Weiber distribution, t represents the time starting from the signal rise, e is a constant, and T(t,α,β) represents the rising edge of the modeled signal. The transition time of a noise rising edge is the time required from the start of the rising edge to the end of the rising edge. The start and end of the rising edge are the moments when the noise amplitude reaches a given percentage of the peak value. Assuming that the start of the rising edge is when the noise amplitude reaches S% of the peak value and the end of the rising edge is when the noise amplitude reaches E% of the peak value, then the start time, end time, and transition time of the noise rising edge are expressed as follows: where τ represents the noise transform time, t end and t start represent the two times at which the signal reaches the peaks S% and E%, respectively. Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ yields the rising edge expressed in terms of noise transformation time and noise shape factor: Step 2: Dynamic power supply noise is modeled using a time misalignment factor, noise transition time used to model the edge, and noise shape factor. The time misalignment factor represents the time difference between the noise edge start time and the start time of the state transition of the standard circuit cell. Step 3: Based on SPICE simulation, calculate the time delay and output signal transition time of each basic circuit unit under different conditions. Use the obtained time delay and output signal transition time to generate a dataset for training the neural network. The output signal transition time is the time difference between the output signal reaching 10% of the power supply voltage and reaching 90% of the power supply voltage, or the time difference between reaching 90% of the power supply voltage and reaching 10% of the power supply voltage. Step 4: Construct a multilayer perceptron, whose input is a vector containing the input signal transformation time, output load capacitance, noise transformation time, noise shape factor, and time misalignment factor of the standard circuit unit, and use the dataset generated in Step 3 to train the neural network model. Step 5: Use the neural network model trained in Step 4 to predict the delay and output signal transformation time of the standard circuit unit under different dynamic noise, different input conversion time and different output load capacitance to obtain timing analysis results.
2. The method of claim 1, wherein, In step 1, the rising edge, represented by the noise transformation time and noise shape factor, is transformed to obtain: In the formula, T represents the rising edge expressed using noise transformation time and noise shape factor; The noise transformation time and noise shape factor are obtained using the least squares method: In the formulae, , , .
3. The method of claim 1, wherein, In step 1, the original expression of the descent path of the noise, fitted using a Weiper distribution, is as follows: In the formula, denotes the modeled signal falling edge; The transition time of the falling edge of noise is the time required from the start to the end of the falling edge. The start and end of the falling edge are the moments when the noise amplitude reaches a given proportion of its peak value. Assume that when the noise amplitude reaches the noise peak value S... ' The moment % marks the start of the falling edge, and the noise amplitude reaches the noise peak value E. ' If the time % is the end of the falling edge, then the start time of the noise falling edge, the end time of the noise falling edge, and the noise transition time are expressed as follows: In the formula, and These represent the signal reaching its peak value E. ' % and S ' % at two moments; Replacing the scaling parameter β of the original Weiber distribution with the noise transformation time τ, we obtain the falling edge expressed in terms of noise transformation time and noise shape factor: 。 4. The static timing analysis method of claim 3, wherein, In step 1, the falling edge, represented by the noise transformation time and noise shape factor, is deformed to obtain: In the formula, T ' indicates a falling edge expressed using a noise transform time and a noise shape factor; The noise transformation time and noise shape factor are obtained using the least squares method: In the formulae, , , .
5. The method of claim 1, wherein, In step 3, the dataset consists of a vector containing the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor of the standard circuit unit. The dataset is labeled with either the delay of the standard circuit unit or the output signal transition time. In the SPICE simulation, the input signal transition time, output load capacitance, noise transition time, noise shape factor, and time misalignment factor are changed respectively, and the delay of the standard circuit unit and the output signal transition time are measured under different conditions. The delay of the standard circuit unit is the time difference between the output response and the input signal.
6. The method of claim 1, wherein In step 4, the constructed multilayer perceptron has four fully connected layers. Layers 1-3 are followed by a batch normalization unit and a sigmoid activation layer. The perceptron is trained using the following loss function: In the formula, L represents the loss function, B represents the batch size during training, i represents the index of the element in each batch, and P represents the prediction result of a training batch using the output of the neural network. i G represents the prediction result of the neural network for the i-th data in the training batch. i eps represents the label value of the i-th data in the training batch, eps represents a positive number used to prevent division by zero errors, and θ1 and θ2 are hyperparameters.
7. An apparatus for static timing analysis of perceivable dynamic power noise based on neural networks, the apparatus comprising: a neural network configured to receive a plurality of input signals and to generate a plurality of output signals; and a perceptron configured to receive the plurality of output signals and to generate a perceptron output signal. It includes one or more processors for implementing the static timing analysis method for perceptible dynamic power supply noise as described in any one of claims 1-6.
8. A computer-readable storage medium, characterized in that, It stores a program that, when executed by a processor, implements the static timing analysis method for perceptible dynamic power supply noise as described in any one of claims 1-6.