A power network cabling method
By using high-level metal layers, transition layers, and stacked vias for routing, the resource shortage problem caused by the cross-laying of low-level metal lines in traditional power networks is solved, achieving resource conservation and reduced design complexity in power networks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INFOTM MICROELECTRONICS
- Filing Date
- 2022-12-16
- Publication Date
- 2026-07-21
AI Technical Summary
In traditional power network cabling, the cross-laying of low-level metal wires leads to a shortage of clock and signal resources, increasing the difficulty of integrated circuit design.
The routing method employs high-level metal layers, transition layers, and stacked vias. By eliminating unnecessary vertical and horizontal metal lines and using stacked vias to connect hardware unit areas with vertical metal lines, the cross-layout of low-level metal lines is reduced.
While meeting voltage drop requirements, this approach saves wiring resources, reduces design complexity, and allows for more space for clock and signal line routing.
Smart Images
Figure CN116050343B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to integrated circuit design, and more particularly to a power network routing method. Background Technology
[0002] With the continuous advancement of integrated circuit technology, the physical design of ICs can become increasingly complex. However, correspondingly, the physical size of various units (such as standard units and hard macros) in integrated circuits is getting smaller and smaller, and their pin density is getting larger and larger. Meanwhile, the density of low-level metal lines in traditional power networks, which are metal lines that must be used by both standard hardware units and power networks, is also getting higher and higher. This leads to increasingly tight wiring resources at low-level metal lines, which greatly increases the difficulty of integrated circuit design.
[0003] Traditional power network cabling uses a large number of low-layer metal wires to cross and lay flat to form the power network, which is more likely to cause clock and signal resource shortages. Summary of the Invention
[0004] In view of the problem that current power network routing methods in integrated circuits cause clock and signal resource shortages due to the use of a large number of low-level metal wires to cross and lay out the power network, this invention provides a power network routing method that can save power network routing resources.
[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:
[0006] A power network cabling method, comprising:
[0007] A high-level metal layer is laid out; the high-level metal layer includes several high-level metal lines arranged parallel to each other along a first direction; the high-level metal lines are grouped in pairs, and each group includes a main power line and a main ground line;
[0008] A transition layer is provided; the transition layer includes a transverse metal transition layer and a longitudinal metal transition layer;
[0009] Deploy the hardware unit area; set up stacked vias between the hardware unit area and the transition layer;
[0010] The transition layer of the hardware unit area and its surrounding narrowband area is redeployed.
[0011] The transverse metal transition layer is arranged along a second direction; the longitudinal metal transition layer is arranged along a first direction; the transverse metal transition layer includes a plurality of parallel transverse metal lines, the transverse metal lines are grouped in pairs, each group including a first power line and a first ground line; the longitudinal metal transition layer includes a plurality of parallel longitudinal metal lines, the longitudinal metal lines are grouped in pairs, each group including a second power line and a second ground line.
[0012] The transition layer of the hardware unit area and its surrounding narrowband area is redeployed, including:
[0013] Delete the vertical metal lines in the hardware unit area and redefine them so that the hardware unit area contains at least one set of vertical metal lines. The hardware unit is usually a hard macro unit, and its pin size is thicker than that of ordinary metal lines. Therefore, deleting the vertical metal lines in this area and redefining them serves two purposes: first, to match the pin size of the hard macro unit; and second, to avoid the vertical metal lines appearing on the boundary of the hard macro unit area, which would cause the power lines and ground lines inside the area to be mispaired.
[0014] Remove the horizontal metal lines in the narrow band area around the hardware unit and rearrange them; the narrow band area around the hard macro unit area usually needs to be filled with pairs of horizontal metal lines if space allows, so remove the horizontal metal lines that do not meet the requirements and rearrange the horizontal metal lines in the narrow band area around the hard macro unit area.
[0015] It also includes a low-level metal line; the low-level metal line is filled between the longitudinal metal line and the hardware unit area; filling the low-level metal line can be used to improve the voltage drop of the power network so that the voltage drop of the power network can meet the design requirements.
[0016] The stacked vias are located at the overlap points of the hardware unit area pins and the longitudinal metal lines, and are composed of several sub-vias stacked sequentially. Using stacked vias to connect the hardware unit area pins and the longitudinal metal lines, instead of the traditional layer-by-layer metal lines, can reduce space occupation, save wiring resources, and leave more space for the subsequent clock and signal line routing.
[0017] The sub-via includes a via body, a conductive filler, and a low-layer metal block.
[0018] Connecting through holes are provided at the stacking points between the high-level metal wire and the horizontal metal wire, and between the horizontal metal wire and the vertical metal wire; the structure of the connecting through holes is the same as that of the sub-through holes.
[0019] The first direction is perpendicular to the second direction.
[0020] A dielectric layer is disposed between the high-layer metal lines, the horizontal metal lines, and the vertical metal lines; the dielectric layer serves as insulation and support, and the stacked vias and connecting vias are all disposed in the dielectric layer.
[0021] Advantages of implementing this invention:
[0022] By using stacked vias to replace the large number of cross-laid low-level metal wires in traditional wiring methods, these stacked vias are composed of sequentially stacked sub-vias. This effectively saves wiring resources while meeting voltage drop requirements, leaving enough space for clock and signal lines and reducing design complexity. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a partial structural diagram of a power network in the prior art;
[0025] Figure 2 This is a partial structural diagram of the power network described in an embodiment of the present invention;
[0026] Figure 3 This is a schematic diagram of the sub-through hole structure according to an embodiment of the present invention;
[0027] Figure 4 A partial structural diagram of the power network before the transition layer is re-laid out;
[0028] Figure 5 A partial structural diagram of the power network after the transition layer has been reconfigured.
[0029] Figure 6 This is a schematic diagram comparing the voltage drop of the power network described in this invention with that of existing power networks.
[0030] Legend: 1. High-layer metal line; 2. Horizontal metal line; 21. First power line; 22. First ground line; 3. Vertical metal line; 31. Second power line; 32. Second ground line; 4. Dielectric layer; 5. Sub-via; 51. Via body; 52. Conductive filler; 53. Low-layer metal block; 6. Connecting via; 7. Unit pin Detailed Implementation
[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] like Figure 1 As shown, it illustrates a portion of the power network structure in a traditional cabling method. Figure 1In this diagram, 'a' represents a high-layer metal line, 'b' and 'c' represent transition layer metal lines, 'd' represents a low-layer metal line used to connect the transition layer metal line to the hardware unit represented by 'e', 'f' represents the dielectric layer between each metal line, and 'g' represents a via located between the stack-up points of two adjacent metal lines, used to connect the two metal lines. Figure 1 As can be seen, in traditional wiring methods, multiple layers of low-level metal lines are laid between the transition layer metal lines and the hardware units (the low-level metal lines are laid out in a cross pattern and connected through vias at the stack-up points). With the advancement of technology, the density of hardware units is increasing, which means that the gap between pins is getting smaller and smaller. Correspondingly, the low-level metal lines need to be laid out more and more densely, resulting in a shortage of wiring resources, which is not conducive to the laying of clock and signal lines and increases the overall design difficulty.
[0033] like Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, a power network cabling method includes:
[0034] A high-level metal layer is laid out; the high-level metal layer includes a plurality of high-level metal lines 1 arranged parallel to each other along a first direction; the high-level metal lines 1 are grouped in pairs, and each group includes a main power line and a main ground line;
[0035] A transition layer is provided; the transition layer includes a transverse metal transition layer and a longitudinal metal transition layer;
[0036] A hardware unit area is provided, which represents the area used to place hardware units, including but not limited to standard units and hard macro units; stacking vias are provided between the hardware unit area and the transition layer.
[0037] The transition layer of the hardware unit area and its surrounding narrowband area is redeployed.
[0038] The transverse metal transition layer is arranged along the second direction; the longitudinal metal transition layer is arranged along the first direction; the transverse metal transition layer includes a plurality of parallel transverse metal lines 2, the transverse metal lines 2 are grouped in pairs, each group including a first power line 21 and a first ground line 22; the longitudinal metal transition layer includes a plurality of parallel longitudinal metal lines 3, the longitudinal metal lines 3 are grouped in pairs, each group including a second power line 31 and a second ground line 32.
[0039] The transition layer of the hardware unit area and its surrounding narrowband area is redeployed, including:
[0040] Delete the vertical metal lines 3 in the hardware unit area and redefine them so that the hardware unit area contains at least one set of vertical metal lines 3. The hardware unit is usually a hard macro unit, and its pin size is thicker than that of ordinary metal lines. Therefore, deleting the vertical metal lines 3 in this area and redefining them serves two purposes: first, to match the pin size of the hard macro unit; and second, to avoid the vertical metal lines 3 appearing on the boundary of the hard macro unit area, which would cause the power lines and ground lines inside the area to be mispaired.
[0041] Delete the horizontal metal lines 2 in the narrow band area around the hardware unit and rearrange them; the narrow band area around the hard macro unit area usually needs to be filled with pairs of horizontal metal lines 2 if space allows. Therefore, delete the horizontal metal lines 2 that do not meet the requirements and rearrange the horizontal metal lines 2 in the narrow band area around the hard macro unit area. Try to lay pairs of horizontal metal lines 2 in the narrow band area to power other smaller hardware units such as standard units. This can also improve the voltage drop degradation to some extent (the power network design method described in this invention reduces the number of low-level metal layers that are cross-laid out compared to traditional power networks, so the overall voltage drop of the power network will inevitably degrade).
[0042] like Figure 4 The diagram shows a schematic of the transition layer before the hardware unit area and surrounding narrow band area are rearranged. The horizontal metal lines 2 and vertical metal lines 3 are uniformly and regularly arranged. However, due to the varying sizes of hardware units such as macrocells, their arrangement is not uniform or regular, and the metal lines have a certain width. Figure 4 It can be seen that some horizontal metal lines 2 and vertical metal lines 3 fall at the edges of the hardware unit area, making this section of metal line difficult to utilize. There are no complete pairs of power lines and ground lines between large hardware unit areas, and sometimes there are no paired power lines and ground lines inside the hardware unit area either; for example... Figure 5 The diagram shows that after deleting some of the horizontal metal lines 2 or vertical metal lines 3, they are redistributed according to the location distribution of the hardware unit area to meet the design requirements. The deletion mentioned here is limited to the design stage and is a modification of the power network design drawing, which does not involve the manufacturing process.
[0043] To mitigate the degradation of power network voltage drop caused by replacing cross-laid low-layer metal layers with stacked vias, low-layer metal lines can be filled between the vertical metal line 3 and the hardware unit area. Filling with low-layer metal lines can improve the voltage drop of the power network, ensuring that the power network voltage drop meets design requirements.
[0044] like Figure 6The figure shows a comparison of the voltage drop and low-layer metal occupancy of the power network of the wiring method of the present invention and the traditional power network using cross-layered low-layer metal lines. It can be seen from the figure that the voltage drop of the present invention is slightly worse than that of the traditional power network, but it can still meet the design requirements. Under the condition of meeting the voltage drop, the low-layer metal of the power network of the present invention.
[0045] The stacked vias are located at the overlap points of the hardware unit area pins and the vertical metal lines 3, and are composed of several sub-vias 5 stacked sequentially. Using stacked vias to connect the hardware unit area pins and the vertical metal lines 3, instead of the traditional layer-by-layer metal wiring, reduces space occupation, saves wiring resources, and leaves more space for subsequent clock and signal line routing, effectively reducing design complexity. Figure 2 The number 7 indicates pin 7 of the hardware unit.
[0046] The sub-via 5 includes a via body 51, a conductive filler 52, and a low-layer metal block 53. The low-layer metal block 53 can be regarded as a small part of the low-layer metal wire in the traditional wiring method. Therefore, the power network designed using this method does not require major changes to the equipment or process in the actual manufacturing process, thus avoiding unnecessary costs.
[0047] A connecting through hole 6 is provided at the stacking point between the high-level metal line 1 and the horizontal metal line 2, and between the horizontal metal line 2 and the vertical metal line 3; the structure of the connecting through hole 6 is the same as that of the sub-through hole 5.
[0048] The first direction is perpendicular to the second direction.
[0049] A dielectric layer 4 is provided between the high-layer metal line 1, the horizontal metal line 2, and the vertical metal line 3; the dielectric layer 4 serves as insulation and support, and the stacked through-holes and the connecting through-holes 6 are both provided in the dielectric layer 4.
[0050] The connecting through hole 6 is filled with conductive filler 52, which can connect the metal wires located at both ends of the connecting through hole 6 to achieve electrical connection between them. The opening of the connecting through hole 6 also needs to follow certain principles, that is, through holes are set between the stacking points of power lines and between the stacking points of ground lines. Four stacking points will be generated between the two sets of metal wires (high-layer metal wire 1 and horizontal metal wire 2, horizontal metal wire 2 and vertical metal wire 3) located in adjacent layers, which are respectively laid along the first direction and the second direction. The connecting through hole 6 can only be set at the diagonal and cannot be set on the adjacent side to avoid short circuit.
[0051] Advantages of implementing this invention:
[0052] By using stacked vias to replace the large number of cross-laid low-level metal wires in traditional wiring methods, these stacked vias are composed of sequentially stacked sub-vias. This effectively saves wiring resources while meeting voltage drop requirements, leaving enough space for clock and signal lines and reducing design complexity.
[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A power network cabling method, characterized in that, include: A high-level metal layer is laid out; the high-level metal layer includes several high-level metal lines arranged parallel to each other along a first direction; the high-level metal lines are grouped in pairs, and each group includes a main power line and a main ground line; A transition layer is provided; the transition layer includes a transverse metal transition layer and a longitudinal metal transition layer; the transverse metal transition layer is provided along a second direction; the longitudinal metal transition layer is provided along a first direction; the transverse metal transition layer includes a plurality of parallel transverse metal lines, the transverse metal lines are grouped in pairs, each group including a first power line and a first ground line; the longitudinal metal transition layer includes a plurality of parallel longitudinal metal lines, the longitudinal metal lines are grouped in pairs, each group including a second power line and a second ground line; A hardware unit area is laid out; stacked vias are provided between the hardware unit area and the transition layer; the stacked vias are located at the stacking points of the hardware unit area pins and the longitudinal metal lines, and are formed by stacking several sub-vias in sequence. The transition layer of the hardware unit area and its surrounding narrow band area is re-laid out; the vertical metal lines in the hardware unit area are deleted and re-laid out, so that the hardware unit area contains at least one set of vertical metal lines; the horizontal metal lines in the narrow band area surrounding the hardware unit are deleted and re-laid out.
2. The power network cabling method according to claim 1, characterized in that, It also includes a low-level metal line; the low-level metal line fills the space between the longitudinal metal line and the hardware unit area.
3. The power network cabling method according to claim 1, characterized in that, The sub-via includes a via body, a conductive filler, and a low-layer metal block.
4. The power network cabling method according to claim 1, characterized in that, Connecting through holes are provided at the overlapping points between the high-level metal wire and the horizontal metal wire, and between the horizontal metal wire and the vertical metal wire.
5. The power network cabling method according to claim 1, characterized in that, The first direction is perpendicular to the second direction.
6. The power network cabling method according to claim 1, characterized in that, A dielectric layer is disposed between the high-layer metal lines, the horizontal metal lines, and the vertical metal lines.