Memory, data processing method and chip

Abstract

The embodiment of the present application provides a memory, a data processing method and a chip, wherein the memory comprises: a storage array, used for storing data written into the storage array; an input / output circuit, used for writing data into the storage array or reading data from the storage array, wherein when the data is written into the storage array, the data to be written is latched; a control circuit, used for comparing a read address of the data to be read with a write address of the data to be written when the input / output circuit reads data from the storage array, and if the read address is consistent with the write address, controlling the input / output circuit to output the latched data to be written as the read data; the memory provided by the embodiment of the present application does not need to prohibit two continuous clock cycles to write and then read the same address, so that the access algorithm of the system is not affected.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit technology, specifically to a memory, a data processing method, and a chip. Background Technology

[0002] Memory is a storage component used to store programs and various data. During operation, it is generally necessary to prevent two consecutive cycles (clock cycles) from writing to the same address before reading it, as this would affect the system's access algorithm and thus limit its usage scenarios.

[0003] Therefore, how to improve the structure of the memory and avoid it affecting the system's access algorithm is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a memory, a data processing method, and a chip to improve the structure of the memory and avoid affecting the system's access algorithm.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] An embodiment of the present invention provides a memory, comprising:

[0007] A storage array for storing data written to the storage array;

[0008] An input / output circuit is used to write data to or read data from the storage array, wherein when writing data to the storage array, the data to be written is latched.

[0009] A control circuit is used to compare the read address of the data to be read with the write address of the data to be written when the input / output circuit reads data from the storage array. If they match, the control circuit outputs the latched data to be written as the read data.

[0010] The read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

[0011] Optionally, the input / output circuit is further configured to latch the write address when writing data to the storage array; and to latch the read address when reading data from the storage array.

[0012] The control circuit includes an XOR unit, which is used to perform an XOR comparison between the latched read address and the latched write address, and output the corresponding result signal.

[0013] Optionally, the input / output circuit further includes a multiplexer, used to select the latched data to be written as the read data output when the result signal in the control circuit indicates that the read address and the write address are consistent.

[0014] Optionally, the input / output circuit further includes a multiplexer, used to select the data at the corresponding read address in the storage array as the read data output when the result signal in the control circuit indicates that the read address and the write address are inconsistent.

[0015] Optionally, the storage array includes multiple storage cells arranged in an array, and the input / output circuit includes a latch, a multiplexer, and a readout trigger.

[0016] The latch's input terminal is used to input external input data, its output terminal is connected to one input terminal of the multiplexer, and its clock signal terminal is connected to the write operation clock signal.

[0017] The other input of the multiplexer is connected to one of the storage cells in the storage array, and the control terminal is connected to the control circuit to receive the result signal from the control circuit.

[0018] The input terminal of the readout trigger is connected to the output terminal of the multiplexer, the output terminal is used to output the readout data, and the clock signal terminal is connected to the read operation clock signal.

[0019] Optionally, the control circuit is further configured to control the read word line signal to be low when the read address and the write address are the same.

[0020] Optionally, the control circuit further includes a read signal control unit, which is used to update the read operation clock signal based on the comparison result between the read address and the write address; wherein, when the read address and the write address are the same, the read operation clock signal is updated to a low level.

[0021] Optionally, the read signal control unit is a first AND operator, used to perform an AND operation on the comparison result of the read address and the write address, and the read operation clock signal, and output the result signal of the AND operation as the read operation clock update signal.

[0022] The memory also includes a read word line driving circuit, which is used to output a read word line signal based on the read operation clock update signal.

[0023] This invention also provides a data processing method, the method comprising:

[0024] When writing data to the storage array, the data to be written is latched;

[0025] When reading data from the storage array, the read address of the data to be read is compared with the write address of the data to be written. If they match, the latched data to be written is used as the read data.

[0026] The read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

[0027] This invention also provides a chip, which includes the memory provided in this invention.

[0028] This invention provides a memory, a data processing method, and a chip. The memory includes: a memory array for storing data written to the memory array; an input / output circuit for writing data to or reading data from the memory array, wherein when writing data to the memory array, the data to be written is latched; and a control circuit for comparing the read address of the data to be read with the write address of the data to be written when the input / output circuit reads data from the memory array. If they match, the control circuit outputs the latched data to be written as the read data. The read address indicates the location of the data to be read in the memory array, and the write address indicates the location of the data to be written in the memory array.

[0029] As can be seen, when the input / output circuit writes data to the storage array, it latches the data to be written. When reading data, the control circuit compares the read address of the data to be read with the write address of the data to be written. If they match, the control circuit outputs the latched data to be written as the read data. It is understood that the data to be written is essentially the latest data corresponding to its address. Reading the latched data ensures that the latest data is always read, regardless of when the data is read, preventing errors in the read operation due to insufficient write operation time. Furthermore, the memory provided in this embodiment does not need to prohibit two consecutive clock cycles from writing to the same address before reading, thus not affecting the system's access algorithm. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a memory structure diagram;

[0032] Figure 2 To and Figure 1 The runtime sequence diagram corresponding to the memory;

[0033] Figure 3 An optional block diagram of a memory provided in an embodiment of the present invention;

[0034] Figure 4 An optional circuit structure diagram of a memory provided in an embodiment of the present invention;

[0035] Figure 5 This is a runtime sequence diagram of the memory signals provided in an embodiment of the present invention;

[0036] Figure 6 An optional flowchart of a data processing method provided in an embodiment of the present invention;

[0037] Figure 7 Another optional flowchart of a data processing method provided in an embodiment of the present invention;

[0038] Figure 8 An optional flowchart for step S18 provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] As described in the background section, during memory operation, it is typically necessary to prevent two consecutive cycles (clock cycles) from writing to the same address before reading from it. The inventors, through analysis, discovered the following reason for this phenomenon:

[0041] Among them, SRAM (Static Random-Access Memory) is used as an example of memory, refer to... Figure 1 A memory structure diagram is shown. Figure 2 The shown and Figure 1 Runtime sequence diagram corresponding to the memory. (Reference) Figure 1 The memory includes a storage array, a word line decoder, a control circuit, and input / output circuits. The control circuit receives the clock signal CLK, the read address Rd_Addr, and the write address Wr_Addr, while the word line decoder decodes the corresponding read word line signal RWL. and the WWL signal The data is then sent to the storage array, thereby outputting the read data Q from the input / output circuit based on the read word line signal. Alternatively, based on the write word line signal, external input data D can be written from the input / output circuit. During one read / write clock cycle of the memory, a high level of CLK is used for read operations, and a low level of CLK is used for write operations.

[0042] by Figure 2 Taking the example of an address being selected for a write operation in the first CLK cycle (marked as cycle1 in the diagram) and the same address being read in the second CLK cycle (marked as cycle2 in the diagram), during the low-level phase of the first CLK cycle, the write word line signal WWL corresponding to the selected address... (Taking i=0 as an example in the diagram) When pulse is enabled, during the high-level phase of the second CLK cycle, the read word line signal RWL corresponding to this address... (The pulse is activated when i=0 in the diagram.)

[0043] The inventors discovered that wordline boosting technology is widely used to ensure the write capability of memory under low voltage. However, this technology can cause the write word line signal (WWL) to be lost. The pulse width has been extended, thus exceeding half a cycle of CLK, meaning that WWL... The pulse will extend into the next CLK cycle, cycle 2. At this point, if a read operation is performed on the memory cell corresponding to that address, it will cause the read word line signal RWL at that address to be interrupted. pulse and write line signal WWL The pulses partially overlap, such as Figure 2 As shown in the shaded area.

[0044] Understandably, if it were before the overlap, that is... Figure 2 During the "t1" time period shown, the memory cell corresponding to the address has already been written with new data. Therefore, the data read from that address in cycle2 is the newly written data (i.e., the data written during the low-level phase of cycle1). If the memory cell has not completed the write operation of new data before the overlap, i.e. during the t1 time period, then the data read from that address in cycle2 may still be the old data in the memory cell.

[0045] Clearly, performing a write operation followed by a read operation on the same address in two consecutive clock cycles can easily lead to inaccurate data reads. Therefore, in memory operation procedures, performing a write operation followed by a read operation on the same address in two consecutive clock cycles is not permitted.

[0046] Based on this, embodiments of the present invention provide a memory, a data processing method, and a chip. The memory includes: a memory array for storing data written to the memory array; an input / output circuit for writing data to or reading data from the memory array, wherein, when writing data to the memory array, the data to be written is latched; and a control circuit for comparing the read address of the data to be read with the write address of the data to be written when the input / output circuit reads data from the memory array. If they match, the control circuit outputs the latched data to be written as the read data. The read address indicates the location of the data to be read in the memory array, and the write address indicates the location of the data to be written in the memory array.

[0047] As can be seen, when the input / output circuit writes data to the storage array, it latches the data to be written. When reading data, the control circuit compares the read address of the data to be read with the write address of the data to be written. If they match, the control circuit outputs the latched data to be written as the read data. It is understood that the data to be written is essentially the latest data corresponding to its address. Reading the latched data ensures that the latest data is always read, regardless of when the data is read, preventing errors in the read operation due to insufficient write operation time. Furthermore, the memory provided in this embodiment does not need to prohibit two consecutive clock cycles from writing to the same address before reading, thus not affecting the system's access algorithm.

[0048] Optional, Figure 3 An optional block diagram of a memory provided in an embodiment of the present invention is shown, such as... Figure 3 As shown, the memory may include:

[0049] A storage array 200 is used to store data written to the storage array; an input / output circuit 210 is used to write data to or read data from the storage array, wherein, when writing data to the storage array 200, the data to be written is latched; a control circuit 220 is used to compare the read address of the data to be read with the write address of the data to be written when the input / output circuit 210 reads data from the storage array, and if they match, control the input / output circuit 210 to output the latched data to be written as the read data; wherein, the read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

[0050] The storage array 200 may include multiple storage cells arranged in an array according to a preset rule. These storage cells may be, for example, SRAM storage cells, specifically 6TB or 8TB SRAM storage cells; correspondingly, the storage array 200 may be an SRAM storage array. It is understood that in the storage array, each storage cell corresponds to a location. During memory operation, each storage cell can be configured with location information, i.e., an address. Based on this address, the location of the storage cell can be determined, thus identifying the corresponding storage cell based on the specific location information. For example, when writing data to a storage cell, the data can be written to the storage cell based on the location indicated by the address corresponding to that storage cell.

[0051] In this embodiment of the invention, the read address indicates the location of the data to be read in the storage array, and the write address indicates the location of the data to be written in the storage array.

[0052] The input / output circuit 210 outputs the data to be read from the read address based on the read instruction signal, and writes the data to be written to the write address based on the write instruction signal. In this embodiment of the invention, by latching the data to be written when writing data to the memory array, the data to be written currently being processed is temporarily saved so that when a read instruction corresponding to the write address is received later, the data to be written is output as the read data, thus avoiding errors in the read operation that may occur due to insufficient write operation time during continuous write-then-read operations.

[0053] It should be noted that when the input / output circuit 210 latches the data to be written, the latching time can be long or short. However, the latching time should be at least greater than or equal to the time it takes for the memory to complete one data write operation. Furthermore, the input / output circuit 210 can continuously update the latched data based on the instruction signals in the instruction stream. That is, the input / output circuit only latches the data to be written corresponding to the current write instruction signal. Upon receiving the next write instruction signal, it uses the received write instruction signal as the current write instruction signal and latches the data to be written corresponding to the current write instruction signal.

[0054] The control circuit 220 compares the read address of the data to be read with the write address of the data to be written to determine whether the data to be read is the data to be written corresponding to the previous write instruction signal. When the read address and the write address are consistent, the control input / output circuit 210 outputs the latched data to be written as the read data, thereby realizing continuous write-then-read operations and avoiding errors in the read operation that may be caused by insufficient write operation time.

[0055] The write address and the read address can be obtained through various means, such as the input / output circuit 210 or the corresponding instruction signal. In an optional example, both the write address and the read address can be obtained by latching the input / output circuit 210.

[0056] Specifically, the input / output circuit 210 can latch the write address when writing data to the memory array, and latch the read address when reading data from the memory array. It is understood that when the input / output circuit 210 receives a write command signal, it can obtain the data to be written and the corresponding write address based on the write command signal, and thus, the input / output circuit 210 can latch the write address. Similarly, when the input / output circuit 210 receives a read command signal, it can obtain the read address of the data to be read based on the read command signal, and thus, the input / output circuit 210 can latch the read address.

[0057] It should be noted that the input / output circuit 210 can be configured to latch at least two addresses simultaneously, thereby achieving latching of the corresponding addresses.

[0058] Accordingly, after latching the write address and the read address, the control circuit can compare the write address and the read address, thereby outputting a corresponding result signal. Wherein, reference... Figure 4 The diagram shows an optional circuit structure of a memory. The control circuit 220 may include an XOR unit. The XOR unit performs an XOR comparison on the latched read address RA and the latched write address WA, thereby outputting a corresponding result signal Hit. It is understood that during the XOR comparison, if the read address RA and the write address WA are the same, the output result signal is a low-level signal "0"; if the read address RA and the write address WA are different, the output result signal is a high-level signal "1".

[0059] Specifically, when the result signal Hit of the control circuit 220 indicates that the read address RA and the write address WA are consistent, the input / output circuit 210 outputs the latched data to be written as the read data; when the result signal Hit of the control circuit 220 indicates that the read address RA and the write address WA are inconsistent, the input / output circuit 210 outputs the data corresponding to the read address RA in the storage array 200 as the read data.

[0060] Optionally, the input / output circuit 210 may be equipped with a multiplexer 211 (also called a data selector MUX), so that when the result signal Hit in the control circuit 220 indicates that the read address RA and the write address WA are consistent, the multiplexer 211 selects the latched data to be written as the read data output. Correspondingly, when the result signal Hit in the control circuit 220 indicates that the read address RA and the write address WA are inconsistent, the multiplexer 211 selects the data at the corresponding read address in the storage array 200 as the read data output.

[0061] For details, please refer to [link / reference]. Figure 4 The diagram shows an optional circuit structure of a memory. The memory array 200 includes multiple memory cells (labeled as cells in the diagram) arranged in an array. The input / output circuit 210 may include a latch 212, which may correspond to one memory cell. The input terminal D of the latch 212 is used to input external input data D. (i = 0, 1, 2, 3), the output terminal Q is connected to the multiplexer 211, and the clock signal terminal Clk is connected to the write operation clock signal WrCLK. In the specific signal control process, the write operation clock signal WrCLK can control the latch 212 to open, thereby enabling the external input data D. The data is latched to one input of the multiplexer 211 to form the latched data signal WD. (i = 0, 1, 2, 3).

[0062] The latched data signal WD is input to one input terminal of the multiplexer 211. The other input terminal is connected to a preset storage cell in the storage array. It can be understood that the multiplexer 211 and the latch 212 correspond to the same storage cell. Correspondingly, the other input terminal of the multiplexer 211 is connected to the corresponding storage cell. The control terminal of the multiplexer 211 is connected to the control circuit 220 to receive the result signal Hit from the control circuit, thereby controlling the output selection data I based on the result signal Hit. (i = 0, 1, 2, 3).

[0063] In this example, when the result signal is 0, the multiplexer outputs the selected data I. For WD When the result signal is 1, the output selected data I The data N stored in the storage unit .

[0064] The input / output circuit may further include a readout trigger 213, the input terminal D of which is connected to the output terminal of the multiplexer 211, for inputting the selected data I. The output terminal Q is used to output the read data Q. (i = 0, 1, 2, 3), the clock signal terminal Clk is connected to the read operation clock signal RdCLK. In the specific signal control process, the read operation clock signal RdCLK can control the read flip-flop 213 to turn on, thereby selecting the data I... Output, forming the read data Q .

[0065] Combination Figure 5 The following is a timing diagram showing the operation of the memory signals. The working principle of the memory is as follows:

[0066] Taking a Write operation on a memory cell in Cycle1 and a Read operation in Cycle2 as an example, in Cycle1, the write operation clock signal WrClk, which controls the write operation, is enabled during the low level period of Cycle1, thus appearing as a high level. External input data D... The data is latched, forming the latched data signal WD. ( Figure 5 The signal shown in the middle is WD), and the write address of the write operation is simultaneously latched into the write address latch signal WA.

[0067] At the same time, the write word line signal WWL corresponding to the write address ( Figure 5 China-Israel WWL <0> (For example) During the low level of Cycle 1, pulse is enabled, thus appearing as a high level, thereby performing a write operation on a certain SRAM cell; in Cycle 2, the read operation clock signal RdClk, which controls the read operation, is enabled during the high level of Cycle 2, and the read address of the read operation is simultaneously latched into a read address latch signal RA. This read address latch signal RA is XORed with the write address latch signal WA of Cycle 1 (see reference). Figure 4 The control circuit shown uses the XOR unit. If RA and WA are the same, the output signal is ( Figure 5 If RA is 0 and WA is different, the output signal is 1, i.e., the Hit signal is 1.

[0068] Understandably, in Cycle1, the external input data D In other words, the latest data to be written to the memory cell has been latched as the latch data signal WD. The signal is connected to one input of the multiplexer, while the data N read from the storage unit... Then connect to the other input terminal of the multiplexer, and the Hit signal is connected to the control terminal of the multiplexer.

[0069] When the Hit signal is 0, the multiplexer selects WD. The output is the selected data I The data is then further processed by a trigger to output the final read data Q. ( Figure 5 The value is represented as Q. In other words, the data Q read from Cycle2... It is the external input data D of Cycle1 Therefore, when RA and WA are the same, that is, when two consecutive cycles perform a write-then-read operation on the same address, the memory of this embodiment of the invention will not read the data in the storage cell in Cycle2, but will read the latest data written in Cycle1.

[0070] As can be seen, the memory provided in this embodiment of the invention reads the latched data to be written when reading data, which can ensure that the data read is the latest data no matter when it is read, and there will be no error in the data read by the read operation due to insufficient write operation time. Therefore, there is no need to prohibit two consecutive clock cycles from writing to the same address before reading, and it will not affect the system's access algorithm.

[0071] In a further optional embodiment of the present invention, the control circuit may further control the read word line signal to be low when the read address is consistent with the write address, thereby eliminating the overlap of high-level signals between the write word line signal and the read word line signal.

[0072] Specifically, the control circuit in this embodiment of the invention may further include a read signal control unit 221. The read signal control unit 221 is used to update the read operation clock signal Rdclk based on the comparison result Hit of the read address RA and the write address WA; wherein, when the read address RA and the write address WA are the same, the read operation clock signal Rdclk is updated to a low level. It can be understood that if the read operation clock signal RWL is low, the corresponding read word line signal RWL can also be controlled to be low.

[0073] In an optional example, continue to refer to Figure 4 The circuit diagram shown indicates that the read signal control unit 221 can be a first AND operator, used to perform an AND operation on the comparison result Hit of the read address RA and the write address WA, and the read operation clock signal RdClk, and output the result signal of the AND operation as the read operation clock update signal RdClkG. It can be understood that the read operation clock update signal RdClkG is the updated read operation clock signal Rdclk.

[0074] Accordingly, the memory further includes a read word line driver circuit 230 for outputting a read word line signal RWL based on the read operation clock update signal RdClkG. Specifically, in an optional example, the read word line driver circuit 230 may include a second AND operator 231 for converting the read address decoding signal Rd_DEC... (i = 0, 1, 2, 3), and the read operation clock update signal RdClkG are ANDed to obtain the read word line signal RWL. (i = 0, 1, 2, 3).

[0075] Combination Figure 4 and Figure 5 The working principle of the memory to eliminate the overlap of high-level signals between the write word line signal and the read word line signal is as follows:

[0076] When RA and WA are the same, the Hit signal is 0. Correspondingly, the read operation clock update signal RdClkG, obtained by performing an AND operation between Hit and the read operation clock signal RdClk, is also 0. After the read operation clock update signal RdClkG is input to the read word line driver circuit, the read operation clock update signal RdClkG and the read address decoding signal Rd_DEC... Performing an AND operation yields the read word line signal RWL. ( Figure 5 (Taking i as 0 as an example) is also 0. Correspondingly, RWL Since Cycle2 is not in a high-level phase, there will be no overlap between WWL and RWL.

[0077] It is understandable that during a write-before-read operation, although the RWL is not in a high-level phase, the input / output circuit can still output the latched data to be written based on the result signal obtained after address comparison, thereby realizing the reading of the corresponding data. From another perspective, this embodiment of the invention can read data without activating the read word line, which can further reduce the power consumption of data reading.

[0078] Additionally, it should be noted that when the result signal in the control circuit indicates that the read address and the write address are inconsistent, the multiplexer can select the data corresponding to the read address in the storage array as the read data output based on the result signal, so that the corresponding read operation can normally read the data corresponding to the read address.

[0079] Specifically, in combination Figure 4 and Figure 5 The memory selects the data at the corresponding read address in the storage array as the read data output based on the result signal of the address comparison. That is, when RA and WA are different, that is, when two consecutive cycles perform write-then-read operations on different addresses, the memory can execute the normal read-write process. Specifically, the working principle of this process is as follows:

[0080] When the read address RA of Cycle2 is not equal to the write address WA of Cycle1 Figure 4 The control circuit outputs a Hit signal of 1 after an XOR comparison. The output signal RdClkG, generated by the AND operation between Hit and RdClk, is also 1. Then, RdClkG is compared with the decoded address signal Rd_DEC. The read line signal RWL obtained by performing an AND operation (i.e., high level 1), according to the result of the decoding signal, the corresponding RWL The high-level pulse is enabled in Cycle2 to read data from a specific memory cell, and the data N read from the memory cell is... Based on the Hit signal (i.e., 1) received by the multiplexer, N is selected. Output to I ，I The signal is then output by the readout trigger, becoming the final readout data Q. This allows Cycle2 to read data Q. The data stored in the storage unit.

[0081] As an optional implementation, this embodiment of the invention further provides a data processing method applied to the memory provided in the above embodiments, with reference to... Figure 6 An optional flowchart of a data processing method is shown, the method comprising:

[0082] Step S10: When writing data to the storage array, latch the data to be written;

[0083] In this way, by latching the data to be written, the latched data to be written can be directly output when outputting later, avoiding the possibility of reading the data before it has been written.

[0084] Step S12: When reading data from the storage array, compare the read address of the data to be read with the write address of the data to be written;

[0085] Understandably, by comparing the read address of the data to be read with the write address of the data to be written, it can be determined whether the data to be read is the data currently being written. If the read address of the data to be read matches the write address of the data to be written, it indicates that the device needs to read the data currently being written, and proceed to step S14.

[0086] The read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

[0087] In an optional example, while latching the data to be written, the write address can also be latched simultaneously. Furthermore, when reading data from the storage array, the read address is also latched. Then, when comparing the read address of the data to be read with the write address of the data to be written, the latched read address and the latched write address can be XORed to output a corresponding result signal to indicate the specific comparison result.

[0088] Step S14: Use the latched data to be written as the data to be read;

[0089] It is understandable that when the read address and write address are the same, it indicates that the device needs to read the data currently being written. Therefore, the latched data to be written is used as the read data, ensuring that the latest data is always read whenever data is read, preventing errors in the read operation due to insufficient write operation time. Furthermore, the memory provided in this embodiment does not need to prohibit two consecutive cycles (clock cycles) from writing to the same address before reading, thus not affecting the system's access algorithm.

[0090] Optionally, step S14 can specifically involve selecting the latched data to be written as the read data and inputting it, thereby realizing the use of the latched data to be written as the read data.

[0091] In an optional example, refer to Figure 7 Another optional flowchart of a data processing method is shown. If, in step S12, the read address of the data to be read is inconsistent with the write address of the data to be written, it indicates that the device needs to read the data stored in the storage array, and then step S16 can be executed.

[0092] Step S16: Select the data at the corresponding read address in the storage array as the read data;

[0093] By selecting the data at the corresponding read address in the memory array as the read data, the memory can perform a normal read process.

[0094] In another optional example, the data processing method further controls the read-word line signal to prevent signal errors. Specifically, after step S12, it may also include:

[0095] Step S18: When the read address and the write address are the same, control the read word line signal to be low;

[0096] By controlling the read line signal to a low level, the overlap of high-level signals between the write line signal and the read line signal can be eliminated.

[0097] For details, please refer to Figure 8 The flowchart shown for step S18 is optional. Step S18 may include:

[0098] Step S181: Perform an AND operation on the comparison result between the read address and the write address, and the read operation clock signal, and use the result signal of the AND operation as the read operation clock update signal;

[0099] Step S182: Output the read word line signal based on the read operation clock update signal;

[0100] It is understandable that when the comparison result between the read address and the write address is consistent, the corresponding result signal is 0. After performing an AND operation with the read operation clock signal, the resulting signal is also 0. Accordingly, the read operation clock update signal is 0. When the read operation clock update signal is 0, the corresponding read word line signal is also 0, thereby eliminating the overlap of high-level signals between the write word line signal and the read word line signal.

[0101] Furthermore, it should be noted that when the comparison result between the read address and the write address is inconsistent, the corresponding result signal is 1. After performing an AND operation with the read operation clock signal, the resulting signal is also 1. Accordingly, the read operation clock update signal is 1. When the read operation clock update signal is 1, the corresponding read word line signal is also 1, thus enabling the normal read process to be executed.

[0102] As an optional implementation, embodiments of the present invention further provide a chip, the chip including the memory provided in the above embodiments.

[0103] It should be noted that in the embodiments provided by the present invention, i represents a natural number, which can be substituted based on a specific numerical value. In the relevant embodiments and figures, i = 0, 1, 2, 3 is used as an example. In other examples, the value of i can vary with the specific structure of the circuit. For example, in a structure with 8 memory cells, the corresponding input and output circuits should also have 8 devices, and the corresponding value of i can be 0, 1, 2, 3, 4, 5, 6, 7. In other structures, those skilled in the art can set the values ​​according to the actual situation and the ideas of the present invention, which will not be elaborated here.

[0104] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0105] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory, characterized in that, The memory includes static random access memory, comprising: A storage array for storing data written to the storage array; An input / output circuit is used to write data to or read data from the storage array, wherein when writing data to the storage array, the data to be written is latched. The control circuit is used to compare the read address of the data to be read with the write address of the data to be written when the input / output circuit reads data from the storage array. If they match, the control circuit outputs the latched data to be written as the read data. When the read address matches the write address, the control circuit controls the read word line signal to be low. The input / output circuit is further configured to latch the write address when writing data to the storage array and to latch the read address when reading data from the storage array; the latching time limit should be at least greater than or equal to the time it takes for the memory to complete one data write; the read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

2. The memory according to claim 1, characterized in that, The control circuit includes an XOR unit, which is used to perform an XOR comparison between the latched read address and the latched write address, and output the corresponding result signal.

3. The memory according to claim 1, characterized in that, The input / output circuit further includes a multiplexer, which is used to select the latched data to be written as the read data output when the result signal in the control circuit indicates that the read address and the write address are consistent.

4. The memory according to claim 3, characterized in that, The input / output circuit further includes a multiplexer, used to select the data at the corresponding read address in the storage array as the read data output when the result signal in the control circuit indicates that the read address and the write address are inconsistent.

5. The memory according to claim 2, characterized in that, The storage array includes multiple storage cells arranged in an array, and the input / output circuit includes a latch, a multiplexer, and a readout trigger. The latch's input terminal is used to input external input data, its output terminal is connected to one input terminal of the multiplexer, and its clock signal terminal is connected to the write operation clock signal. The other input of the multiplexer is connected to one of the storage cells in the storage array, and the control terminal is connected to the control circuit to receive the result signal from the control circuit. The input terminal of the readout trigger is connected to the output terminal of the multiplexer, the output terminal is used to output the readout data, and the clock signal terminal is connected to the read operation clock signal.

6. The memory according to claim 1, characterized in that, The control circuit further includes a read signal control unit, which is used to update the read operation clock signal based on the comparison result between the read address and the write address; wherein, when the read address and the write address are the same, the read operation clock signal is updated to a low level.

7. The memory according to claim 6, characterized in that, The read signal control unit is a first AND operator, used to perform an AND operation on the comparison result of the read address and the write address, and the read operation clock signal, and output the result signal of the AND operation as the read operation clock update signal. The memory also includes a read word line driving circuit, which is used to output a read word line signal based on the read operation clock update signal.

8. A data processing method, characterized in that, Applied to a memory, including static random access memory, the method includes: When writing data to the storage array, latch the data to be written; When reading data from the storage array, the read address of the data to be read is compared with the write address of the data to be written. If they match, the latched data to be written is used as the read data. When the read address matches the write address, the read word line signal is controlled to be low. In the step of writing data to the storage array and latching the data to be written, the write address is also latched simultaneously; in the step of reading data from the storage array, the read address is also latched; the latching time limit should be at least greater than or equal to the time it takes for the memory to complete one data write; the read address is used to indicate the location of the data to be read in the storage array, and the write address is used to indicate the location of the data to be written in the storage array.

9. The method according to claim 8, characterized in that, The comparison of the read address of the data to be read and the write address of the data to be written specifically involves performing an XOR comparison on the latched read address and the latched write address.

10. The method according to claim 8, characterized in that, Specifically, using latched data to be written as read data means selecting the latched data to be written as read data.

11. The method according to claim 10, characterized in that, It also includes selecting the data at the corresponding read address in the storage array as the read data when the read address and the write address are inconsistent.

12. The method according to claim 8, characterized in that, When the read address and the write address are the same, controlling the read word line signal to be low includes: The comparison result between the read address and the write address, and the read operation clock signal are ANDed, and the result of the AND operation is output as the read operation clock update signal. Based on the read operation clock update signal, the read word line signal is output.

13. A chip, characterized in that, The chip includes the memory as described in any one of claims 1-7.

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