Shift register control-based driving circuit and electronic device

Abstract

The application discloses a kind of driving circuit based on shift register control, including: shift register configuration circuit, can be bit by bit register to the input configuration signal in series and parallel output, to configure the different gear of voltage stabilizing circuit and the different channel of buffer and voltage control circuit;Voltage stabilizing circuit, including analog power management integrated circuit for realizing voltage stabilization, for providing stable voltage to buffer and voltage control circuit;The decoding circuit is used for decoding the control signal output by shift register configuration circuit, the control signal is decoded as single-bit output control signal, to independently control the buffer and voltage control circuit of different channel;The buffer and voltage control circuit, including the drive circuit of MOSFET and the control circuit composed of MOSFET, can realize the independent opening or shutoff of different channel, to realize the independent drive of different channel of GaN FET and logic level MOSFET.The application also provides corresponding electronic device.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to a drive circuit and electronic device based on shift register control. Background Technology

[0002] In high-speed applications, including LiDAR (Light Identification Detection and Ranging), time-of-flight, and any power converter involving low-side drivers, low-side driver chips are typically used to drive GaN FETs (GaN Field Effect Transistors) and logic-level MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors). Traditional driver schemes use discrete FPGAs (Field Programmable Gate Arrays) or MCUs (Microcontroller Units) to generate control logic, which then controls the discrete driver chip to drive the discrete GaN FETs and logic-level MOSFETs. This results in complex control and wiring, large size, high cost, and poor configurability in traditional solutions. Therefore, developing a simple, small, low-cost driver with good compatibility has become a critical issue. Summary of the Invention

[0003] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a drive circuit based on shift register control, which is simple, small in size, low in cost, and has good compatibility.

[0004] To achieve the above objectives, according to one aspect of the present invention, a drive circuit based on shift register control is provided, comprising a shift register configuration circuit, a voltage regulator circuit, a decoding circuit, and a buffer and voltage control circuit, wherein:

[0005] The shift register configuration circuit includes a multi-bit shift register composed of several registers connected end to end, a D flip-flop for buffering the output signal of the shift register, and an output buffer tri-state gate circuit. It can register the serial input configuration signal bit by bit and output it in parallel, thereby configuring different levels of the voltage regulator circuit and different channels of the buffer and voltage control circuit.

[0006] The voltage regulator circuit includes an analog power management integrated circuit for achieving voltage stability, which provides a stable voltage to the buffer and voltage control circuit.

[0007] The decoding circuit is used to decode the control signal output by the shift register configuration circuit, and decode the control signal into a single-bit output control signal, thereby independently controlling the buffer and voltage control circuits of different channels.

[0008] The buffer and voltage control circuit, including the MOSFET driving circuit and the control circuit composed of MOSFETs, can independently turn different channels on or off, thereby realizing independent driving of different channels of GaN FET and logic level MOSFET.

[0009] In one embodiment of the present invention, the shift register configuration circuit includes a set of multi-bit shift registers consisting of registers connected end to end with a reset signal. Each shift register is followed by a D flip-flop for buffering the output signal of the shift register, and each D flip-flop is followed by a tri-state gate for output control and buffering.

[0010] In one embodiment of the present invention, the multi-bit shift register includes eight shift registers with reset signals. Each shift register is connected to a D flip-flop for buffering the output signal of the shift register. Each D flip-flop is connected to a tri-state gate to control and buffer the output.

[0011] In one embodiment of the present invention,

[0012] The input configuration signal is a serial input. When each shift clock signal arrives, the shift register will perform a shift once to achieve buffering and parallel output of the serial input configuration signal;

[0013] The reset signal can reset the shift register;

[0014] When the buffer control signal arrives, the configuration signal in the shift register will be sampled by the D flip-flop connected to it.

[0015] When the input enable signal arrives, all eight tri-state gates open simultaneously, and the configuration signal buffered in the D flip-flops is output to the subsequent circuit through the tri-state gate buffer.

[0016] In one embodiment of the present invention, the voltage regulator circuit includes a low-dropout linear regulator, which is powered by an external input power supply and the input signals are six input configuration signals from the shift register configuration circuit.

[0017] In one embodiment of the present invention, the output of the low-dropout linear regulator can be configured to provide 26-64 stable voltages to the buffer and voltage control circuit of the subsequent drive.

[0018] In one embodiment of the present invention, the number of channels selected is 4.

[0019] In one embodiment of the present invention, the decoding circuit includes a 2-to-4 decoder, the input of which is two configuration signals from the shift register configuration circuit. The 2-to-4 decoder decodes the two-bit configuration signals into four single-bit outputs, thereby controlling the buffer and voltage control circuits of different channels.

[0020] In one embodiment of the present invention, the buffer and voltage control circuit includes four buffer circuits powered by low dropout linear regulators. Each buffer circuit is connected to a MOSFET as a switch to control the four channels. The four channels are independently controlled by the output of a 2-to-4 decoder and the differential external chip input signals IN+ and IN-, thereby enabling the independent opening or closing of different channels.

[0021] According to another aspect of the invention, an electronic device is also provided, which includes the aforementioned shift register-based drive circuit.

[0022] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0023] This invention provides a driver circuit based on shift register control. Compared to traditional discrete implementations that use discrete FPGAs or MCUs to generate control logic and drive discrete GaN FETs and logic-level MOSFETs via discrete driver chips, this circuit only requires a serial-input shift register to achieve serial-to-parallel conversion of configuration signals. The output signal of the shift register configures different voltage levels of the voltage regulator circuit and different channels of the buffer and voltage control circuits. Compared to traditional discrete implementations, this driver circuit has a simpler structure. By integrating the configuration circuit, voltage regulator circuit, and buffer and voltage control circuit, it achieves small size, low cost, and flexible configuration. It also reduces the number of input ports, thus saving a significant number of I / O (Input / Output) lines in the control circuit. Attached Figure Description

[0024] Figure 1 This is a block diagram of a drive circuit based on shift register control provided by the present invention;

[0025] Figure 2 This is a specific implementation example diagram of the drive circuit based on shift register control provided by the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] This invention discloses a drive circuit based on shift register control, including a shift register configuration circuit for configuring different levels of the voltage regulator circuit and different channels of the buffer and voltage control circuit; a voltage regulator circuit for providing a stable voltage to the buffer and voltage control circuit; a decoding circuit for decoding the two-bit control signal output by the shift register configuration circuit, decoding it into a single-bit output to control the buffer and voltage control circuits of different channels; and a buffer and voltage control circuit for independently turning different channels on or off.

[0028] For the purposes of this invention, see [link to relevant documentation]. Figure 1 As shown, this invention provides a drive circuit based on shift register control, including a shift register configuration circuit, a voltage regulator circuit, a decoding circuit, and a buffer and voltage control circuit, wherein:

[0029] The shift register configuration circuit includes a multi-bit shift register composed of several registers connected end to end, a D flip-flop for buffering the output signal of the shift register, and an output buffer tri-state gate circuit. It can register the serial input configuration signal bit by bit and output it in parallel, thereby configuring different levels of the voltage regulator circuit and different channels of the buffer and voltage control circuit.

[0030] The voltage regulator circuit includes an analog power management integrated circuit for achieving voltage stability, which provides a stable voltage to the buffer and voltage control circuit.

[0031] The decoding circuit is used to decode the control signal output by the shift register configuration circuit, and decode the control signal into a single-bit output control signal, thereby independently controlling the buffer and voltage control circuits of different channels.

[0032] The buffer and voltage control circuit, including the MOSFET driving circuit and the control circuit composed of MOSFETs, can independently turn different channels on or off, thereby realizing independent driving of different channels of GaN FET and logic level MOSFET.

[0033] See Figure 2 As shown in the figure, an embodiment of this invention provides a drive circuit based on shift register control, including: a shift register configuration circuit, a voltage regulator circuit, a decoding circuit, and a buffer and voltage control circuit. Wherein:

[0034] Specifically, in this embodiment, the shift register configuration circuit includes a set of multi-bit shift registers consisting of registers connected end to end with a reset signal. Each shift register is followed by a D flip-flop for buffering the output signal of the shift register, and each D flip-flop is followed by a tri-state gate for output control and buffering.

[0035] Specifically, in this embodiment, the multi-bit shift register includes eight shift registers with reset signals. Each shift register is followed by a D flip-flop to buffer the output signal of the shift register. Each D flip-flop is followed by a tri-state gate to control and buffer the output. The input configuration signal (SRE signal) is a serial input. The shift register shifts once when each shift clock signal (SCK clock signal) arrives, achieving buffering and parallel output of the serial input configuration signal. The reset signal (RST signal) resets the shift register. When the buffer control signal (RCK signal) arrives, the configuration signal in the shift register is sampled by the subsequent D flip-flops. When the input enable signal (OEN signal) arrives, all eight tri-state gates open simultaneously, and the configuration signal buffered in the D flip-flops is buffered and output to subsequent circuits through the tri-state gates.

[0036] Specifically, in this embodiment, the voltage regulator circuit includes a low dropout linear regulator. The low dropout linear regulator is powered by an external input power supply, and the input signals are six input configuration signals from the shift register configuration circuit. The output of the low dropout linear regulator can be configured to 26-64 stable voltages to provide buffer and voltage control circuits for the drive.

[0037] Specifically, in this embodiment, the number of channels selected is 4. Therefore, the decoding circuit includes a 2-to-4 decoder. The input is two configuration signals from the shift register configuration circuit. The 2-to-4 decoder decodes the two-bit configuration signals into four single-bit outputs, thereby controlling the buffer and voltage control circuits of different channels.

[0038] Specifically, in this embodiment, the buffer and voltage control circuit includes four buffer circuits powered by low-dropout linear regulators. Each buffer circuit is connected to a MOSFET as a switch to control the four channels. The four channels are independently controlled by the output of a 2-to-4 decoder and the differential external chip input signals IN+ and IN-, thereby enabling different channels to be independently turned on or off.

[0039] Furthermore, the present invention also provides an electronic device comprising the aforementioned shift register-based drive circuit.

[0040] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A drive circuit based on shift register control, characterized in that, It includes a shift register configuration circuit, a voltage regulator circuit, a decoding circuit, and a buffer and voltage control circuit, wherein: The shift register configuration circuit includes a multi-bit shift register composed of several registers connected end to end, a D flip-flop for buffering the output signal of the shift register, and an output buffer tri-state gate circuit. It can register the serial input configuration signal bit by bit and output it in parallel, thereby configuring different voltage levels of the voltage regulator circuit and different channels of the buffer and voltage control circuit. The voltage regulator circuit includes an analog power management integrated circuit for achieving voltage stability, used to provide a stable voltage to the buffer and voltage control circuit; wherein the analog power management integrated circuit is a low dropout linear regulator; The decoding circuit is used to decode the control signal output by the shift register configuration circuit, and decode the control signal into a single-bit output control signal, thereby independently controlling the buffer and voltage control circuits of different channels. The buffer and voltage control circuit, including the MOSFET driving circuit and the control circuit composed of MOSFETs, can independently turn different channels on or off, thereby realizing independent driving of different channels of GaN FET and logic level MOSFET.

2. The drive circuit based on shift register control as described in claim 1, characterized in that, The shift register configuration circuit includes a set of multi-bit shift registers with a reset signal, consisting of registers connected end to end. Each shift register is followed by a D flip-flop for buffering the output signal of the shift register, and each D flip-flop is followed by a tri-state gate for output control and buffering.

3. The drive circuit based on shift register control as described in claim 2, characterized in that, The multi-bit shift register contains eight shift registers with reset signals. Each shift register is connected to a D flip-flop for buffering the output signal of the shift register. Each D flip-flop is connected to a tri-state gate to control and buffer the output.

4. The drive circuit based on shift register control as described in claim 3, characterized in that, The input configuration signal is a serial input. When each shift clock signal arrives, the shift register will perform a shift once to achieve buffering and parallel output of the serial input configuration signal; The reset signal can reset the shift register; When the buffer control signal arrives, the configuration signal in the shift register will be sampled by the D flip-flop connected to it. When the input enable signal arrives, all eight tri-state gates open simultaneously, and the configuration signal buffered in the D flip-flops is output to the subsequent circuit through the tri-state gate buffer.

5. The drive circuit based on shift register control as described in claim 1 or 2, characterized in that, The voltage regulator circuit includes a low-dropout linear regulator, which is powered by an external input power source, and the input signals are six input configuration signals from the shift register configuration circuit.

6. The drive circuit based on shift register control as described in claim 5, characterized in that, The output of the low-dropout linear regulator can be configured to provide 26-64 stable voltages to the buffer and voltage control circuitry of the drive.

7. The drive circuit based on shift register control as described in claim 1 or 2, characterized in that, The selected number of channels is 4.

8. The drive circuit based on shift register control as described in claim 7, characterized in that, The decoding circuit includes a 2-to-4 decoder. The input is two configuration signals from the shift register configuration circuit. The 2-to-4 decoder decodes the two-bit configuration signals into four single-bit outputs, thereby controlling the buffer and voltage control circuits of different channels.

9. The drive circuit based on shift register control as described in claim 1 or 2, characterized in that, The buffer and voltage control circuit includes four buffer circuits powered by low dropout linear regulators. Each buffer circuit is connected to a MOSFET as a switch to control the four channels. The four channels are independently controlled by the output of the 2-to-4 decoder and the differential external chip input signals IN+ and IN-, thereby enabling different channels to be turned on or off independently.

10. An electronic device, characterized in that, It includes the drive circuit based on shift register control as described in any one of claims 1-9.

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