Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate having a first trench and a second trench formed therein; forming a first gate oxide dielectric layer and a first initial gate electrode on an upper sidewall surface of the first trench, and forming a second gate oxide dielectric layer and a second gate electrode on an upper sidewall surface of the second trench, removing a portion of the first initial gate electrode, and removing the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose an upper half of the upper sidewall surface of the first trench; and filling a gate electrode material in the first trench to form a first gate electrode. The present application can reduce the number of source contact holes required, effectively overcome the size limitation of semiconductor devices, and reduce production costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Shielded-gate MOSFETs (SGTs, also known as metal-oxide-semiconductor field-effect transistors) offer greater flexibility in semiconductor integrated circuit applications compared to traditional MOSFETs due to their lower gate-drain capacitance (Cgd), lower on-resistance, and higher breakdown voltage. Specifically, by placing a shielding electrode below the gate electrode in a SGT, the gate-drain capacitance can be significantly reduced, the device electric field optimized, and the breakdown voltage improved. Furthermore, the drift region of a SGT exhibits a higher concentration of impurity carriers, which correspondingly reduces the on-resistance.

[0003] Furthermore, for semiconductor structures with split-gate field-effect transistors, in order to achieve fast switching, improve reverse recovery speed and reduce power consumption when the transistor is turned off, an additional rectifier, such as a super barrier rectifier (SBR) device, is usually set in the semiconductor structure.

[0004] However, in existing technologies, to achieve the function of an SBR device, an additional source contact hole structure needs to be formed on the gate electrode surface to short-circuit the remaining source terminals, thereby providing reverse freewheeling capability. However, as the device feature size shrinks further, the device size becomes difficult to reduce further due to limitations in the maximum source contact hole density.

[0005] There is an urgent need for a method to form semiconductor structures that can effectively overcome the size limitations of semiconductor devices and reduce production costs. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can reduce the number of source contact holes required, effectively overcome the size limitations of semiconductor devices, and reduce production costs.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first trench and a second trench are formed in the semiconductor substrate; forming a field oxide dielectric layer on the bottom and lower sidewall surfaces of the first trench and the second trench, and forming a shielding electrode encapsulated within the field oxide dielectric layer; forming a first gate oxide dielectric layer on the upper sidewall surface of the first trench, and forming a second gate oxide dielectric layer on the upper sidewall surface of the second trench, wherein the thickness of the first gate oxide dielectric layer is less than the thickness of the second gate oxide dielectric layer; filling the surface of the field oxide dielectric layer in the first trench with a gate electrode material to form a first initial gate electrode, and forming a second gate electrode on the surface of the field oxide dielectric layer in the second trench; removing a portion of the first initial gate electrode, and removing the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose the upper half of the upper sidewall surface of the first trench; and filling the first trench with a gate electrode material to form a first gate electrode.

[0008] Optionally, the method of forming the semiconductor structure further includes: forming a first well region and a first source region in a semiconductor substrate on the side of the first trench to form a super barrier rectifier SBR device; wherein the first source region covers a portion of the first well region, the first source region is electrically connected to the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.

[0009] Optionally, the method for forming the semiconductor structure further includes: forming a source contact hole structure in a semiconductor substrate on the side of the first trench; wherein the first source region surrounds or partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure; the first well region partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure.

[0010] Optionally, the method of forming the semiconductor structure further includes: forming a first body region in a semiconductor substrate on the side of the first trench; wherein the first body region partially surrounds the first well region, and the first source region covers a portion of the first body region.

[0011] Optionally, the method of forming the semiconductor structure further includes: forming one or more of the following in a semiconductor substrate on the side of the second trench to form a split-gate field-effect transistor (SGT) MOS device: a second body region, a second well region, and a second source region; wherein the second source region covers a portion of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide layer, the second body region partially surrounds the second well region, and the second source region covers a portion of the second body region.

[0012] Optionally, forming a field oxygen dielectric layer on the bottom and lower sidewall surfaces of the first and second trenches, and forming a shielding electrode encapsulated within the field oxygen dielectric layer, includes: forming an initial field oxygen dielectric film covering the bottom and sidewall surfaces of the first and second trenches and having a cavity region; filling the shielding electrode in the cavity region; removing a portion of the shielding electrode and removing the initial field oxygen dielectric film surrounding the removed portion of the shielding electrode; depositing a field oxygen dielectric film covering the remaining initial field oxygen dielectric film and the shielding electrode; and removing a portion of the field oxygen dielectric film to obtain the field oxygen dielectric layer.

[0013] Optionally, forming a first gate oxide dielectric layer on the upper sidewall surface of the first trench and a second gate oxide dielectric layer on the upper sidewall surface of the second trench includes: forming a first initial gate oxide dielectric layer on the upper sidewall surface of the first trench and a second initial gate oxide dielectric layer on the upper sidewall surface of the second trench using a first oxidation process, wherein the thickness of the first initial gate oxide dielectric layer is the same as the thickness of the second initial gate oxide dielectric layer; removing the first initial gate oxide dielectric layer; forming the first gate oxide dielectric layer on the upper sidewall surface of the first trench using a second oxidation process, and performing a secondary oxidation on the second initial gate oxide dielectric layer to obtain the second gate oxide dielectric layer.

[0014] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a first trench and a second trench located within the semiconductor substrate; a field oxide dielectric layer and a shielding electrode encapsulated within the field oxide dielectric layer, wherein the field oxide dielectric layer is located at the bottom and lower sidewall surfaces of the first trench and the second trench; a first gate oxide dielectric layer located on the surface of a portion of the upper sidewall of the first trench; a second gate oxide dielectric layer located on the surface of the upper sidewall of the second trench, wherein the thickness of the first gate oxide dielectric layer is less than the thickness of the second gate oxide dielectric layer; a first gate electrode located on the surface of the field oxide dielectric layer within the first trench and in contact with the upper half of the upper sidewall surface of the first trench; and a second gate electrode located on the surface of the field oxide dielectric layer within the second trench.

[0015] Optionally, the semiconductor structure further includes: a first well region and a first source region, located in the semiconductor substrate on the side of the first trench, to form a super barrier rectifier (SBR) device; wherein the first source region covers a portion of the first well region, the first source region is electrically connected to the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer.

[0016] Optionally, the semiconductor structure further includes: a source contact hole structure located in the semiconductor substrate on the side of the first trench; wherein the first source region surrounds or partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure; the first well region partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure.

[0017] Optionally, the semiconductor structure further includes: a first body region located in a semiconductor substrate on the side of the first trench; wherein the first body region partially surrounds the first well region, and the first source region covers a portion of the first body region.

[0018] Optionally, the semiconductor structure further includes one or more of a second body region, a second well region, and a second source region, located in a semiconductor substrate on the side of the second trench to form a split-gate field-effect transistor (SGT) MOS device; wherein the second source region covers a portion of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide layer, the second body region partially surrounds the second well region, and the second source region covers a portion of the second body region.

[0019] Optionally, both the SBR device and the SGT MOS device in the semiconductor structure are located in the cell region.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0021] In this embodiment of the invention, a first gate oxide dielectric layer and a first initial gate electrode are formed on the upper sidewall surface of a first trench, and a second gate oxide dielectric layer and a second gate electrode are formed on the upper sidewall surface of a second trench. A portion of the first initial gate electrode is removed, and the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode is also removed to expose the upper half of the upper sidewall surface of the first trench. Then, gate electrode material is filled into the first trench to form a first gate electrode. This allows for the formation of a thinner first gate oxide dielectric layer within the first trench, and a first gate electrode that contacts the upper half of the upper sidewall surface of the first trench. This allows the device formed in the first trench to directly obtain the gate control voltage provided by the source contact hole structure located on the side of the trench without being isolated by the gate oxide layer. Thus, the device formed in the first trench can be controlled (e.g., turned on / off) without relying on an additional source contact hole structure to provide the gate control voltage. Compared with the prior art, which requires an additional source contact hole structure to be formed on the gate electrode surface in the SBR device to provide the gate control voltage, resulting in a large number of source contact hole structures required, the solution of this embodiment can reduce the number of source contact hole structures required, effectively overcome the size limitations of semiconductor devices, and reduce production costs.

[0022] Furthermore, a first well region and a first source region are formed in the semiconductor substrate on the side of the first trench to form a super-barrier rectifier SBR device; wherein, the first source region covers a portion of the first well region, the first source region is electrically connected to the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer, thereby enabling the SBR device to be turned on / off without relying on the source contact hole structure to provide the gate control voltage, while effectively reducing leakage current.

[0023] Furthermore, by forming an initial field oxygen dielectric film, filling the cavity region with the shielding electrode, removing a portion of the shielding electrode, depositing a field oxygen dielectric film, and removing a portion of the field oxygen dielectric film to obtain the field oxygen dielectric layer, the same process can be used to form the field oxygen dielectric layer encapsulating the shielding electrode in both the first and second trenches, effectively improving process efficiency and reducing process costs.

[0024] Furthermore, a first oxidation process is used to form a first initial gate oxide dielectric layer and a second initial gate oxide dielectric layer, and then the first initial gate oxide dielectric layer is removed; then a second oxidation process is used to form a first gate oxide dielectric layer on the upper sidewall surface of the first trench, and the second initial gate oxide dielectric layer is subjected to secondary oxidation to obtain a second gate oxide dielectric layer. Using the scheme of this embodiment of the invention, a thinner first gate oxide dielectric layer can be obtained through the oxidation process. Compared with other processes (such as deposition processes), a gate oxide dielectric layer of better quality can be formed. By using secondary oxidation after removing the first initial gate oxide dielectric layer, a thinner gate oxide dielectric layer can be formed in the device (such as SBR device) formed in the first trench; and the second gate oxide dielectric layer formed by secondary oxidation also has better density and electrical isolation characteristics. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor device in the prior art;

[0026] Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0027] Figures 3 to 13 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0028] Figure 14 This is a schematic diagram of the working scenario of an SBR device in an embodiment of the present invention.

[0029] Figure label:

[0030] Semiconductor substrate 100; source contact hole structure 151; SBR source contact hole structure 152; metal layer 180; semiconductor substrate 200; first trench 211; second trench 212; initial field oxide dielectric film 221; shielding electrode 222; field oxide dielectric film 223; field oxide dielectric layer 220; first initial gate oxide dielectric layer 231; second initial gate oxide dielectric layer 232; first mask layer 261; first gate oxide dielectric layer 233; second gate oxide dielectric layer 234; first initial gate electrode 241; second gate electrode 242; second mask layer 262; gate electrode material 243; first gate electrode 240; source contact hole structure 251; metal layer 280; first source region 271; first well region 272; first body region 273; second source region 274; second well region 275; second body region 276. Detailed Implementation

[0031] In the existing technology, SGT MOS devices are widely used in switching power supplies due to their excellent on-resistance and switching characteristics. Especially in applications such as synchronous rectification, the MOS transistor needs to freewheel through the body diode in the dead zone before conduction. However, the inherent forward voltage drop of the diode (0.7V at room temperature) can easily increase the overall power consumption and limit the efficiency improvement.

[0032] To solve this problem, the following three common solutions are available:

[0033] 1. Integrated Schottky diodes; however, Schottky diodes are limited by process constraints, resulting in poor high-temperature characteristics and reliability.

[0034] 2. Reduce the non-equilibrium carrier lifetime of the body diode (electron irradiation, gold / platinum / palladium doping), but special processes are required, making it difficult to apply in a wide range of applications;

[0035] 3. Integrating SBR devices: Since SBR devices and MOS devices have good process compatibility and conduct through channels, they can avoid the disadvantages of Schottky diodes. Therefore, this method is receiving increasing attention.

[0036] Research has revealed that, in one specific implementation of the existing technology, to achieve the function of the SBR device, an additional source contact hole structure needs to be formed on the surface of the gate electrode in the SBR device to provide a gate control voltage. For example, the SBR device can be turned on when the gate control voltage is greater than or equal to a preset threshold voltage, and turned off when the gate control voltage is less than the preset threshold voltage. Furthermore, source contact hole structures also need to be formed in the semiconductor substrate on the side of both the SBR device and the SGT MOS device to provide carrier flow voltage, resulting in a large required number of source contact hole structures.

[0037] Reference Figure 1 , Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device in the prior art.

[0038] As shown in the figure, in an existing SGT MOS device that integrates SBR devices, appropriate SBR devices and SGT MOS devices can be formed in the semiconductor substrate 100 first. As can be seen from the figure, the gate electrode structures of the SBR device and the SGT MOS device are quite similar, and both are isolated by the gate oxide dielectric layer.

[0039] To provide the gate control voltage, an additional SBR source contact hole structure 152 can be formed on the surface of the gate electrode structure of the SBR device, and the gate control voltage can be provided through the metal layer 180. For example, the SBR device can be turned on when the gate control voltage is greater than or equal to a preset threshold voltage, and the SBR device can be turned off when the gate control voltage is less than the preset threshold voltage.

[0040] In addition, source contact hole structures 151 need to be formed in the semiconductor substrate on the side of the SBR device and the SGT MOS device to provide carrier flow voltage via the metal layer 180.

[0041] Research has found that, Figure 1 The prior art shown requires both source contact hole structure 151 and SBR source contact hole structure 152, resulting in a large total demand for source contact hole structure 151, which limits the size of semiconductor devices and increases production costs.

[0042] It should be noted that, in another specific embodiment of the prior art, at the location of the SBR device, a larger source contact hole is formed with a cross-sectional size larger than the trench size of the SBR device, and then filled with conductive material to provide a gate control voltage to the SBR device.

[0043] However, in this method, since the bottom of the larger source contact hole is formed inside the semiconductor substrate, it will damage the semiconductor substrate material. Furthermore, the cross-sectional size of the source contact hole is larger, occupying more space, making it more difficult to reduce the size of the semiconductor device, and it is also prone to short circuit problems.

[0044] In this embodiment of the invention, a first gate oxide dielectric layer and a first initial gate electrode are formed on the upper sidewall surface of a first trench, and a second gate oxide dielectric layer and a second gate electrode are formed on the upper sidewall surface of a second trench. A portion of the first initial gate electrode is removed, and the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode is also removed to expose the upper half of the upper sidewall surface of the first trench. Then, gate electrode material is filled into the first trench to form a first gate electrode. This allows for the formation of a thinner first gate oxide dielectric layer within the first trench, and a first gate electrode that contacts the upper half of the upper sidewall surface of the first trench. This allows the device formed in the first trench to directly obtain the gate control voltage provided by the source contact hole structure located on the side of the trench without being isolated by the gate oxide layer. Thus, the device formed in the first trench can be controlled (e.g., turned on / off) without relying on an additional source contact hole structure to provide the gate control voltage. Compared with the prior art, which requires an additional source contact hole structure to be formed on the gate electrode surface in the SBR device to provide the gate control voltage, resulting in a large number of source contact hole structures required, the solution of this embodiment can reduce the number of source contact hole structures required, effectively overcome the size limitations of semiconductor devices, and reduce production costs.

[0045] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Reference Figure 2 , Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method for forming the semiconductor structure may include steps S21 to S26:

[0047] Step S21: Provide a semiconductor substrate in which a first trench and a second trench are formed;

[0048] Step S22: Form a field oxygen dielectric layer on the bottom and lower sidewall surface of the first trench and the second trench, and form a shielding electrode wrapped inside the field oxygen dielectric layer;

[0049] Step S23: A first gate oxide dielectric layer is formed on the upper sidewall surface of the first trench, and a second gate oxide dielectric layer is formed on the upper sidewall surface of the second trench, wherein the thickness of the first gate oxide dielectric layer is less than the thickness of the second gate oxide dielectric layer.

[0050] Step S24: Fill the surface of the field oxygen dielectric layer in the first trench with gate electrode material to form a first initial gate electrode, and form a second gate electrode on the surface of the field oxygen dielectric layer in the second trench.

[0051] Step S25: Remove a portion of the first initial gate electrode and remove the first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode to expose the upper half of the upper sidewall surface of the first trench;

[0052] Step S26: Fill the first trench with gate electrode material to form a first gate electrode.

[0053] The following is combined Figures 3 to 13 The steps described above will be explained.

[0054] Figures 3 to 13 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Reference Figure 3 A semiconductor substrate 200 is provided, wherein a first trench 211 and a second trench 212 are formed in the semiconductor substrate 200.

[0056] The semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may also include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. The semiconductor substrate 200 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxy layer (Epi layer) grown on it. Preferably, the semiconductor substrate 200 is a lightly doped semiconductor substrate.

[0057] Non-limiting, the semiconductor substrate 200 can be formed by implanting a first type of ion into an initial semiconductor substrate, for example, implanting N-type ions to form a shallowly doped N-type substrate (N... - Substrate.

[0058] The dimensions of the first trench 211 and the second trench 212 can be determined according to the device to be formed later. For example, if the first trench 211 is used to form an SBR device and the second trench 212 is used to form an SGT MOS device, the first trench 211 and the second trench 212 can be formed according to the design dimensions.

[0059] Reference Figure 4 An initial field oxygen dielectric film 221 is formed, which covers the bottom and sidewall surfaces of the first trench 211 and the second trench 212 and has a cavity region, in which the shielding electrode 222 is filled.

[0060] The material of the initial field oxygen dielectric film 221 can be a dielectric material, such as a stack of oxides and nitrides, oxides, nitrides, or other suitable dielectric materials.

[0061] The material of the shielding electrode 222 can be a conductive material, such as polycrystalline silicon or other suitable conductive materials.

[0062] Furthermore, an active electrode connection structure can be formed to electrically lead out the shielding electrode 222.

[0063] Reference Figure 5 A portion of the shielding electrode 222 is removed, as well as the initial field oxygen dielectric film 221 surrounding the removed portion of the shielding electrode 222.

[0064] In a specific implementation, the shielding electrode 222 and the initial field oxygen dielectric film 221 of the same thickness can be removed, for example, by using the same etching process.

[0065] Specifically, a dry etching method can be used to remove a portion of the thickness of the shielding electrode 222 and a portion of the thickness of the initial field oxygen dielectric film 221 from top to bottom.

[0066] Reference Figure 6 A field oxygen dielectric film 223 is deposited, which covers the remaining initial field oxygen dielectric film 221 and the shielding electrode 222. A portion of the field oxygen dielectric film 223 is then removed to obtain the field oxygen dielectric layer 220. Specifically, the material of the field oxygen dielectric film 223 can be the same as that of the initial field oxygen dielectric film 221 to improve the insulation effect; alternatively, the material of the field oxygen dielectric film 223 can be different from that of the initial field oxygen dielectric film 221 to improve the stress effect.

[0067] In this embodiment of the invention, the field oxygen dielectric film 223 and the remaining initial field oxygen dielectric film 221 are combined to form the field oxygen dielectric layer 220, and the field oxygen dielectric layer 220 wraps the shielding electrode 222, which is wrapped inside the field oxygen dielectric layer 220.

[0068] It should be noted that by first depositing a thicker field oxide dielectric film 223 and then removing a portion of the field oxide dielectric film 223, the upper sidewall surface of the first trench 211 can be kept as the material of the semiconductor substrate 200 after the field oxide dielectric layer 220 is formed.

[0069] In this embodiment of the invention, by forming an initial field oxygen dielectric film 221, filling the cavity region with the shielding electrode 222, removing a portion of the shielding electrode 222, depositing a field oxygen dielectric film 223, and removing a portion of the field oxygen dielectric film 223 to obtain the field oxygen dielectric layer 220, the field oxygen dielectric layer 220 encapsulating the shielding electrode 222 can be formed in the first trench 211 and the second trench 212 using the same process, which effectively improves process efficiency and reduces process cost.

[0070] Reference Figure 7 A first oxidation process is used to form a first initial gate oxide dielectric layer 231 on the upper sidewall surface of the first trench 211 and a second initial gate oxide dielectric layer 232 on the upper sidewall surface of the second trench 212. The thickness of the first initial gate oxide dielectric layer 231 is the same as the thickness of the second initial gate oxide dielectric layer 232.

[0071] The first initial gate oxide dielectric layer 231 is made of an oxide, such as silicon oxide. By using a first oxidation process to oxidize the material of the semiconductor substrate 200 to form the first initial gate oxide dielectric layer 231, the thickness of the first initial gate oxide dielectric layer 231 can be effectively controlled and a better insulation quality can be obtained. Similarly, the second initial gate oxide dielectric layer 232 can be obtained.

[0072] Reference Figure 8 Remove the first initial gate oxide dielectric layer 231 (refer to) Figure 7 ).

[0073] Specifically, a patterned first mask layer 261 can be formed, which covers the second initial gate oxide dielectric layer 232 and exposes the first initial gate oxide dielectric layer 231, and then the first initial gate oxide dielectric layer 231 is removed.

[0074] Reference Figure 9 A second oxidation process is used to form a first gate oxide dielectric layer 233 on the upper sidewall surface of the first trench 211, and a second oxidation process is performed on the second initial gate oxide dielectric layer 232 to obtain a second gate oxide dielectric layer 234.

[0075] It should be noted that, in another specific embodiment of the present application, the first gate oxide dielectric layer 233 and the second gate oxide dielectric layer 234 may be formed sequentially, and there is no restriction on the formation order between the two. For example, the second gate oxide dielectric layer 234 may be formed first, and then the first gate oxide dielectric layer 233 may be formed, or the first gate oxide dielectric layer 233 may be formed first, and then the second gate oxide dielectric layer 234 may be formed.

[0076] The material of the first gate oxide dielectric layer 233 can be the same as that of the first initial gate oxide dielectric layer 231, and can be an oxide, such as silicon oxide. By employing a second oxidation process to oxidize the material of the semiconductor substrate 200 to form the first gate oxide dielectric layer 233, the thickness of the first gate oxide dielectric layer 233 can be effectively controlled, and better insulation quality can be obtained.

[0077] It should be noted that when there is a higher requirement for the thickness of the first gate oxide dielectric layer 233, the thickness can be appropriately controlled when the first oxidation process is used to form the first initial gate oxide dielectric layer 231 and the second initial gate oxide dielectric layer 232. For example, the preset thickness can be reduced based on the designed thickness of the second initial gate oxide dielectric layer 232 so that the thickness of the second initial gate oxide dielectric layer 232 after secondary oxidation is more in line with the design requirements.

[0078] When cost control is more critical, the first initial gate oxide dielectric layer 231 and the second initial gate oxide dielectric layer 232 can be formed using the designed thickness of the second initial gate oxide dielectric layer 232 during the first oxidation process. Since the thickness of the second initial gate oxide dielectric layer 232 is relatively large, the secondary increase in thickness formed during the second oxidation process is also relatively small. Since the thickness increase during the second oxidation process no longer needs to be controlled and monitored, it is beneficial to reduce production costs.

[0079] In this embodiment of the invention, a first oxidation process is used to form a first initial gate oxide dielectric layer 231 and a second initial gate oxide dielectric layer 232, and then the first initial gate oxide dielectric layer 231 is removed; then a second oxidation process is used to form a first gate oxide dielectric layer 233 on the upper sidewall surface of the first trench 211, and the second initial gate oxide dielectric layer 232 is subjected to secondary oxidation to obtain a second gate oxide dielectric layer 234. Using the scheme of this embodiment of the invention, a thinner first gate oxide dielectric layer 233 can be obtained through the oxidation process. Compared with other processes (such as deposition processes), a gate oxide dielectric layer 233 of better quality can be formed. By using secondary oxidation after removing the first initial gate oxide dielectric layer 231, a thinner first gate oxide dielectric layer 233 can be formed in the device (such as an SBR device) formed in the first trench 211; and the second gate oxide dielectric layer 234 formed by secondary oxidation also has better density and electrical isolation characteristics.

[0080] Reference Figure 10 A gate electrode material is filled on the surface of the field oxygen dielectric layer 220 in the first trench 211 to form a first initial gate electrode 241, and a second gate electrode 242 is formed on the surface of the field oxygen dielectric layer 220 in the second trench 212.

[0081] The gate electrode material can be a conductive material, such as polycrystalline silicon or other suitable conductive materials.

[0082] Reference Figure 11 A portion of the first initial gate electrode 241 is removed, as well as the first gate oxide dielectric layer 233 surrounding the removed portion of the first initial gate electrode 241, to expose the upper half of the upper sidewall surface of the first trench 211 (as circled in dashed).

[0083] In a specific implementation, the first initial gate electrode 241 and the first gate oxide dielectric layer 233 of the same thickness can be removed, for example, by using the same etching process.

[0084] Specifically, a patterned second mask layer 262 can be formed, which covers the second gate electrode 242 and exposes the first initial gate electrode 241, and then the first initial gate electrode 241 is removed.

[0085] Specifically, a dry etching method can be used to remove a portion of the thickness of the first initial gate electrode 241 and a portion of the thickness of the first gate oxide dielectric layer 233 from top to bottom.

[0086] Reference Figure 12 The first trench 211 is filled with gate electrode material 243 to form the first gate electrode 240.

[0087] It should be noted that when processing the first trench 211, the second mask layer 262 covering the second trench 212 and its internal structure can be retained to effectively protect the completed device in the second trench 212.

[0088] The gate electrode material 243 may be the same as the material forming the first initial gate electrode 241 to improve the conductivity of the device; the gate electrode material 243 may also be different from the material forming the first initial gate electrode 241 to meet other characteristic requirements of the device while ensuring that the conductivity of the device meets the requirements.

[0089] Reference Figure 13 A first well region 272 and a first source region 271 can be formed in the semiconductor substrate 200 on the side of the first trench 211 to form a super barrier rectifier SBR device; wherein, the first source region 271 covers a part of the first well region 272, the first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233.

[0090] Non-limiting, the first source region 271 can be formed by performing a first type of ion implantation, for example, implanting N-type ions to form an N-type heavily doped (N... + First source region 271.

[0091] Non-limiting, the first well region 272 can be formed by performing a second type of ion implantation, for example, implanting P-type ions to form a lightly doped P-type region (P-type ions). - First pit region 272.

[0092] The method of forming the semiconductor structure may further include: forming a first body region 273 in a semiconductor substrate 200 on the side of the first trench 211; wherein the first body region 273 partially surrounds the first well region 272, and the first source region 271 covers a portion of the first body region 273.

[0093] Non-limiting, the first body region 273 can be formed by performing a second type of ion implantation, for example, implanting P-type ions to form a heavily P-type doped region (P... + First pit region 272.

[0094] In this embodiment of the invention, a first well region 272 and a first source region 271 are formed to form a super barrier rectifier SBR device. The first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233. This allows the SBR device to achieve SBR device turn-on / off without relying on the source contact hole structure to provide gate control voltage, while effectively reducing the leakage current between the first well region 272 and the first gate electrode 240 and improving device quality.

[0095] It should be noted that other suitable structures can also be used to form SBR devices, such as increasing or decreasing appropriate doping regions.

[0096] The method for forming the semiconductor structure may further include: forming a source contact hole structure 251 in a semiconductor substrate 200 on the side of the first trench 211; wherein the first source region 271 surrounds or partially surrounds the source contact hole structure 251 and is electrically connected to the source contact hole structure 251; the first well region 272 partially surrounds the source contact hole structure 251 and is electrically connected to the source contact hole structure 251. The gate control voltage can be provided via the metal layer 280.

[0097] In this embodiment of the invention, the device formed within the first trench 211 can directly obtain the gate control voltage provided by the source contact hole structure 251 located on the side of the first trench 211 without being isolated by the first gate oxide layer 233, thus eliminating the need for an additional source contact hole structure (such as...). Figure 1 The SBR source contact hole structure 252 shown provides a gate control voltage, which enables control (such as turning on / off) of the device formed in the first trench 211.

[0098] Furthermore, the method for forming the semiconductor structure further includes forming one or more of the following in the semiconductor substrate 200 on the side of the second trench 212 to form an SGT MOS device: a second body region 276, a second well region 275, and a second source region 274; wherein the second source region 274 covers a portion of the second well region 275, the second source region 274 and the second gate electrode 242 are electrically isolated by the second gate oxide dielectric layer 234, the second well region 275 and the second gate electrode 242 are electrically isolated by the second gate oxide dielectric layer 234, the second body region 276 partially surrounds the second well region 275, and the second source region 274 covers a portion of the second body region 276.

[0099] Non-limiting, the second source region 274 can be formed by performing a first type of ion implantation, for example, implanting N-type ions to form an N-type heavily doped (N... +The second source region 274; a second well region 275 can also be formed by performing a second type of ion implantation, for example, implanting P-type ions to form a lightly doped P-type well region (P... - The second well region 275; a second body region 276 can also be formed by performing a second type of ion implantation, for example, implanting P-type ions to form a heavily P-type doped region (P... + Second body area 276.

[0100] It should be noted that other suitable structures can also be used to form SGT MOS devices, such as increasing or decreasing appropriate doping regions.

[0101] It is understood that although the first body region 273 and the second body region 276 are used in this application to represent the body area in the SBR device and the SGT MOS device, respectively, in specific implementations, the first body region 273 and the second body region 276 can be formed together using the same process to reduce process costs and improve production efficiency. Similarly, the first source region 271 and the second source region 274 can also be formed together using the same process, and the first well region 272 and the second well region 275 can also be formed together using the same process.

[0102] Reference Figure 14 , Figure 14 This is a schematic diagram of the working scenario of an SBR device in an embodiment of the present invention.

[0103] like Figure 14 As shown, since the first gate electrode 240 is in contact with the upper half of the upper sidewall surface of the first trench 211 (such as the area circled in the dashed circle), the first gate electrode 240 is electrically connected to the first source region 271 and to the source contact hole structure 251. That is, the first gate electrode 240, the first source region 271 and the source contact hole structure 251 are at the same potential.

[0104] In this embodiment of the invention, the SBR device can directly obtain the gate control voltage provided by the source contact hole structure 251 located on the side of the first trench 211 without being isolated by the first gate oxide dielectric layer 233. Thus, the gate control function of the SBR device can be realized without relying on an additional source contact hole structure to provide the gate control voltage.

[0105] In a non-limiting sense, when the gate control voltage is greater than or equal to a preset threshold voltage, carrier flow as shown by the dashed arrow can be achieved, thus turning on the SBR device. For example, for positive carriers, the arrow direction can be upward, and for negative carriers, the arrow direction can be downward.

[0106] Understandably, since the voltage drop of the SBR device is smaller than that of the SGT MOS device, the improvement in reverse power consumption is more significant, effectively improving device performance.

[0107] In this embodiment of the invention, a first gate oxide dielectric layer 231 and a first initial gate electrode 241 are formed on the upper sidewall surface of the first trench 211, and a second gate oxide dielectric layer 232 and a second gate electrode 242 are formed on the upper sidewall surface of the second trench 212. A portion of the first initial gate electrode 241 is removed, and the first gate oxide dielectric layer 233 surrounding the removed portion of the first initial gate electrode 241 is also removed to expose the upper half of the upper sidewall surface of the first trench 241. Then, gate electrode material is filled into the first trench 241 to form a first gate electrode 240. A thinner first gate oxide dielectric layer 231 can be formed in the first trench 241, and the upper half of the upper sidewall surface of the first trench 211 is also formed. The first gate electrode 240 with contact allows the device formed in the first trench 211 to directly obtain the gate control voltage provided by the source contact hole structure 251 located on the side of the first trench 211 without being isolated by the first gate oxide layer 233. Thus, the device formed in the first trench 211 can be controlled (e.g., turned on / off) without relying on an additional source contact hole structure to provide the gate control voltage. Compared with the prior art, which requires an additional source contact hole structure to be formed on the gate electrode surface in the SBR device to provide the gate control voltage, resulting in a large number of source contact hole structures, the solution of this embodiment can reduce the number of source contact hole structures 251 required, effectively overcome the size limitations of semiconductor devices, and reduce production costs.

[0108] In this embodiment of the invention, a semiconductor structure is also disclosed, with reference to... Figure 13 The device may include: a semiconductor substrate 200; a first trench 211 and a second trench 212 located within the semiconductor substrate 200; a field oxide dielectric layer 220 and a shielding electrode 222 encapsulated within the field oxide dielectric layer 220, the field oxide dielectric layer 220 being located at the bottom and lower sidewall surfaces of the first trench 211 and the second trench 212; a first gate oxide dielectric layer 233 located on the surface of a portion of the upper sidewall of the first trench 211; a second gate oxide dielectric layer 234 located on the surface of the upper sidewall of the second trench 212, wherein the thickness of the first gate oxide dielectric layer 233 is less than the thickness of the second gate oxide dielectric layer 234; a first gate electrode 240 located on the surface of the field oxide dielectric layer 220 within the first trench 211 and in contact with the upper half of the upper sidewall surface of the first trench 211; and a second gate electrode 242 located on the surface of the field oxide dielectric layer 220 within the second trench 212.

[0109] Furthermore, the semiconductor structure may also include a first well region 272 and a first source region 271, located in the semiconductor substrate 200 on the side of the first trench 211 to form an SBR device; wherein the first source region 271 covers a portion of the first well region 272, the first source region 271 is electrically connected to the first gate electrode 240, and the first well region 272 and the first gate electrode 240 are electrically isolated by the first gate oxide dielectric layer 233.

[0110] Furthermore, the semiconductor structure may also include: a source contact hole structure 251 located in the semiconductor substrate 200 on the side of the first trench 211; wherein, the first source region 271 surrounds or partially surrounds the source contact hole structure 251 and is electrically connected to the source contact hole structure 251; the first well region 272 partially surrounds the source contact hole structure 251 and is electrically connected to the source contact hole structure 251.

[0111] Furthermore, the semiconductor structure may also include: a first body region 273 located in the semiconductor substrate 200 on the side of the first trench 211; wherein the first body region 273 partially surrounds the first well region 272, and the first source region 271 covers a portion of the first body region 273.

[0112] Furthermore, the semiconductor structure may also include one or more of a second body region 276, a second well region 275, and a second source region 274, located in the semiconductor substrate 200 on the side of the second trench 212 to form an SGT MOS device; wherein the second source region 274 covers a portion of the second well region 275, the second source region 274 and the second gate electrode 242 are electrically isolated by the second gate oxide dielectric layer 234, the second well region 275 and the second gate electrode 242 are electrically isolated by the second gate oxide dielectric layer 234, the second body region 276 partially surrounds the second well region 275, and the second source region 274 covers a portion of the second body region 276.

[0113] Furthermore, both the SBR device and the SGT MOS device in the semiconductor structure are located in the cell region.

[0114] In this embodiment of the invention, by setting both the SBR device and the SGT MOS device to be located in the cell region, the integration of SBR devices and SGT MOS devices under all cell sizes can be compatible, and the withstand voltage problem caused by different trenches (such as the first trench 211 and the second trench 212) can be solved.

[0115] For the principles, specific implementation, and beneficial effects of this semiconductor structure, please refer to the previous description of the semiconductor structure formation method, which will not be repeated here.

[0116] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0117] In the embodiments of this application, "multiple" refers to two or more.

[0118] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first trench and a second trench are formed in the semiconductor substrate; A field oxygen dielectric layer is formed at the bottom and lower sidewall surface of the first and second trenches, and a shielding electrode is formed inside the field oxygen dielectric layer. A first gate oxide dielectric layer is formed on the upper sidewall surface of the first trench, and a second gate oxide dielectric layer is formed on the upper sidewall surface of the second trench, wherein the thickness of the first gate oxide dielectric layer is less than the thickness of the second gate oxide dielectric layer. A gate electrode material is filled on the surface of the first trench inner field oxygen dielectric layer to form a first initial gate electrode, and a second gate electrode is formed on the surface of the second trench inner field oxygen dielectric layer. A portion of the first initial gate electrode is removed, and a first gate oxide dielectric layer surrounding the removed portion of the first initial gate electrode is removed, to expose the upper half of the upper sidewall surface of the first trench; The first trench is filled with gate electrode material to form a first gate electrode; A first well region and a first source region are formed in a semiconductor substrate on the side of the first trench; wherein the first source region covers a portion of the first well region, the first source region is electrically connected to the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer. A source contact hole structure is formed in the semiconductor substrate on the side of the first trench; wherein, the first source region surrounds or partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure; the first well region partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: A first body region is formed in the semiconductor substrate on the side of the first trench; The first body region partially surrounds the first well region, and the first source region covers a portion of the first body region.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: One or more of the following are formed in the semiconductor substrate on the side of the second trench to form a split-gate field-effect transistor (SGT) MOS device: a second body region, a second well region, and a second source region; Wherein, the second source region covers a portion of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region partially surrounds the second well region, and the second source region covers a portion of the second body region.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, A field oxygen dielectric layer is formed on the bottom and lower sidewall surface of the first and second trenches, and a shielding electrode is formed encapsulated within the field oxygen dielectric layer, comprising: An initial field oxygen dielectric film is formed, which covers the bottom and sidewall surfaces of the first and second trenches and has a cavity region; The shielding electrode is filled into the cavity region; Remove a portion of the shielding electrode, and remove the initial field oxygen dielectric film surrounding the removed portion of the shielding electrode; A field oxygen dielectric film is deposited, which covers the remaining initial field oxygen dielectric film and the shielding electrode; A portion of the field oxygen dielectric film is removed to obtain the field oxygen dielectric layer.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, Forming a first gate oxide dielectric layer on the upper sidewall surface of the first trench and forming a second gate oxide dielectric layer on the upper sidewall surface of the second trench, comprising: A first oxidation process is used to form a first initial gate oxide dielectric layer on the upper sidewall surface of the first trench and a second initial gate oxide dielectric layer on the upper sidewall surface of the second trench, wherein the thickness of the first initial gate oxide dielectric layer is the same as the thickness of the second initial gate oxide dielectric layer. Remove the first initial gate oxide dielectric layer; A second oxidation process is used to form a first gate oxide dielectric layer on the upper sidewall surface of the first trench, and the second initial gate oxide dielectric layer is subjected to secondary oxidation to obtain a second gate oxide dielectric layer.

6. A semiconductor structure, characterized in that, include: Semiconductor substrate; The first trench and the second trench are located in the semiconductor substrate; The field oxygen dielectric layer and the shielding electrode wrapped inside the field oxygen dielectric layer, wherein the field oxygen dielectric layer is located at the bottom and lower sidewall surface of the first trench and the second trench; The first gate oxide dielectric layer is located on the surface of a portion of the upper sidewall of the first trench; The second gate oxide dielectric layer is located on the upper sidewall surface of the second trench, wherein the thickness of the first gate oxide dielectric layer is less than the thickness of the second gate oxide dielectric layer. The first gate electrode is located on the surface of the field oxygen dielectric layer in the first trench and is in contact with the upper half of the upper sidewall surface of the first trench. The second gate electrode is located on the surface of the field oxygen dielectric layer within the second trench; A first well region and a first source region are located in a semiconductor substrate on the side of the first trench; wherein, the first source region covers a portion of the first well region, the first source region is electrically connected to the first gate electrode, and the first well region and the first gate electrode are electrically isolated by the first gate oxide dielectric layer. A source contact hole structure is located in a semiconductor substrate on the side of the first trench; wherein, the first source region surrounds or partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure; the first well region partially surrounds the source contact hole structure and is electrically connected to the source contact hole structure.

7. The semiconductor structure according to claim 6, characterized in that, Also includes: The first body region is located in the semiconductor substrate on the side of the first trench; The first body region partially surrounds the first well region, and the first source region covers a portion of the first body region.

8. The semiconductor structure according to claim 6, characterized in that, Also includes: One or more of the second body region, the second well region, and the second source region are located in the semiconductor substrate on the side of the second trench to form a split-gate field-effect transistor (SGT) MOS device. Wherein, the second source region covers a portion of the second well region, the second source region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second well region and the second gate electrode are electrically isolated by the second gate oxide dielectric layer, the second body region partially surrounds the second well region, and the second source region covers a portion of the second body region.

9. The semiconductor structure according to claim 6, characterized in that, Both the SBR device and the SGT MOS device in the semiconductor structure are located in the cell region.

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