Power module and packaging method thereof
By optimizing the packaging process through silver-coated copper foil layers, sintering molds, and ultrasonic welding technology, the problems of poor welding precision and consistency in traditional packaging have been solved, achieving high-efficiency silicon carbide chip packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN BASIC SEMICON LTD
- Filing Date
- 2022-12-27
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional packaging processes, such as solder paste reflow soldering, result in low soldering position accuracy, low process yield, and poor process consistency, making it difficult to meet the packaging requirements of silicon carbide chips in high-power and high-temperature environments.
By employing a silver-coated copper foil layer, sintering mold, and ultrasonic welding technology, combined with a soft material layer and a protective layer, a silver sintered layer is formed through a single sintering process. Copper needles are used as signal and current needles, and the packaging process is optimized to eliminate the reflow soldering step.
It improves the heat dissipation and conductivity of the connection layer, reduces thermal resistance, enhances positioning accuracy and process yield, reduces hardware investment and electrical connection material costs, and solves the accuracy and consistency problems in traditional processes.
Smart Images
Figure CN116053144B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a power module and its packaging method. Background Technology
[0002] With the rapid development of technologies such as aerospace and new energy power generation, the performance requirements for power electronic systems are also increasing. Developing high-power device chips for use in extreme environments such as high temperatures is a key focus in the current field of power electronics technology. For example, semiconductor device chips represented by silicon carbide (SiC) materials are a major research trend.
[0003] With the increasingly widespread application of silicon carbide (SiC) chips, these chips are required to operate at higher power and higher temperatures, posing greater challenges to the packaging process of high-power chips like SiC. Packaging is a post-production process in semiconductor manufacturing, aiming to ensure that the packaged chip possesses strong mechanical properties, good electrical properties, and excellent heat dissipation performance. It provides mechanical and environmental protection for the chip, ensuring its efficient and stable operation. Traditional packaging processes typically include a reflow soldering step. The solder used in reflow soldering is mostly solder paste, which melts and flows during the process, easily leading to problems such as low soldering accuracy, low process yield, and poor process consistency. Summary of the Invention
[0004] In view of this, this application proposes a power module packaging method to solve at least one of the above problems.
[0005] One embodiment of this application provides a method for packaging a power module, comprising the following steps:
[0006] The mounting step involves mounting components on a substrate. The substrate has a conductor layer on its surface, and the components are mounted on the conductor layer. The components include chips, and a silver paste copper foil layer is disposed at the source level of the chip. The silver paste copper foil layer includes a silver paste layer and a copper foil layer stacked together, with the silver paste layer located between the chip and the copper foil layer.
[0007] The sintering step involves sintering using a sintering mold, which includes an upper sintering mold and a lower sintering mold. The substrate is placed on the lower sintering mold, and a soft material layer and a protective layer are sequentially deposited on the surface of the component facing away from the substrate. The upper sintering mold is located on the side of the protective layer facing away from the soft material layer. After sintering, both the conductor layer and the silver paste layer form sintered layers.
[0008] In the wire bonding step, copper wires are used to connect the source stage of the chip to the substrate, and aluminum wires are used to connect the gate stage of the chip to the substrate.
[0009] The ultrasonic welding step involves ultrasonically welding copper pins to areas of the substrate where the components are not located; and
[0010] In the potting step, the substrate is placed in a housing with a first opening and a second opening. The copper pin extends out from the first opening. Silicone is poured in from the second opening under vacuum and then heated and cured to complete the encapsulation of the power module.
[0011] In one embodiment, the components further include a thermistor and a gate resistor.
[0012] In one embodiment, the sintering upper mold includes a body and a first pressure joint, a second pressure joint, and a third pressure joint protruding from the body. The first, second, and third pressure joints protrude from the body at different heights. The first pressure joint corresponds to the thermistor, the second pressure joint corresponds to the chip, and the third pressure joint corresponds to the gate resistor.
[0013] In one embodiment, the sintering pressure in the sintering step is 15 MPa to 30 MPa, the sintering temperature is above 200°C, and the sintering time is 3 min to 10 min.
[0014] In one embodiment, the conductor layer is made of silver or gold.
[0015] In one embodiment, the thickness of the silver-coated copper foil layer is 45μm to 55μm, and the thickness of the silver paste layer is 30μm to 40μm.
[0016] In one embodiment, the thickness of the soft material layer is 5 to 10 times the thickness of the silver-coated copper foil layer.
[0017] In one embodiment, the soft material layer is made of silicone film, polytetrafluoroethylene, or graphite.
[0018] In one embodiment, the protective layer is made of polytetrafluoroethylene.
[0019] In one embodiment, the substrate is a ceramic copper-clad laminate. The ceramic copper-clad laminate includes a ceramic layer and a metallic copper layer disposed on the ceramic layer, wherein the conductive layer is disposed on the surface of the metallic copper layer opposite to the ceramic layer.
[0020] One embodiment of this application provides a power module, which includes:
[0021] A power device, comprising a substrate and components disposed on the substrate and copper pins; the components and the substrate are connected by a sintering layer, the components including a chip, the source stage of the chip being connected to the substrate by copper wires, and the gate stage of the chip being connected to the substrate by aluminum wires.
[0022] A package that covers the surface of the power device to encapsulate the power device; and
[0023] A housing that houses the power device and the package, the housing including a first opening through which the copper needle extends.
[0024] This application performs a single sintering process on the top and bottom surfaces of the chip to form a silver sintered layer as a bonding layer, improving the heat dissipation, conductivity, and mechanical properties of the bonding layer. Furthermore, this application utilizes sintering molds with pressure connectors of different heights to balance the height differences between components. A soft material layer is used to balance the height difference between the gate and source levels of the chip caused by the silver paste copper foil layer, thereby achieving single-stage sintering of components (e.g., the chip) and reducing the thermal resistance of the silver sintered layer. Additionally, this application uses copper pins of the same design as signal and current pins, reducing hardware investment in the manufacturing process. The use of ultrasonic welding of the copper pins ensures high positional accuracy and good connection, improving the current carrying capacity of the current pins and reducing the cost of electrical connection materials. Through optimized process design, this application achieves de-reflow soldering and desoldering throughout the packaging process, breaking through the technical barriers of traditional processes and solving the problems of low positional accuracy, low process yield, and poor process consistency associated with traditional reflow soldering. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a structure for mounting components on a substrate according to one embodiment of this application.
[0026] Figure 2 This is a schematic diagram of a sintering step provided in one embodiment of this application.
[0027] Figure 3 This is a cross-sectional schematic diagram of the chip and the silver-coated copper foil layer provided in one embodiment of this application.
[0028] Figure 4 This is a schematic diagram of a metal wire bonding structure provided in one embodiment of this application.
[0029] Figure 5 This is a schematic diagram of a substrate ultrasonically welded according to an embodiment of this application.
[0030] Figure 6 This is a schematic diagram of a substrate potting structure provided in one embodiment of this application.
[0031] Explanation of main component symbols
[0032] Substrate 10
[0033] Ceramic layer 11
[0034] Copper layer 12
[0035] Conductor layer 13
[0036] Components 20
[0037] Chip 21
[0038] Thermistor 22
[0039] Gate resistor 23
[0040] 24 layers of silver-coated copper foil
[0041] Silver paste layer 241
[0042] Copper foil layer 242
[0043] sintering mold 30
[0044] Sintering upper mold 31
[0045] Sintering lower mold 32
[0046] Soft material layer 40
[0047] Protective layer 50
[0048] Ontology 310
[0049] First crimp connector 311
[0050] Second crimp connector 312
[0051] Third crimp connector 313
[0052] Copper wire 60
[0053] 70 aluminum wire
[0054] Copper needle 80
[0055] 90% of the outer casing
[0056] First opening 91
[0057] Second opening 92
[0058] Power Module 100
[0059] The following detailed description, in conjunction with the accompanying drawings, further illustrates the embodiments of this application. Detailed Implementation
[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application.
[0061] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0062] It will be understood that when a layer is referred to as being "on" another layer, it can be directly on that other layer or there can be intermediate layers in between. Conversely, when a layer is referred to as being "directly" on another layer, there are no intermediate layers.
[0063] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0064] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0065] Please see Figures 1 to 5 One embodiment of this application provides a packaging method for a power module 100, including steps S10 to S50.
[0066] like Figure 1 As shown, step S10: mounting step, mounting components 20 on substrate 10.
[0067] In this embodiment, the substrate 10 is a ceramic copper-clad laminate. The ceramic copper-clad laminate can be a direct bonding copper-ceramic substrate (DBC) or an active metal brazing ceramic substrate (AMB), etc., and this application is not limited thereto. Figure 2 As shown, the substrate 10 includes a ceramic layer 11 and a copper layer 12 disposed on the ceramic layer 11. A conductor layer 13 is partially disposed on the surface of the copper layer 12 facing away from the ceramic layer 11. The component 20 is disposed on the surface of the conductor layer 13. The conductor layer 13 may be, but is not limited to, silver or gold. In this embodiment, the conductor layer 13 is silver.
[0068] Please also refer to Figure 2 In this embodiment, the component 20 includes a chip 21, a thermistor 22, and a gate resistor 23. In other embodiments, other components can be added or replaced as needed. During mounting, a conductor layer 13 (silver in this embodiment) can also be formed on the surfaces of the chip 21, the thermistor 22, and the gate resistor facing the substrate 10. Then, the conductor layer 13 on the surface of the substrate 10 and the conductor layer 13 on the surface of the component 20 are heated by a soldering head, and the component 20 is mounted on the surface of the substrate 10 through the connection effect of the conductor layer 13. Then, a silver paste copper foil layer 24 is formed on the source stage (not shown) of the chip 21, such as... Figure 3 As shown, the silver paste copper foil layer 24 includes a silver paste layer 241 and a copper foil layer 242 stacked together, with the silver paste layer 241 located between the chip 21 and the copper foil layer 242.
[0069] In some embodiments, the thickness of the silver-coated copper foil layer 24 is relatively thin, approximately 45 μm to 55 μm, and the thickness of the silver paste layer 241 is approximately 30 μm to 40 μm. In this embodiment, the thickness of the silver-coated copper foil layer 24 is 50 μm.
[0070] Please continue reading. Figure 2 Step S20: Sintering step. It is understood that the chip 21, thermistor 22 and gate resistor 23 are all sinterable devices that are resistant to high temperature (above 200℃) and high voltage (greater than 15Mpa).
[0071] The sintering process densifies the silver powder particles (which can be at the nano or micro-nano level) in the conductor layer 13 and the silver paste layer 241 to form a relatively dense sintered layer with low porosity (not shown in the figure). In this embodiment, the sintered layer is a silver sintered layer. The pore size of the silver sintered layer is at the micron and nanometer level. With a porosity of 10%, its thermal and electrical conductivity can reach 90% of that of pure silver, which is much higher than that of ordinary soft solder. The silver sintered layer is a good mechanical connection layer with excellent electrical and thermal conductivity (the thermal conductivity of the silver sintered layer can reach about 1.4 to 2 W / cm / ℃), a high melting point, and can withstand operating temperatures above 710℃, making it an ideal structure for power device chip packaging. Furthermore, the melting point of the silver sintered layer is the melting point of silver (961℃). If secondary soldering is required, a higher temperature solder can be selected for the secondary soldering, which can significantly improve the temperature resistance and high-temperature reliability of the interconnect, and greatly expand the selection range of secondary solder joints.
[0072] In this embodiment, sintering is performed using a sintering mold 30, which includes an upper sintering mold 31 and a lower sintering mold 32. The substrate 10 is placed on the lower sintering mold 32, and a soft material layer 40 and a protective layer 50 are sequentially disposed on the surface of the component 20 facing away from the substrate 10. The upper sintering mold 31 is located on the side of the protective layer 50 facing away from the soft material 40.
[0073] In some embodiments, such as Figure 2 As shown, the sintering upper mold 31 includes a body 310 and a first pressure joint 311, a second pressure joint 312, and a third pressure joint 313 protruding from the body 310 with different heights. The first pressure joint 311, the second pressure joint 312, and the third pressure joint 313 protrude from the body 310 at different heights. The first pressure joint 311 corresponds to the thermistor 22, the second pressure joint 312 corresponds to the chip 21, and the third pressure joint 313 corresponds to the gate resistor 23. It can be understood that the pressure joint with a higher height will correspond to components with a smaller height (thickness), and the pressure joint with a smaller height will correspond to components with a larger height (thickness), in order to balance the height difference between the components, thereby enabling the chip and other components to be sintered on their upper and lower surfaces in one step. For example, in this embodiment, the thermistor 22 has the greatest thickness, so the thermistor 22 will correspond to the first crimp connector 311 with the smallest height; the thickness of the chip 21 and the gate resistor 23 are not much different, so the heights of the second crimp connector 312 and the third crimp connector 313 corresponding to the chip 21 and the gate resistor 23 are also not much different.
[0074] In some embodiments, the sintering pressure in the sintering step is 15 MPa to 30 MPa, the sintering temperature is above 200°C, and the sintering time is 3 min to 10 min. This accelerates the sintering of the silver solder and results in a sintered layer with good thermoelectric and mechanical properties. However, excessive pressure may damage the chip 21 to some extent and requires a larger economic investment, which is detrimental to cost control.
[0075] In some embodiments, the soft material layer 40 may be made of materials with high porosity, such as silicone film, polytetrafluoroethylene (PTFE), or graphite. Because the source stage of chip 21 has a silver-coated copper foil layer 24 while the gate stage does not, there is a certain height difference between the gate and source stages. The soft material layer 40 can balance this height difference. Furthermore, the thickness of the soft material layer 40 can be adjusted according to the thickness of the silver-coated copper foil layer 24, generally 5 to 10 times the thickness of the silver-coated copper foil layer 24. Different materials shrink differently, so the multiple will also vary and can be adjusted according to actual conditions.
[0076] In some embodiments, the protective layer 50 may be made of, but is not limited to, polytetrafluoroethylene (PTFE). The protective layer 50 can prevent the soft material layer 40 from contaminating the component 20 (such as the chip 21) or the sintering mold 30.
[0077] like Figure 4 As shown, step S30: wire bonding step. Copper wire 60 is used to connect the source stage of the chip 21 and the substrate 10 (copper layer 12), and aluminum wire 70 is used to connect the gate stage of the chip 21 and the substrate 10 (copper layer 12).
[0078] Compared to using aluminum wires to connect the source stage of chip 21, using copper wires 60 to connect the source stage of chip 21 can improve the lifespan of the power module because copper wires 60 have stronger current carrying and heat dissipation capabilities than aluminum wires, which are prone to stress fatigue when carrying large currents. Using aluminum wires 70 to connect the gate stage of chip 21 avoids the above problems because the gate current is relatively small, making aluminum wire connections suitable. Since the source stage of chip 21 has a silver-coated copper foil layer 24, this layer prevents excessive bonding force during copper wire bonding, which could damage chip 21.
[0079] like Figure 5 As shown, step S40: ultrasonic welding step, the copper needle 80 is ultrasonically welded to the area of the substrate 10 where the component 20 is not set.
[0080] In this embodiment, the copper needle 80 is welded to the area of the copper layer 12 where the component 20 is not located by torque ultrasonic welding. The principle of torque welding is to transmit the energy generated by the ultrasonic generator (not shown) to the welding joint (not shown) in a torque vibration manner with a center point as the center. The torque vibration is then applied to the surface of the workpiece to be welded (substrate 10 in this embodiment) through the welding joint, causing friction between the substrate 10 and the welding joint. At the same time, the ultrasonic waves cause the copper particles of the copper layer 12 at the interface to vibrate and form a connection, achieving a molecular-level welding effect and reducing the thermal resistance of the connection between the copper needle 80 and the substrate 10. Since torque welding requires a rotational torque on the surface of the workpiece to be welded, the welding efficiency is improved. The welding position of the copper needle 80 can be confirmed by means of image recognition, thereby improving the accuracy of the welding position and the process yield.
[0081] The copper pin 80 can be used to connect to an external printed circuit board (PCB). When the copper pin 80 is used to output a signal and connect to the PCB, it acts as a signal pin; when the copper pin 80 is used as an output terminal and connected to the PCB, it acts as a current pin. Since the copper pin 80 can function as both a signal pin and a current pin, there is no need to additionally provide copper terminals on the substrate 10, which reduces the investment in hardware manufacturing.
[0082] like Figure 6 As shown, step S50: potting step.
[0083] In this embodiment, a ring of sealant (not shown) is first applied around the periphery of the substrate 10. Then, the substrate 10 with the sealant applied is placed inside the housing 90, and the sealant is cured by heat. The housing 90 has a first opening 91 and a second opening 92. The diameter of the first opening 91 is smaller than the diameter of the second opening 92, and the second opening 92 is approximately located at the center of the housing 90. There are multiple first openings 91, and the copper pin 80 extends from each of the first openings 91. After degassing the silicone (not shown), the silicone is injected through the second opening 92 under vacuum, and then cured by heat to complete the encapsulation of the power module 100. Curing the silicone under vacuum reduces air bubbles inside the silicone and improves its insulation performance.
[0084] like Figure 6 As shown, one embodiment of this application provides a power module 100, which includes a power device, a package, and a housing 90.
[0085] like Figure 1 , Figure 4 and Figure 5 As shown, the power device includes a substrate 10, components 20 disposed on the substrate 10, and copper pins 80. The components 20 and the substrate 10 are connected by a sintered layer (not shown). The components 20 include a chip 21, the source stage of which is connected to the substrate 10 (copper layer 12) via copper wires 60, and the gate stage of which is connected to the substrate 10 (copper layer 12) via aluminum wires 70. The package covers the surface of the power device to encapsulate it. In this embodiment, the package is formed by heating and curing silicone. Figure 5 As shown, the housing 90 houses the power device and the package. The housing 90 includes a first opening 91 through which the copper pin 80 extends.
[0086] This application performs a single sintering process on the upper and lower surfaces of chip 21 to form a silver sintered layer as a connection layer, improving the heat dissipation, conductivity, and mechanical properties of the connection layer. This application also uses sintering molds 30 with different height pressure connectors to balance the height differences of the components 20, and utilizes a soft material layer 40 to balance the height difference between the gate and source levels of chip 21 caused by the silver paste copper foil layer 24. This allows for a single sintering of the components 20 (e.g., chip 21) from top to bottom, reducing the thermal resistance of the silver sintered layer. Furthermore, this application uses copper pins 80 of the same design as signal pins and current pins, reducing hardware investment in the manufacturing process. The use of ultrasonic welding of the copper pins 80 ensures high positional accuracy and good connection effect, improving the current carrying capacity of the current pins and reducing the cost of electrical connection materials. Through optimized process design, this application achieves de-reflow soldering and desoldering throughout the packaging process, breaking through the technical barriers of traditional processes and solving the problems of low positional accuracy, low process yield, and poor process consistency in traditional reflow soldering.
[0087] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.
Claims
1. A packaging method of a power module, characterized by, Includes the following steps: The mounting step involves mounting components on a substrate. The substrate has a conductor layer on its surface, and the components are mounted on the conductor layer. The components include chips, and a silver paste copper foil layer is disposed at the source of the chip. The silver paste copper foil layer includes a stacked silver paste layer and a copper foil layer, with the silver paste layer located between the chip and the copper foil layer. The sintering step involves sintering using a sintering mold, which includes an upper sintering mold and a lower sintering mold. The substrate is placed on the lower sintering mold, and a soft material layer and a protective layer are sequentially deposited on the surface of the component facing away from the substrate. The upper sintering mold is located on the side of the protective layer facing away from the soft material layer. After sintering, both the conductor layer and the silver paste layer form sintered layers. In the wire bonding step, copper wires are used to connect the source of the chip to the substrate, and aluminum wires are used to connect the gate of the chip to the substrate. The ultrasonic welding step involves ultrasonically welding copper pins to areas of the substrate where no components are located. and In the potting step, the substrate is placed in a housing with a first opening and a second opening. The copper pin extends out from the first opening. Silicone is poured in from the second opening under vacuum and then heated and cured to complete the encapsulation of the power module.
2. The packaging method of a power module according to claim 1, wherein, The components also include thermistors and gate resistors.
3. The packaging method of a power module according to claim 2, wherein The sintering upper mold includes a body and a first pressure joint, a second pressure joint, and a third pressure joint protruding from the body. The first pressure joint, the second pressure joint, and the third pressure joint protrude from the body at different heights. The first pressure joint corresponds to the thermistor, the second pressure joint corresponds to the chip, and the third pressure joint corresponds to the gate resistor.
4. The packaging method of a power module according to claim 1, wherein The sintering pressure in the sintering step is 15 MPa to 30 MPa, the sintering temperature is above 200℃, and the sintering time is 3 min to 10 min.
5. The packaging method of a power module according to claim 1, wherein The conductor layer may be made of silver or gold.
6. The packaging method of a power module according to claim 1, wherein The thickness of the silver-coated copper foil layer is 45 μm to 55 μm, and the thickness of the silver paste layer is 30 μm to 40 μm.
7. The packaging method of a power module according to claim 1, wherein The thickness of the soft material layer is 5 to 10 times the thickness of the silver-coated copper foil layer.
8. The packaging method of a power module according to claim 1, wherein, The soft material layer is made of silicone film, polytetrafluoroethylene (PTFE), or graphite, and the protective layer is made of PTFE.
9. The packaging method of a power module according to claim 1, wherein, The substrate is a ceramic copper-clad laminate, which includes a ceramic layer and a metallic copper layer disposed on the ceramic layer. The conductive layer is disposed on the surface of the metallic copper layer opposite to the ceramic layer.
10. A power module produced using the encapsulating method according to any one of claims 1 to 9, characterized by The power module includes: A power device, comprising a substrate and components disposed on the substrate and copper pins; the components and the substrate are connected by a sintering layer, the components including a chip, the source of the chip being connected to the substrate by a copper wire, and the gate of the chip being connected to the substrate by an aluminum wire. A package that covers the surface of the power device to encapsulate the power device; and A housing that houses the power device and the package, the housing including a first opening through which the copper needle extends.