Method for manufacturing a silicon interposer
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
- Filing Date
- 2022-12-30
- Publication Date
- 2026-06-26
Smart Images
Figure CN116053199B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device manufacturing, and more specifically, relates to a method for preparing a silicon interposer. Background Technology
[0002] 2.5D packaging, as an advanced heterogeneous chip packaging method, enables the high-density interconnection of multiple chips into a single package. Chips using 2.5D packaging can achieve faster data input and output. For example... Figure 1 As shown, by using silicon interposer and 2.5D TSV technology to integrate memory, CPU and I / O chips onto a single substrate, the distance between them and the processor is shortened, and the transmission bandwidth is increased. This not only saves energy and cost, but also improves computing efficiency.
[0003] In 2.5D packaging, silicon interpose (Si interpose, with copper pillars formed inside the through-silicon via) is a packaging and testing technology that enables mass production. The silicon interpose is fabricated using the TSV process. First, through-silicon vias are formed in the silicon substrate. Then, silicon oxide is formed on the inner wall of the through-silicon via. Next, Cu pillars are filled into the through-silicon via. Then, a back silicon thinning process is used to expose the copper pillars (removing the silicon on the back of the Cu pillars to expose the Cu pillars and achieve conductive connection between the front and back sides). This exposes the copper pillars, which are then used as back solder joints for subsequent interconnection.
[0004] Currently, in the technology of exposing copper pillars in the whole-surface silicon thinning process (such as...) Figure 2 Dry etching is typically used, employing the chemical action of SF6 etching gas to etch silicon, which can achieve high etching rates (e.g., ...). Figure 3a ), to improve the selectivity of silicon to silicon oxide (e.g. Figure 3b ) and etching uniformity to ensure the uniformity of the copper pillar height (e.g. Figure 4a and Figure 4b However, during SF6 etching, sulfur (S) readily reacts with copper (Cu) to form CuS. Cu diffuses easily, and after diffusion, it reacts with sulfur to form a CuS micromask, which blocks etching. This leads to abnormal Cu pillars, causing Cu pillar skipping (an abnormal Cu pillar results in loss of conductivity, rendering the workpiece unable to connect). Figures 5a-5c As shown, this anomaly cannot be improved through process technology. Summary of the Invention
[0005] The purpose of this invention is to propose a method for preparing a silicon interposer plate, which avoids Cu pillar skipping abnormalities during the etching process, while ensuring the uniformity of the height and morphology of the exposed Cu pillars.
[0006] To achieve the above objectives, the present invention proposes a method for preparing a silicon interposer plate, comprising:
[0007] S1: A silicon substrate filled with an insulating layer and a conductive metal;
[0008] S2: The back side of the silicon substrate is etched using a first etching gas for a first set time. The first etching gas includes a fluorocarbon gas. During the etching process, a grid-like deposit is formed on the top of the insulating layer.
[0009] S3: The back side of the silicon substrate is etched using a second etching gas for a second set time period. The second etching gas includes a fluorocarbon gas and a processing gas, and the processing gas is used to remove the grid-like deposits.
[0010] S4: Repeat steps S2-S3 until the silicon on the back side of the silicon substrate is etched to a set depth, exposing the conductive metal from the back side of the silicon substrate.
[0011] Optionally, the flow ratio of the processing gas to the fluorocarbon gas in the second etching gas is greater than or equal to 1:10 and less than or equal to 1:4.
[0012] Optionally, the fluorocarbon gas is CF4 or C4F8.
[0013] Optionally, the processing gas includes O2.
[0014] Optionally, the first etching gas may further include a physical bombardment gas.
[0015] Optionally, the first set duration is greater than or equal to 1 second and less than or equal to 3 seconds, and / or the second set duration is approximately equal to 2 seconds and less than or equal to 5 seconds.
[0016] Optionally, the flow rate of the fluorocarbon gas in the first etching gas is in the range of 100-300 Sccm.
[0017] Optionally, the flow rate of the carbon-fluorine gas in the second etching gas is in the range of 300-500 Sccm, and the flow rate of the processing gas is in the range of 100-300 Sccm.
[0018] Optionally, the physical bombardment gas is Ar, and the flow rate of Ar is 20-150 sccm.
[0019] Optionally, in step S2, the upper electrode power range is 1000-2000W, the lower electrode power range is 50W-100W, and the process chamber pressure is 50-200mT.
[0020] In step S3, the power range of the upper electrode is 1500-2500W, the power range of the lower electrode is 150W-250W, and the pressure range of the process chamber is 50-200mT.
[0021] The beneficial effects of this invention are as follows:
[0022] This invention uses a first etching gas and a second etching gas to etch the back side of a silicon substrate until the silicon on the back side of the substrate is etched to a set depth, exposing copper pillars from the back side of the silicon substrate. Both the first and second etching gases include fluorocarbon gases. Compared with existing methods that use SF6 etching gas, this method uses fluorocarbon gases as etching gases, which avoids the problem of Cu pillar skipping during the etching process. At the same time, in this method, a grid-like deposit is formed on the top of the insulating layer during the etching process using the first etching gas. Therefore, a treatment gas is added to the second etching gas to remove the grid-like deposit, thereby ensuring the uniformity of the height and morphology of the exposed Cu pillar.
[0023] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description
[0024] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.
[0025] Figure 1 A diagram of a heterogeneous chip package structure formed using a 2.5D packaging process is shown.
[0026] Figure 2 The image shows a before-and-after comparison of the existing whole-surface silicon thinning process that exposes copper pillars.
[0027] Figure 3a and Figure 3b The diagrams show the etching rate and selectivity (silicon to silicon oxide) of the back side of the silicon adapter plate etched using SF6 in the existing process.
[0028] Figure 4a and Figure 4b The diagrams show the uniformity and morphology of the copper pillars after etching the back of the silicon interposer using SF6 etching in the existing process.
[0029] Figures 5a-5c This diagram illustrates the Cu pillar skip phenomenon caused by the reaction between SF6 and copper when the back of a silicon interposer is etched with SF6 in an existing process.
[0030] Figure 6 A step diagram illustrating a method for fabricating a silicon adapter plate according to the present invention is shown.
[0031] Figure 7a and Figure 7b The electron microscope image and structural schematic diagram of the copper pillar morphology after etching with the first etching gas in this invention are shown.
[0032] Figure 8 The EDX elemental analysis diagram of the grid formed after etching with the first etching gas is shown.
[0033] Figure 9 The graphs show the performance of the fence under different pressures and chiiller temperatures.
[0034] Figure 10a A schematic diagram shows the formation of pitting anomalies after adding O2 gas to the etching gas.
[0035] Figure 10b The morphology of the pit and its EDX elemental analysis plot are shown.
[0036] Figure 11 A flowchart illustrating the steps of a method for preparing a silicon adapter plate according to an embodiment of the present invention is shown.
[0037] Figure 12 The diagram shows the etching structure changes corresponding to each step of a method for fabricating a silicon adapter plate according to an embodiment of the present invention.
[0038] Figure 13 This is an electron microscope image of Cu columnar morphology obtained by a method for preparing a silicon adapter plate according to an embodiment of the present invention. Detailed Implementation
[0039] Experimental analysis revealed that the key factor causing copper pillar skipping in existing technologies is SF6 gas. The sulfur in SF6 gas reacts with Cu to form CuS, which prevents the formation of Cu-Skip during silicon etching. This anomaly cannot be improved through process technology and is a defect of SF6 etching.
[0040] The silicon interposer fabrication method of the present invention provides a novel back-side etching process for silicon interposers (alternating switching of CF4+Ar / CF4+O2), which can effectively avoid Cu pillar skipping abnormalities caused by SF6, while ensuring the uniformity and morphology of exposed Cu pillars on the back side of the interposer, satisfying the BVR (back via reveal) etching process for 2.5D packaging.
[0041] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
[0042] like Figure 6 As shown, the present invention provides a method for preparing a silicon interposer plate, specifically including the following steps:
[0043] S1: A silicon substrate filled with an insulating layer and a conductive metal;
[0044] Specifically, the silicon substrate filled with an insulating layer and conductive metal is prepared using the TSV process. First, through-silicon vias (VIAs) are etched into the silicon substrate. Then, an insulating layer, typically SiO2, is grown on the inner wall of the VIA using PECVD (plasma-enhanced chemical vapor deposition). Conductive metal is then filled into the holes formed by the insulating layer to form conductive metal pillars, preferably Cu. The conductive metal pillars can be formed by sequentially growing a Ti layer, a Ni layer, and a Cu seed layer on the insulating layer, followed by Cu electroplating to form Cu pillars filling the vias. The silicon substrate filled with the insulating layer and conductive metal is used as the substrate for preparing the silicon adapter plate. S2: The back side of the silicon substrate is etched using a first etching gas, including a fluorocarbon gas, for a first set time. During the etching process, a grid-like deposit is formed at the top edge of the insulating layer.
[0045] In this step, the carbon-fluorine gas in the first etching gas can be CF4 or C4F8. The first etching gas also includes a physical bombardment gas, which is preferably Ar. Therefore, the first etching gas is CF4+Ar or C4F8+Ar.
[0046] Preferably, in this step, the etching process duration (first set duration) is greater than or equal to 1s and less than or equal to 3s, the flow rate of the fluorocarbon gas in the first etching gas is in the range of 100-300 Sccm, the flow rate of Ar is preferably 20-150 Sccm, the upper electrode power is in the range of 1000-2000W, the lower electrode power is in the range of 50W-100W, and the process chamber pressure is 50-200mT.
[0047] Specifically, compared to existing methods that use SF6 etching gas, this method uses fluorocarbon gases CF4 or C4F8 as etching gas, which avoids the Cu pillar skip problem during the etching process.
[0048] However, this step, using CF4+Ar for full-surface silicon etching, revealed a barrier phenomenon. Specifically, during the reaction between CF4 and silicon oxide (Oxideline, copper pillar sidewalls), the carbon and CF* atoms of CF4 accumulate (deposit) on top of the silicon oxide, forming a barrier. Figure 7a and Figure 7b As shown, the Si to SiO2 ratio is relatively low, approximately 1.3:1, which does not meet the process requirements. EDX elemental analysis further confirms this. Figure 8 As shown, column
[0049] The main component of the gate is carbon (accounting for more than 50%), the element Al is brought in by the stage, the elements O, Si, and Cu5 are the elements of the Cu pillar itself, and the element F is a reaction byproduct.
[0050] Experiments were conducted on the process conditions of CF4+Ar, and it was found that increasing the pressure can improve the selectivity (Si to Sio2), and increasing the chiiller temperature has a slight improvement on the gate structure, as shown in Table 1 and... Figure 9 As shown, however, the fence effect caused by CF* cannot be eliminated. Fence anomalies will lead to subsequent CVD generation.
[0051] A decrease in the bonding strength of long SiN / SiO2 is unacceptable. Therefore, in step S3 of this invention, a treatment gas is used to remove the barrier formed in step S2.
[0052] Table 1: Optimizing Process Conditions to Improve Fences
[0053]
[0054] S3: The back side of the silicon substrate is etched using a second etching gas for a second set time. The second etching gas includes a fluorocarbon gas and a processing gas. The processing gas is used to remove the grid-like deposits.
[0055] In this step, the ratio of the processing gas to the fluorocarbon gas in the second etching gas is greater than or equal to 1:10 and less than or equal to 1:4. The fluorocarbon gas can also preferably be CF4 or C4F8, the processing gas is preferably O2, the flow rate range of the fluorocarbon gas in the second etching gas is preferably 300-500 Sccm, and the flow rate of O2 is preferably 100-300 Sccm.
[0056] Preferably, in this step, the etching process duration (second set duration) is 2-5 seconds, the upper electrode power range is 1500-2500W, the lower electrode power range is 150W-250W, and the process chamber pressure range is 50-200mT.
[0057] Specifically, this step addresses the composition of the barrier formed in step S2 by adding O2 to the second etching gas to remove the barrier. The barrier is removed by reacting O2 with C / CF* to generate CO or CO2. An etching gas of CF4 + O2 is used, with an O2 to CF4 ratio greater than or equal to 1:10, for full-surface silicon etching.
[0058] The etching results show that the gate disappears and the selectivity ratio of silicon to silicon oxide increases to 4:1. This is because O2 can consume some of the CF*, which reduces the etching rate of SiO2 without affecting the etching rate of Si. Therefore, the selectivity ratio of silicon to silicon oxide is significantly improved.
[0059] However, this step introduced a new problem during the experiment: the addition of O2 to the second etching gas resulted in pitting anomalies, such as... Figure 10a and Figure 10b As shown in Table 2, with the O2 ratio increasing to greater than 4:1 and the etching time increasing to 180 s, the number and extent of pits significantly increase, indicating that O2 is a key factor in pit formation. This is because Cu on the silicon surface creates a local electric field (O2's high electronegativity exacerbates this field), leading to increased bombardment of localized areas on the silicon surface and causing pits. This is detrimental to subsequent CVD film formation and carries the risk of leakage.
[0060] Table 2: Effects of etching time and O2 flow rate on pitting
[0061]
[0062] It can be seen that eliminating the barrier requires adding O2 to the etching gas, and the O2:CF4 ratio must be greater than 1:10 to completely eliminate the barrier. However, this results in pitting anomalies. Experiments show that increasing the O2:CF4 ratio (O2:CF4 greater than 1:4) and increasing the etching time (without increasing the O2 ratio) both worsen the pitting and increase its area. Specifically, etching for a long time (180 seconds) with an O2:CF4 ratio of 1:10 increases the pit area, while etching for 180 seconds with an O2:CF4 ratio of 1:4 increases both the number and area of pits. Therefore, to avoid pitting anomalies, this step needs to maintain the O2:CF4 ratio between 1:10 and 1:4. Simultaneously, the single-step etching time in this step needs to be short, between 2 and 5 seconds. Because the single-step etching time is short, the process will switch to the next step before charge accumulation occurs, preventing pit formation due to localized electric fields. Thus, pit formation can be avoided while eliminating the barrier.
[0063] S4: Repeat steps S2-S3 until the silicon on the back side of the silicon substrate is etched to the set depth, so that the copper pillars are exposed from the back side of the silicon substrate.
[0064] Specifically, to avoid prolonged O2 etching in step S3, steps S2 and S3 are performed alternately to reduce the electrochemical effects of O2 and prevent the formation of pits. This alternating etching method also reduces the likelihood of persistent CF4+AR barriers that cannot be removed, while maintaining selectivity and etching rate. It should be noted that in step S2, excessive etching time leads to low selectivity, while insufficient time may not achieve the desired switching. Furthermore, after completing step S3 and switching back to step S2, residual O2 may accumulate, causing charge buildup and potentially forming pits. Therefore, the single-step etching time in step S2 must be greater than or equal to 1 second and less than or equal to 3 seconds.
[0065] By repeatedly performing the etching process in steps S2-S3, the silicon on the back side of the silicon substrate is thinned to a set thickness. Finally, copper pillars are exposed from the back side of the silicon substrate to a set height. Typically, the height of the Cu pillars before thinning is about 200 nm, and after etching, 5 μm Cu pillars are exposed. The morphology of the exposed Cu pillars after etching is normal and without barriers, and the entire back side of the silicon substrate is free of pits. At the same time, the height of the exposed Cu pillars is uniform.
[0066] Example
[0067] This embodiment provides a method for fabricating a silicon interposer. It employs continuous switching between a first etching gas (CF4+Ar or C4F8+Ar) and a second etching gas (CF4+O2 or C4F8+O2) to address the issues of railings and pits that occur during back-side etching of the silicon interposer. During etching with the first etching gas, CF4 causes railings for a short time. When switching to the second etching gas, O2 removes the railings. Simultaneously, because the etching time is short (2-5 seconds), pits are not formed due to localized electric fields. Thus, the formation of pits is avoided while eliminating railings.
[0068] like Figure 11 and Figure 12 As shown, taking the selection of CF4+Ar and CF4+O2 as two etching gases as an example, the preparation method of the silicon interposer in this embodiment includes the following steps:
[0069] Step S100: CF4 and Ar are used as the first etching gases. The upper electrode power is 1000-2000W, the lower electrode power is 50W-100W, the CF4 flow rate is 100-300Sccm, the Ar flow rate is 20-150Sccm, the process pressure is 50-200mT, and the etching time is greater than or equal to 1s and less than or equal to 3s. The entire back side of the silicon substrate 003 filled with silicon oxide and copper is etched. During the etching process, due to the relatively heavy polymer of CF4, a small number of fences 200 are formed on the periphery of the top of the sidewall of Cu pillar 001 (i.e., silicon oxide 002).
[0070] Step S200: After forming a small number of gates 200, immediately switch the etching gas to CF4 and O2, with an upper power of 1500-2500W and a lower power of 150W-250W. The CF4 flow rate is 300-500Sccm, the O2 flow rate is 100-300Sccm, the process pressure is 50-200mT, and the etching time is 2-5S. The entire back side of the silicon substrate 003 is etched. Because of the addition of O2, the gates 200 are etched away, forming smooth sidewalls of Cu pillars 001.
[0071] Step S300: Repeat steps S100-S200 and check the number of cycles. If the set number of cycles (etching depth) has not been reached, return to step S100 to start a new round of etching; if the set number of cycles (etching depth) has been reached, proceed to the next step S400.
[0072] Step S400: End the process.
[0073] The etching method in this embodiment can simultaneously solve the barrier problem and the pits caused by localized etching imbalance due to long-term electrochemical effects. After etching, the uniformity and selectivity of the copper pillars also meet the requirements. The exposed portion of the final obtained Cu pillar is as follows: Figure 13 As shown, the exposed portion of the Cu pillar has a normal morphology without any barriers, and the entire silicon surface is free of pits.
[0074] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.
Claims
1. A method for preparing a silicon interposer, characterized in that, include: S1: A silicon substrate filled with an insulating layer and a conductive metal; S2: The back side of the silicon substrate is etched using a first etching gas for a first set time. The first etching gas includes a fluorocarbon gas. During the etching process, a grid-like deposit is formed on the top of the insulating layer. S3: The back side of the silicon substrate is etched using a second etching gas for a second set time period. The second etching gas includes a fluorocarbon gas and a processing gas, and the processing gas is used to remove the grid-like deposits. S4: Repeat steps S2-S3 until the silicon on the back side of the silicon substrate is etched to a set depth, exposing the conductive metal from the back side of the silicon substrate.
2. The preparation method according to claim 1, characterized in that, The flow ratio of the processing gas to the fluorocarbon gas in the second etching gas is greater than or equal to 1:10 and less than or equal to 1:
4.
3. The preparation method according to claim 1 or 2, characterized in that, The fluorocarbon gas is CF4 or C4F8.
4. The preparation method according to claim 1 or 2, characterized in that, The processing gas includes O2.
5. The preparation method according to claim 1, characterized in that, The first etching gas also includes a physical bombardment gas.
6. The preparation method according to claim 1, characterized in that, The first set duration is greater than or equal to 1 second and less than or equal to 3 seconds, and / or the second set duration is greater than or equal to 2 seconds and less than or equal to 5 seconds.
7. The preparation method according to claim 1, characterized in that, The flow rate of the fluorocarbon gas in the first etching gas is in the range of 100-300 Sccm.
8. The preparation method according to claim 1, characterized in that, The flow rate of the carbon-fluorine gas in the second etching gas is 300-500 Sccm, and the flow rate of the processing gas is 100-300 Sccm.
9. The preparation method according to claim 5, characterized in that, The physical bombardment gas is Ar, and the Ar flow rate is 20-150 Sccm.
10. The preparation method according to claim 1, characterized in that, In step S2, the power range of the upper electrode is 1000-2000W, the power range of the lower electrode is 50W-100W, and the pressure of the process chamber is 50-200mT. In step S3, the power range of the upper electrode is 1500-2500W, the power range of the lower electrode is 150W-250W, and the pressure range of the process chamber is 50-200mT.