A slicing method of a wafer structure

Abstract

The application provides a wafer structure slicing method, which comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of device regions and a plurality of cutting channel regions; forming a first groove in the device region and a second groove in the cutting channel region, wherein the width of the second groove is greater than that of the first groove, the position of the second groove corresponds to the position of the cutting channel, the depth of the second groove is greater than that of the first groove; forming a semiconductor device in the first groove, and forming a filling layer on the bottom and sidewall of the second groove, wherein the filling layer does not completely fill the second groove, and the second groove has a through hole in the depth direction; thinning the second surface of the wafer to expose the through hole, and separating the adjacent device regions. The wafer structure slicing method provided by the application can avoid damaging the wafer, improve the reliability of the device, improve the efficiency of cutting the wafer, and save costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for slicing a wafer structure. Background Technology

[0002] In semiconductor manufacturing, after dies are formed on a wafer, the wafer needs to be diced into individual dies through a dicing process. These dies are then packaged to form ready-to-use chips. The dicing process takes place in dicing channels; however, the mechanical force of dicing can cause micro-cracks to form at the edges, especially near the corners. These cracks can propagate towards the central circuit area of ​​the integrated circuit, causing damage to that circuit area. Furthermore, with the development of semiconductor manufacturing processes, semiconductor device sizes are becoming smaller, and chip density on wafers is increasing. This results in a larger area ratio of dicing channels, reducing the surface area utilization of the wafer. Moreover, the large number of dicing processes reduces production efficiency and increases production costs.

[0003] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0004] This application provides a wafer slicing method, which on the one hand can avoid damage to the wafer during wafer slicing, thereby improving device reliability; on the other hand, it can improve wafer slicing efficiency and save costs.

[0005] One aspect of this application provides a method for slicing a wafer structure, comprising: providing a wafer including a plurality of device regions for forming semiconductor devices and a plurality of dicing regions for forming dicing tracks, the wafer including a first side and a second side opposite to each other; forming a first trench in the device region of the first side of the wafer and forming a second trench in the dicing regions of the first side of the wafer, the width of the second trench being greater than the width of the first trench and the position of the second trench corresponding to the position of the dicing track, the depth of the second trench being greater than the depth of the first trench; forming a semiconductor device in the first trench and simultaneously forming a filling layer at the bottom and sidewalls of the second trench, wherein the filling layer does not completely fill the second trench and the second trench has a through hole in the depth direction; thinning the second side of the wafer to expose the through hole, thereby separating adjacent device regions.

[0006] In some embodiments of this application, the method for forming the first trench and the second trench includes: performing a first etching process to etch a first surface of the wafer in the dicing area to form a second trench; performing a second etching process to etch a first surface of the wafer in the device area to form a first trench, while simultaneously etching the wafer at the bottom of the second trench to make the depth of the second trench greater than the depth of the first trench.

[0007] In some embodiments of this application, the depth of the second trench formed by the first etching process is H1, the depth of the second trench after the second etching process is H2, the depth of the first trench is H3, and H2 is 0.5 micrometers to 100 micrometers larger than H3.

[0008] In some embodiments of this application, the method for forming the first trench and the second trench includes: performing a third etching process to etch a first surface of the wafer in the device region to form the first trench, and simultaneously etching a first surface of the wafer in the dicing area to form the second trench; and continuing to perform a fourth etching process to etch the wafer at the bottom of the second trench so that the depth of the second trench is greater than the depth of the first trench.

[0009] In some embodiments of this application, the depth of the first trench formed by the third etching process is h1, the depth of the second trench is h2, and the depth of the second trench after the fourth etching process is h3, where h3 is 0.5 micrometers to 100 micrometers larger than h1.

[0010] In some embodiments of this application, the width of the through hole is 10 nanometers to 80 micrometers, and the width of the second trench is less than or equal to 100 micrometers.

[0011] In some embodiments of this application, the method of thinning the second side of the wafer to expose the through-hole and separating adjacent devices includes: forming a carrier substrate on the first side of the wafer; thinning the second side of the wafer to expose the through-hole; and removing the carrier substrate to separate adjacent devices.

[0012] In some embodiments of this application, the method of forming a carrier substrate on the first surface of the wafer includes: simultaneously bonding a carrier wafer, wherein the carrier wafer is the carrier substrate, to the first surface of the wafer.

[0013] In some embodiments of this application, the method of forming a carrier substrate on the first surface of the wafer includes: forming an organic film on the first surface of the wafer, wherein the organic film is the carrier substrate.

[0014] In some embodiments of this application, the semiconductor device is a capacitor. A semiconductor device is formed in the first trench, and a filling layer is formed at the bottom and sidewalls of the second trench. The method of having a through hole in the second trench in the depth direction includes: forming a lower electrode layer, a dielectric layer, and an upper electrode layer sequentially at the bottom and sidewalls of the first trench, the first surface of the wafer, and the bottom and sidewalls of the second trench. The lower electrode layer, dielectric layer, and upper electrode layer fill the first trench but do not fill the second trench. The lower electrode layer, dielectric layer, and upper electrode layer in the first trench form the capacitor, and the lower electrode layer, dielectric layer, and upper electrode layer in the second trench form the filling layer.

[0015] This application provides a wafer slicing method. When etching to fabricate semiconductor devices in the device region, through-holes are simultaneously etched in the dicing area. The device region is separated through the through-holes to achieve slicing. On the one hand, this method can avoid damage to the wafer during slicing, thereby improving device reliability; on the other hand, it can improve the efficiency of wafer slicing and save costs. Attached Figure Description

[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0017] Figure 1 This is a flowchart of the wafer slicing method described in the embodiments of this application;

[0018] Figures 2 to 13 This is a schematic diagram of each step in the wafer slicing method described in the embodiments of this application. Detailed Implementation

[0019] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0020] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0021] Figure 1 This is a flowchart of the wafer slicing method described in the embodiments of this application.

[0022] Embodiments of this application provide a wafer slicing method, referencing... Figure 1 As shown, it includes:

[0023] Step S1: Provide a wafer, the wafer including a plurality of device regions for forming semiconductor devices and a plurality of dicing regions for forming dicing channels, the wafer including a first side and a second side opposite to each other;

[0024] Step S2: A first trench is formed in the device region on the first side of the wafer, and a second trench is formed in the dicing region on the first side of the wafer. The width of the second trench is greater than the width of the first trench, and the position of the second trench corresponds to the position of the dicing. The depth of the second trench is greater than the depth of the first trench.

[0025] Step S3: A semiconductor device is formed in the first trench, and a filling layer is formed at the bottom and sidewalls of the second trench, wherein the filling layer does not completely fill the second trench and the second trench has a through hole in the depth direction;

[0026] Step S4: Thin the second side of the wafer to expose the through-hole, separating adjacent devices.

[0027] Figures 2 to 13 This is a schematic diagram of each step in the wafer slicing method described in the embodiments of this application. The wafer slicing method described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] refer to Figure 1 and Figure 2 As shown, in step S1, a wafer 100 is provided, the wafer 100 including a plurality of device regions 101 for forming semiconductor devices and a plurality of dicing regions 102 for forming dicing channels, the wafer including a first surface 110 and a second surface 120 opposite to each other.

[0029] In semiconductor manufacturing, after the dies are formed on the wafer, the wafer needs to be cut into individual dies through a dicing process, which takes place in dicing channels. Therefore, in addition to several device regions 101 for forming semiconductor devices, the wafer 100 also includes several dicing channel regions 102 for forming dicing channels. The dicing channel regions 102 are located between adjacent device regions 101, facilitating the subsequent separation of adjacent device regions 101 through the dicing channel regions 102, thus achieving the purpose of slicing.

[0030] In some embodiments of this application, the wafer 100 is a semiconductor wafer, such as a silicon wafer. Silicon is a commonly used material in the semiconductor field, which is beneficial for improving process compatibility and saving costs.

[0031] It should be noted that, for ease of understanding and for the purpose of brevity, only two device regions 101 and one dicing region 102 are shown in the accompanying drawings. However, those skilled in the art should understand that there may be multiple device regions 101 and dicing regions 102.

[0032] refer to Figure 1 and Figures 3 to 4As shown, in step S2, a first trench 111 is formed in the device region 101 of the first surface 110 of the wafer, and a second trench 112 is formed in the dicing region 102 of the first surface 110 of the wafer. The width of the second trench 112 is greater than the width of the first trench 111, and the position of the second trench 112 corresponds to the position of the dicing. The depth of the second trench 112 is greater than the depth of the first trench 111.

[0033] In some embodiments of this application, the method of forming the first trench 111 and the second trench 112 includes: referring to Figure 3 As shown, a first etching process is performed to etch the first surface of the wafer in the dicing region 102 to form a second trench 112; (Refer to...) Figure 4 As shown, a second etching process is performed to etch the first surface of the wafer in the device region 101 to form a first trench 111, while simultaneously etching the wafer at the bottom of the second trench 112 so that the depth of the second trench 112 is greater than the depth of the first trench 111.

[0034] In some embodiments of this application, the first and second etching processes are photolithography processes, which are conventional processes in semiconductor manufacturing. The specific processes and steps of photolithography are not detailed here. The first and second etching processes can be performed using only a photoresist layer as a mask, or they can be performed using both a photoresist layer and a hard mask layer as masks. The hard mask layer can be formed before the second trench is etched, or it can be formed after the second trench is formed but before the first trench is etched. Similarly, in the process of multiple etchings to form the depth difference between the second and first trenches, the hard mask layer can be formed before the second trench is etched, or it can be formed after the second trench is etched but before the first trench is etched.

[0035] In some embodiments of this application, the depth of the second trench 112 formed by the first etching process is H1, the depth of the second trench 112 after the second etching process is H2, the depth of the first trench 111 is H3, and H2 is 0.5 micrometers to 100 micrometers larger than H3, for example, 5 micrometers, 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers or 90 micrometers.

[0036] In some embodiments of this application, the first trench 111 is used to form a semiconductor device, and the second trench 112 is used to separate adjacent device regions 101.

[0037] The width of the second trench 112 needs to be greater than the width of the first trench 111 to ensure that the second trench 112 will not be completely filled when a semiconductor device is subsequently formed in the first trench 111. In some embodiments of this application, the width of the first trench 111 is 20% to 60% of the width of the second trench 112, for example, 30%, 40%, 50%, etc. Specifically, the width of the first trench 111 is set according to the size of the semiconductor device to be formed. The width difference between the second trench 112 and the first trench 111 cannot be too large, so as to reduce the width of the second trench 112 and save the area of ​​the wafer surface; the width difference between the second trench 112 and the first trench 111 cannot be too small, so that after the semiconductor device is formed in the first trench 111, the remaining through-holes in the second trench 112 are not easily closed in subsequent processes.

[0038] The position of the second trench 112 corresponds to the position of the dicing track. The technical solution of this application uses the second trench 112 to separate adjacent device areas instead of cutting on the dicing track, which avoids mechanical damage to the wafer during cutting, simplifies the process, improves efficiency, and saves costs.

[0039] In some embodiments of this application, the method for forming the first trench 111 and the second trench 112 includes: etching the first surface 110 of the wafer 100 using an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial for improving the controllability of the etching profile, thereby improving the profile morphology quality of the first trench 111 and the second trench 112, for example, improving the smoothness and steepness of the sidewalls of the first trench 111 and the second trench 112. Furthermore, the anisotropic dry etching process has high etching precision, which is beneficial for reducing damage to the wafer 100.

[0040] Specifically, the anisotropic dry etching process is, for example, reactive ion etching (RIE). In RIE, a radio frequency voltage is applied between planar electrodes, and the generated plasma chemically and physically etches the layer to be etched. The plasma generated by gas discharge contains a large number of chemically active gas ions. These gas ions interact with the material surface, causing surface atoms to undergo chemical reactions and generate volatile products. These volatile products are then expelled from the reaction chamber by a vacuum pumping system. Through a cyclical process of "reaction-stripping-emission" of the material surface, the material is etched layer by layer to a specified depth. In addition to surface chemical reactions, the bombardment of the material surface by energetic ions also causes surface atoms to sputter, producing a certain etching effect. Therefore, by selecting reactive ion etching, it is beneficial to further improve the cross-sectional morphology quality of the first trench 111 and the second trench 112, and also to precisely control the depth of the first trench 111 and the second trench 112.

[0041] Figure 3 and Figure 4 This illustrates a method for forming the first trench 111 and the second trench 112 in one embodiment. Below... Figure 5 and Figure 6 The illustration shows a method for forming the first trench 111a and the second trench 112a in another embodiment.

[0042] In other embodiments of this application, the method of forming the first trench 111a and the second trench 112a includes: referring to Figure 5 As shown, a third etching process is performed to etch the first wafer surface of the device region 101 to form a first trench 111a, and simultaneously etch the first wafer surface of the dicing region 102 to form a second trench 112a; (Refer to...) Figure 6 As shown, the fourth etching process is continued to etch the wafer at the bottom of the second trench 112a so that the depth of the second trench 112a is greater than the depth of the first trench 111a.

[0043] In some embodiments of this application, the depth of the first trench 111a formed by the third etching process is h1, the depth of the second trench 112a is h2, and the depth of the second trench 112a after the fourth etching process is h3. h3 is 0.5 micrometers to 50 micrometers larger than h1, for example, 5 micrometers, 10 micrometers, 20 micrometers, 30 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers or 90 micrometers.

[0044] Both methods described above for forming the first and second trenches require two etching processes. However, in some embodiments of this application, the first and second trenches can be formed with only one etching process. In the etching process, the etching rate is also related to the width of the trench; the wider the trench, the faster the etching rate. Therefore, by controlling the width ratio of the second trench to the first trench, making the width of the second trench greater than the width of the first trench, the etching rate of the second trench is greater than that of the first trench, and the depth of the second trench is greater than that of the first trench. By strictly controlling the etching process and designing the width ratio of the second and first trenches, the etching rate ratio of the second and first trenches can be controlled, thereby controlling the depth ratio of the second and first trenches.

[0045] refer to Figure 1 and Figure 7 As shown, in step S3, a semiconductor device 130 is formed in the first trench 111, and a filling layer 140 is formed at the bottom and sidewalls of the second trench 112. The filling layer 140 does not completely fill the second trench 112, and the second trench 112 has a through hole 113 in the depth direction.

[0046] It should be noted that in the technical solution of this application, a second trench 112 is formed in the dicing area 102 while the first trench 111 is formed in the device region 101. In subsequent processes, the second trench 112 is controlled to prevent it from being filled and closed, thereby further penetrating the wafer 100 through the second trench 112 to achieve separation of the device region 101, i.e., to achieve slicing. Therefore, the technical solution of this application is theoretically suitable for all semiconductor devices involving deep trench processes, as long as the trenches in the dicing area 102 are not filled and closed after the deep trench process. In this embodiment, only the semiconductor device 130 is used as a capacitor as an example for illustration.

[0047] It should be noted that the through hole 113 is part of the second groove 112, that is, the second groove 112 includes the through hole 113. Therefore, although the second groove 112 is not indicated in the drawings, it should be understood that the through hole 113 is part of the second groove 112.

[0048] refer to Figure 7 As shown, the semiconductor device 130 is, for example, a capacitor. The method of forming the semiconductor device 130 in the first trench 111 and simultaneously forming a filling layer 140 on the bottom and sidewalls of the second trench 112, wherein the second trench 112 has a through-hole 113 in the depth direction, includes:

[0049] refer to Figure 7As shown, a lower electrode layer 131, a dielectric layer 132, and an upper electrode layer 133 are sequentially formed at the bottom and sidewalls of the first trench 111, the first surface 110 of the wafer, and the bottom and sidewalls of the second trench 112. The lower electrode layer 131, the dielectric layer 132, and the upper electrode layer 133 fill the first trench 111 but do not fill the second trench 112. A through hole 113 is left in the second trench 112. The lower electrode layer 131, the dielectric layer 132, and the upper electrode layer 133 in the first trench 111 form the capacitor (i.e., semiconductor device 130), and the lower electrode layer 131, the dielectric layer 132, and the upper electrode layer 133 in the second trench 112 form the filling layer 140.

[0050] In some embodiments of this application, the capacitor (i.e., semiconductor device 130) is a silicon-based capacitor. Silicon-based capacitors have advantages such as low insertion loss and high stability. Moreover, the electrode material of a silicon-based capacitor includes silicon, which is a commonly used and readily available material in semiconductor processes, thus improving process compatibility and reducing process costs.

[0051] The materials of the lower electrode layer 131 and the upper electrode layer 133 are conductive materials. In some embodiments of this application, the capacitor is a silicon-based capacitor, and the materials of the lower electrode layer 131 and the upper electrode layer 133 include polycrystalline silicon doped with conductive ions.

[0052] Among them, the conductive ions include N-type ions (e.g., P ions, As ions or Sb ions) or P-type ions (e.g., P-type ions can be B ions, Ga ions or In ions).

[0053] The dielectric layer 132 is used to electrically isolate the lower electrode layer 131 and the upper electrode layer 133. The dielectric layer 132 is made of an insulating material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments of this application, the dielectric layer 132 is made of silicon oxide, which is a commonly used insulating material in the semiconductor field. Silicon oxide is beneficial for improving process compatibility and reducing process costs. Furthermore, silicon oxide has good insulating properties, which helps ensure the insulation performance between the lower electrode layer 131 and the upper electrode layer 133. In addition, silicon oxide has good adhesion to other material layers, which helps improve the structural stability of the capacitor.

[0054] In some embodiments of this application, the process for forming the capacitor includes one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). Specifically, in this embodiment, ALD is used to sequentially form the lower electrode layer 131, the dielectric layer 132, and the upper electrode layer 133.

[0055] In some embodiments of this application, the width of the through-hole 113 is 10 nanometers to 80 micrometers, and the width of the second trench is less than or equal to 100 micrometers. The width of the through-hole 113 should not be too large to save wafer area; the width of the through-hole 113 should also not be too small to avoid the through-hole 113 being closed and filled in subsequent processes.

[0056] In some other embodiments of this application, the semiconductor device 130 is a deep trench isolation structure in an image sensor. The semiconductor device 130 is formed in the first trench 111, and a filling layer 140 is formed at the bottom and sidewalls of the second trench 112. The method for having a through-hole 113 in the depth direction of the second trench 112 includes: forming an isolation material layer at the bottom and sidewalls of the first trench 111, the first surface 110 of the wafer, and the bottom and sidewalls of the second trench 112; the isolation material layer fills the first trench 111 but does not fill the second trench 112, leaving a through-hole 113 in the second trench 112; removing the isolation material layer above the first surface 110 of the wafer; the isolation material layer in the first trench 111 forms the deep trench isolation structure, and the isolation material layer in the second trench 112 forms the filling layer 140.

[0057] In some embodiments of this application, the semiconductor device 130 may also be other devices that incorporate deep trench technology, such as memory, CMOS transistors, etc. Furthermore, when the device region contains multiple deep trench devices and therefore requires multiple deep trench etchings, etching can also be performed in the etch channel region each time the device region is etched, increasing the depth of the second trench.

[0058] refer to Figure 8 As shown, the lower electrode layer 131, dielectric layer 132 and upper electrode layer 133 are etched to expose different electrode layers, which facilitates the subsequent metal interconnect layers to electrically connect the different electrode layers respectively, and separates the lower electrode layer 131, dielectric layer 132 and upper electrode layer 133 in the first trench 111 and the second trench 112, so as to avoid the lower electrode layer 131, dielectric layer 132 and upper electrode layer 133 in the second trench 112 from affecting the capacitor in the first trench 111.

[0059] Specifically, the upper electrode layer 133 can be etched first, followed by the dielectric layer 132, and finally the lower electrode layer 131. The etching process is the same as the conventional method for opening different electrode layers, and will not be described in detail here.

[0060] refer to Figure 9As shown, an insulating dielectric layer 150 is formed on the first surface 110 of the wafer and the bottom and sidewalls of the second trench; a metal interconnect layer (not shown) electrically connecting the semiconductor device 130 is formed in the insulating dielectric layer 150 of the first surface 110 of the wafer.

[0061] In some embodiments of this application, the method for forming the insulating dielectric layer 150 is chemical vapor deposition or physical vapor deposition, etc. The material of the insulating dielectric layer 150 is, for example, silicon oxide.

[0062] In some embodiments of this application, the method for forming the metal interconnect layer that electrically connects the semiconductor device 130 is a conventional process and will not be described in detail here.

[0063] refer to Figure 1 and Figures 10 to 13 As shown, in step S4, the second side of the wafer 100 is thinned to expose the through hole 113, and the adjacent device regions 101 are separated.

[0064] In some embodiments of this application, the method of thinning the second side of the wafer 100 to expose the through-hole 113 and separating adjacent device regions 101 includes: referring to Figure 10 and Figure 11 As shown, a carrier substrate 160 is formed on the first surface 110 of the wafer (the surface of the insulating dielectric layer 150). The carrier substrate 160 is used to support the wafer 100 and protect the structure on the first surface 110 of the wafer 100 for processing on the second surface 120 of the wafer 100. Figure 10 and Figure 11 Two methods for forming the support substrate 160 in the embodiments of this application are shown respectively.

[0065] refer to Figure 10 As shown, in some embodiments of this application, the method of forming a carrier substrate 160 on the first surface 110 of the wafer includes: temporarily bonding a carrier wafer, which is the carrier substrate 160, to the first surface 110 of the wafer. The carrier wafer is, for example, a semiconductor wafer or a glass wafer. The carrier wafer is temporarily bonded using temporary bonding adhesive.

[0066] refer to Figure 11 As shown, in some other embodiments of this application, the method of forming a carrier substrate 160 on the first surface 110 of the wafer includes: forming an organic adhesive layer in the first surface 110 of the wafer and the second trench, the organic adhesive layer being the carrier substrate 160. The organic adhesive layer may completely fill the through-hole or partially fill the through-hole.

[0067] In some other embodiments of this application, the method of forming a carrier substrate 160 on the first surface 110 of the wafer further includes: forming an organic film on the first surface 110 of the wafer, wherein the organic film is the carrier substrate 160.

[0068] In some other embodiments of this application, the method of forming a carrier substrate 160 on the first surface 110 of the wafer further includes: forming an organic adhesive layer in the first surface 110 of the wafer and the second trench, forming an organic film on the surface of the organic adhesive layer, wherein the organic adhesive layer and the organic film together constitute the carrier substrate 160.

[0069] In other words, an organic adhesive layer can be used alone as the carrier substrate 160, an organic film can be used alone as the carrier substrate 160, or both an organic adhesive layer and an organic film can be used simultaneously as the carrier substrate 160. The difference between the organic adhesive layer and the organic film is that the organic adhesive is a fluid adhesive that is applied to the wafer and needs to be dried and cured before it can be used as a carrier substrate, while the organic film is a film layer made of organic material that is directly adhered to the wafer.

[0070] In some embodiments of this application, the method further includes: curing the organic adhesive layer, for example, using a hardbaking process to cure the organic adhesive layer.

[0071] In some embodiments of this application, the method of thinning the second side of the wafer 100 to expose the through-hole 113 and separating adjacent device regions 101 further includes: referring to Figure 12 As shown, the second side of the wafer 100 is thinned to expose the through hole 113. Figure 12 It is along Figure 10 To be continued.

[0072] In some embodiments of this application, the method for thinning the second surface of the wafer 100 to expose the through-hole 113 includes chemical mechanical polishing (CMP) or mechanical polishing. Since the through-hole 113 (i.e., the second trench 112) is relatively deep, meaning the wafer thickness at the bottom of the through-hole 113 is relatively thin, only a small amount of polishing is needed to expose the through-hole. This results in high process efficiency and feasibility, eliminating the need for etching the protective layer 140 or mechanical cutting.

[0073] In some embodiments of this application, the method of thinning the second side of the wafer 100 to expose the through-hole 113 and separating adjacent device regions 101 further includes: referring to Figure 13 As shown, the carrier substrate 160 is removed to separate the adjacent device regions 101.

[0074] In some embodiments of this application, if the carrier substrate 160 is a carrier wafer, it is only necessary to release the temporary bond and remove the carrier wafer; if the carrier substrate 160 is an organic adhesive layer, it is only necessary to remove the adhesive directly.

[0075] In conventional processes, wafers are sliced ​​by cutting along dicing channels. However, the mechanical force during dicing can easily damage the wafer, reducing device reliability. Furthermore, as chip density on the wafer increases, the number of dicing operations and dicing time also increase, reducing efficiency and increasing cost. In the technical solution of this application, a second trench is formed simultaneously in the dicing channel area during semiconductor device fabrication. This second trench is deeper than the first trench. Subsequent dicing only requires grinding the second side of the wafer to expose the second trench and separate adjacent device areas, resulting in less grinding and higher process efficiency and feasibility. Integrating the dicing step into semiconductor device fabrication and using etching to separate device areas improves efficiency and avoids mechanical damage to the wafer from dicing, thus improving device reliability. In addition, the through-hole size formed by etching can be smaller, allowing for a smaller dicing channel area, thereby improving wafer area utilization and increasing chip density.

[0076] This application provides a wafer slicing method. When etching to fabricate semiconductor devices in the device region, through-holes are simultaneously etched in the dicing area. The device region is separated through the through-holes to achieve slicing. On the one hand, this method can avoid damage to the wafer during slicing, thereby improving device reliability; on the other hand, it can improve the efficiency of wafer slicing and save costs.

[0077] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0078] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0079] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0080] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0081] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for slicing a wafer structure, characterized in that, include: A wafer is provided, the wafer including a plurality of device regions for forming semiconductor devices and a plurality of dicing regions for forming dicing channels, the wafer including opposing first and second surfaces; A first trench is formed in the device region of the first surface of the wafer, and a second trench is formed in the dicing region of the first surface of the wafer. The width of the second trench is greater than the width of the first trench, and the position of the second trench corresponds to the position of the dicing. The depth of the second trench is greater than the depth of the first trench. A semiconductor device is formed in the first trench, and a filling layer is formed at the bottom and sidewalls of the second trench, wherein the filling layer does not completely fill the second trench and the second trench has a through hole in the depth direction, and the depth of the second trench is such that when the second side of the wafer is thinned to expose the through hole, adjacent devices can be separated. The second side of the wafer is then directly thinned to expose the through-hole, separating adjacent devices.

2. The wafer slicing method as described in claim 1, characterized in that, The method of forming the first trench and the second trench includes: A first etching process is performed to etch the first surface of the wafer in the dicing area to form a second trench; A second etching process is performed to etch the first surface of the wafer in the device region to form a first trench, while simultaneously etching the bottom of the second trench on the wafer to make the depth of the second trench greater than the depth of the first trench.

3. The wafer slicing method as described in claim 2, characterized in that, The depth of the second trench formed by the first etching process is H1, and the depth of the second trench after the second etching process is H2. The depth of the first trench is H3, and H2 is 0.5 micrometers to 100 micrometers larger than H3.

4. The wafer slicing method as described in claim 1, characterized in that, The method of forming the first trench and the second trench includes: A third etching process is performed to etch the first surface of the wafer in the device region to form a first trench, and simultaneously etch the first surface of the wafer in the dicing area to form a second trench; Continue with the fourth etching process to etch the wafer at the bottom of the second trench so that the depth of the second trench is greater than the depth of the first trench.

5. The wafer slicing method as described in claim 4, characterized in that, The first trench formed by the third etching process has a depth of h1, the second trench has a depth of h2, and after the fourth etching process, the second trench has a depth of h3, which is 0.5 micrometers to 100 micrometers larger than h1.

6. The wafer slicing method as described in claim 1, characterized in that, The width of the through hole is 10 nanometers to 80 micrometers, and the width of the second trench is less than or equal to 100 micrometers.

7. The wafer slicing method as described in claim 1, characterized in that, The method for thinning the second side of the wafer to expose the through-hole and separating adjacent devices includes: A support substrate is formed on the first surface of the wafer; Thin the second side of the wafer to expose the through-hole; Remove the supporting substrate to separate adjacent device regions.

8. The wafer slicing method as described in claim 7, characterized in that, A method for forming a carrier substrate on the first face of the wafer includes: simultaneously bonding a carrier wafer, wherein the carrier wafer is the carrier substrate, to the first face of the wafer.

9. The wafer slicing method as described in claim 7, characterized in that, A method for forming a carrier substrate on the first surface of the wafer includes: forming an organic film on the first surface of the wafer, wherein the organic film is the carrier substrate.

10. The wafer slicing method as described in claim 1, characterized in that, The semiconductor device is a capacitor. A semiconductor device is formed in the first trench, and a filling layer is formed at the bottom and sidewalls of the second trench. The method of having a through hole in the second trench in the depth direction includes: forming a lower electrode layer, a dielectric layer and an upper electrode layer sequentially at the bottom and sidewalls of the first trench, the first surface of the wafer and the bottom and sidewalls of the second trench. The lower electrode layer, dielectric layer and upper electrode layer fill the first trench but do not fill the second trench. The lower electrode layer, dielectric layer and upper electrode layer in the first trench form the capacitor, and the lower electrode layer, dielectric layer and upper electrode layer in the second trench form the filling layer.

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