An insulated gate bipolar transistor

Abstract

This invention provides an insulated-gate bipolar transistor (IGBT), comprising: a drift layer; a well region located within the drift layer; a source region located within the well region; a first dielectric barrier layer located in the drift layer at the bottom of the well region and adjacent to the well region; and a second dielectric barrier layer disposed in the drift layers on both sides of the well region along the channel length direction, wherein the distance from the second dielectric barrier layer to the top surface of the drift layer is greater than zero; the first and second dielectric barrier layers expose the boundary region between the bottom surface of the well region and the sidewalls of the well region. The aforementioned IGBT reduces the on-state voltage drop without increasing the turn-off loss of the IGBT, thus well meeting the application requirements of high-voltage, high-power switching.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and more specifically to an insulated gate bipolar transistor. Background Technology

[0002] The Insulated Gate Bipolar Transistor (IGBT) combines the advantages of the MOSFET and the BJT, featuring low on-state voltage drop and fast switching speed, thus becoming one of the core electronic components in modern power electronic circuits. When an IGBT is turned on, both holes and electrons participate in conduction, creating a good conductivity modulation effect to reduce its on-state voltage drop. However, when it is turned off, electrons in the drift layer are quickly drawn away from the channel, while holes can only be slowly cleared through recombination. This results in a significant tail current, increasing the IGBT's turn-off losses.

[0003] To further optimize the trade-off between IGBT on-state voltage drop and turn-off loss, an IGBT with a carrier storage layer has been proposed, such as... Figure 1 As shown, by adding a carrier storage layer 7' around the well region 6', the on-state voltage drop can be reduced without increasing the turn-off loss. However, the carrier storage layer 7' structure also has corresponding drawbacks. As the concentration of the carrier storage layer 7' increases, a high peak electric field is formed between the well region 6' and the carrier storage layer 7', especially at the corner, which seriously affects the blocking capability of the IGBT. Therefore, the doping concentration of the carrier storage layer 7' should not be set too high, and the concentration of the drift layer 8' needs to be appropriately reduced and the chip thickness increased for compensation. However, such compensation will lead to an increase in the on-state voltage drop of the device, and the advantages of the compromise characteristics of the carrier storage layer 7' cannot be fully utilized. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to reduce the on-state voltage drop of an insulated gate bipolar transistor (IGBT) without increasing its turn-off loss.

[0005] This invention provides an insulated gate bipolar transistor (IGBT), comprising: a drift layer; a well region located within the drift layer; a source region located within the well region; a first dielectric barrier layer located in the drift layer at the bottom of the well region and adjacent to the well region; a second dielectric barrier layer disposed in the drift layers on both sides of the well region along the channel length direction, wherein the distance from the second dielectric barrier layer to the top surface of the drift layer is greater than zero; the first dielectric barrier layer and the second dielectric barrier layer expose the boundary region between the bottom surface of the well region and the sidewall of the well region.

[0006] Optionally, the materials of the second insulating dielectric barrier layer and the first insulating dielectric barrier layer include silicon dioxide.

[0007] Optionally, the distance from the top surface of the second insulating dielectric barrier layer to the top surface of the drift layer is greater than the channel depth of the insulated gate bipolar transistor.

[0008] Optionally, the number of well regions is several; for any two adjacent well regions, the second insulating dielectric barrier layer adjacent to one well region and the second insulating dielectric barrier layer adjacent to the other well region are arranged alternately.

[0009] Optionally, for a second insulating dielectric barrier layer located on any side of the trench length direction of the well region and adjacent to the well region, the second insulating dielectric barrier layer includes a first second sub-insulating dielectric barrier layer to an Nth second sub-insulating dielectric barrier layer arranged sequentially at intervals. The lateral distance between the first second sub-insulating dielectric barrier layer and the well region increases from the lateral distance between the Nth second sub-insulating dielectric barrier layer and the well region. The depth of the first second sub-insulating dielectric barrier layer in the drift layer increases from the depth of the Nth second sub-insulating dielectric barrier layer in the drift layer, where N is an integer greater than or equal to 2.

[0010] Optionally, the shape of any k-th second sub-insulating dielectric barrier layer includes an ellipsoid, where k is an integer greater than or equal to 1 and less than or equal to N.

[0011] Optionally, any k-th second sub-insulating dielectric barrier layer has a first central axis and a second central axis that are perpendicular to each other in a cross-section parallel to the length direction of the channel and perpendicular to the top surface of the drift layer. The k-th second sub-insulating dielectric barrier layer has a first diameter on the first central axis and a second diameter on the second central axis. The first diameter is smaller than the second diameter.

[0012] Optionally, the first diameter of the first sub-insulating dielectric barrier layer to the first diameter of the Nth sub-insulating dielectric barrier layer are parallel to each other, and the second diameter of the first sub-insulating dielectric barrier layer to the second diameter of the Nth sub-insulating dielectric barrier layer are parallel to each other.

[0013] Optionally, for the well region and the second insulating dielectric barrier layer adjacent to the well region, the distance from the vertex of any k-th second sub-insulating dielectric barrier layer in the second insulating dielectric barrier layer to the well region is greater than the distance from the bottom point of the k-th second sub-insulating dielectric barrier layer to the well region.

[0014] Optionally, the acute angle between the second diameter and the sidewall of the trap area is 45° to 60°.

[0015] Optionally, the second diameter is 1 / 3 to 1 / 2 of the depth of the well region.

[0016] Optionally, the first diameter is 1 / 5 to 1 / 3 of the depth of the well region.

[0017] Optionally, the second insulating dielectric barrier layer adjacent to the well region has a continuous structure.

[0018] Optionally, the second insulating dielectric barrier layer is elongated or ellipsoidal.

[0019] Optionally, the second insulating dielectric barrier layer is in contact with the well region.

[0020] Optionally, the dimension of the second insulating dielectric barrier layer in the direction perpendicular to the top surface of the drift layer is 1 / 3 to 1 / 2 of the depth of the well region.

[0021] Optionally, the number of well regions is several; the dimension of the second insulating dielectric barrier layer in the direction parallel to the channel is 1 / 4 to 1 / 3 of the distance between adjacent well regions.

[0022] The technical solution of the present invention has the following beneficial effects:

[0023] The insulated-gate bipolar transistor (IGBT) provided by this invention, by setting a first insulating dielectric barrier layer at the bottom of the well region and a second insulating dielectric barrier layer in the drift layer on both sides of the well region along the channel length direction, reduces the collection of holes in the well region when the IGBT is turned on, thereby indirectly enhancing the recombination of holes and electrons in the drift layer, increasing the conductivity modulation effect of the IGBT, and reducing the on-state voltage drop of the IGBT. At the same time, the first and second insulating dielectric barrier layers expose the boundary region between the bottom surface and the sidewall of the well region. When the IGBT is turned off, the boundary region is less prone to electric field concentration, avoiding an increase in the turn-off loss of the IGBT. Moreover, the second and first insulating dielectric barrier layers are made of insulating materials. Compared with hole blocking layers of the same conductivity type with a higher doping concentration than the drift layer, this does not increase the doping concentration of the drift layer, and the blocking voltage of the IGBT does not decrease when the IGBT is turned off. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of an insulated gate bipolar transistor.

[0026] Figure 2 This is a schematic diagram of the structure of the insulated gate bipolar transistor according to Embodiment 1 of the present invention;

[0027] Figure 3 This is a schematic diagram of the carrier motion trajectory in the insulated gate bipolar transistor of Example 1;

[0028] Figure 4 This is a schematic diagram of the structure of the insulated gate bipolar transistor according to Embodiment 2 of the present invention;

[0029] Figure 5 This is a schematic diagram of the carrier motion trajectory in the insulated gate bipolar transistor of Example 2.

[0030] Figure label:

[0031] 1. Emitter; 2. Insulating dielectric layer; 3. Gate dielectric layer; 4. Gate electrode; 5. Source region; 6. Well region; 8. Drift layer; 9. Electric field blocking layer; 10. Collector region; 11. Collector electrode; 71. First insulating dielectric barrier layer; 72. Second insulating dielectric barrier layer; 72a. First second sub-insulating dielectric barrier layer; 72b. Second sub-insulating dielectric barrier layer; 6'. Well region; 7'. Carrier storage layer; 8'. Drift layer; 72'. Second insulating dielectric barrier layer. Detailed Implementation

[0032] The technical solutions of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0033] Example 1

[0034] This invention provides an insulated gate bipolar transistor, such as... Figure 2 and Figure 3 As shown, it includes: a drift layer 8; a well region 6 located within the drift layer 8; a source region 5 located within the well region 6; a first insulating dielectric barrier layer 71 located in the drift layer 8 at the bottom of the well region 6 and adjacent to the well region 6; a second insulating dielectric barrier layer 72 disposed in the drift layers 8 on both sides of the well region 6 along the channel length direction, the distance from the second insulating dielectric barrier layer 72 to the top surface of the drift layer 8 being greater than zero; the first insulating dielectric barrier layer 71 and the second insulating dielectric barrier layer 72 cooperate to expose the boundary area between the bottom surface of the well region 6 and the sidewall of the well region 6.

[0035] By providing a first insulating dielectric barrier layer 71 at the bottom of the well region 6 and a second insulating dielectric barrier layer 72 in the drift layers 8 on both sides of the well region 6 along the channel length direction, the collection of holes in the well region 6 is reduced when the insulated gate bipolar transistor (IGBT) is turned on. This indirectly enhances the recombination of holes and electrons in the drift layers 8, increases the conductivity modulation effect of the IGBT, and reduces the on-state voltage drop of the IGBT. At the same time, the first insulating dielectric barrier layer 71 and the second insulating dielectric barrier layer 72 expose the boundary region between the bottom surface of the well region 6 and the sidewall of the well region 6. When the IGBT is turned off, the boundary region is less prone to electric field concentration, thus not increasing the turn-off loss of the IGBT. Moreover, the second insulating dielectric barrier layer and the first insulating dielectric barrier layer are insulating materials. Compared with using a hole barrier layer of the same conductivity type with a higher doping concentration than the drift layer, the doping concentration of the drift layer is not increased, and the blocking voltage of the IGBT does not decrease when the IGBT is turned off.

[0036] In the insulated gate bipolar transistor provided in this embodiment, the drift layer 8 and the well region 6 have opposite conductivity types, while the drift layer 8 and the source region 5 have the same conductivity type.

[0037] The drift layer 8 has an N-type conductivity. The well region 6 has a P-type conductivity. The source region 5 has an N-type conductivity.

[0038] The insulated gate bipolar transistor of this embodiment further includes: a collector region 10; a collector electrode 11 located on the back side of the collector region 10; an electric field blocking layer 9 located between the collector region 10 and the drift layer 8; an emitter 1 located on a portion of the source region 5 and a portion of the well region 6 and electrically connected to the source region 5 and the well region 6 respectively; a gate structure including a gate dielectric layer 3 and a gate electrode 4 located above the gate dielectric layer 3, the gate electrode 4 spanning the drift layer 8, a portion of the well region 6 and a portion of the source region 5 between adjacent well regions 6; an insulating dielectric layer 2 located above the source region 5 and the gate dielectric layer 3, and completely surrounding the gate dielectric layer 3 and the gate electrode 4; the gate electrode 4 can be a metal gate electrode or a polysilicon gate electrode.

[0039] The conductivity type of collector region 10 is opposite to that of drift layer 8. The conductivity type of collector region 10 is P-type. The material of collector 11 includes metal.

[0040] The conductivity type of the electric field blocking layer 9 is the same as that of the drift layer 8. The conductivity type of the electric field blocking layer 9 is N-type. The doping concentration of the electric field blocking layer 9 is higher than that of the drift layer, which mainly reduces the electric field between the drift layer 8 and the collector region 10 to almost zero in the electric field blocking layer 9, thereby reducing the conduction loss of the insulated gate bipolar transistor without reducing the breakdown voltage.

[0041] In one embodiment, such as Figure 3 As shown, the trajectory of electrons is from the source region 5 through the channel into the drift layer 8, and the trajectory of holes is sequentially through the collector region 10, the electric field blocking layer 9, the drift layer 8, and into the trap region 6.

[0042] In this embodiment, the materials of the second insulating dielectric barrier layer 72 and the first insulating dielectric barrier layer 71 include silicon dioxide.

[0043] In this embodiment, the distance from the top surface of the second insulating dielectric barrier layer 72 to the top surface of the drift layer 8 is greater than the channel depth of the insulated gate bipolar transistor (IGBT). This ensures that the second insulating dielectric barrier layer 72 does not block the channel. When the IGBT is turned on, electrons can freely travel along the channel from the source region through the well region into the drift layer, where they recombine with holes. This increases the conductivity modulation effect of the IGBT and reduces the on-state voltage drop of the IGBT.

[0044] In this embodiment, there are several well regions 6; these well regions 6 are spaced apart; each well region 6 has a second insulating dielectric barrier layer 72 on both sides along the channel length direction, and the second insulating dielectric barrier layer 72 between adjacent well regions 6 is not shared; for any two adjacent well regions 6, the second insulating dielectric barrier layer 72 adjacent to one well region 6 and the second insulating dielectric barrier layer 72 adjacent to the other well region 6 are spaced apart. This arrangement provides a channel for charge carriers to flow through, allowing the charge carriers to flow along a predetermined trajectory.

[0045] In this embodiment, for the second insulating dielectric barrier layer 72 located on any side of the well region 6 along the channel length direction and adjacent to the well region 6, the second insulating dielectric barrier layer 72 includes a first to an Nth second sub-insulating dielectric barrier layer arranged sequentially at intervals. The lateral distance between the first and Nth second sub-insulating dielectric barrier layers and the well region increases progressively, as does the depth of the first and Nth second sub-insulating dielectric barrier layers in the drift layer, where N is an integer greater than or equal to 2. By setting multiple second insulating dielectric barrier layers 72, the collection of holes by the well region can be effectively reduced, thereby indirectly enhancing hole recombination with electrons within the drift layer.

[0046] exist Figure 2Taking N as an example of 2, the second insulating dielectric barrier layer 72 includes a first second sub-insulating dielectric barrier layer 72a and a second second sub-insulating dielectric barrier layer 72b arranged sequentially at intervals. Specifically, the lateral distance between the first second sub-insulating dielectric barrier layer 72a and the well region increases to the lateral distance between the second second sub-insulating dielectric barrier layer 72b and the well region, and the depth of the first second sub-insulating dielectric barrier layer 72a in the drift layer increases to the depth of the second second sub-insulating dielectric barrier layer 72b in the drift layer.

[0047] In this embodiment, the shape of any k-th second sub-insulating dielectric barrier layer includes an ellipsoid, where k is an integer greater than or equal to 1 and less than or equal to N. Specifically, the first second sub-insulating dielectric barrier layer 72a is ellipsoidal in shape, and the second second sub-insulating dielectric barrier layer 72b is ellipsoidal in shape.

[0048] The shape of any kth second sub-insulating dielectric barrier layer can vary according to design requirements; its shape can be a regular or irregular square or circle.

[0049] In this embodiment, the shape of any k-th second sub-insulating dielectric barrier layer includes an ellipsoid, and the cross-section of any k-th second sub-insulating dielectric barrier layer in the direction parallel to the length of the channel and perpendicular to the top surface of the drift layer (i.e. Figure 2 The paper has a first central axis and a second central axis that are perpendicular to each other. The kth second sub-insulating dielectric barrier layer has a first diameter on the first central axis and a second diameter on the second central axis. The first diameter is smaller than the second diameter.

[0050] In this embodiment, the first diameters of the first to Nth second sub-insulating dielectric barrier layers are parallel to each other, and the second diameters of the first to Nth second sub-insulating dielectric barrier layers are parallel to each other. This arrangement of the second insulating dielectric barrier layers 72 helps to form a uniform multiple barrier for charge carriers, effectively reducing hole collection in the well region. Specifically, the first diameter of the first second sub-insulating dielectric barrier layer 72a is parallel to the first diameter of the second second sub-insulating dielectric barrier layer 72b, and the second diameters of the first second sub-insulating dielectric barrier layer 72a and the second second sub-insulating dielectric barrier layer 72b are parallel to each other.

[0051] In one embodiment, for the well region 6 and the second insulating dielectric barrier layer 72 adjacent to the well region 6, the distance from the vertex of any k-th second sub-insulating dielectric barrier layer 72 to the well region 6 is greater than the distance from the bottom point of the k-th second sub-insulating dielectric barrier layer to the well region 6. Specifically, the distance from the vertex of the first second sub-insulating dielectric barrier layer 72a to the well region 6 is greater than the distance from the bottom point of the first second sub-insulating dielectric barrier layer 72a to the well region 6, and the distance from the vertex of the second second sub-insulating dielectric barrier layer 72b to the well region 6 is greater than the distance from the bottom point of the second second sub-insulating dielectric barrier layer 72b to the well region 6. The advantage is that any k-th second sub-insulating dielectric barrier layer can block the trajectory of charge carriers over a larger area.

[0052] In another embodiment, for the well region and the second insulating dielectric barrier layer adjacent to the well region, the distance from the vertex of any k-th second sub-insulating dielectric barrier layer in the second insulating dielectric barrier layer to the well region is less than or equal to the distance from the bottom point of the k-th second sub-insulating dielectric barrier layer to the well region.

[0053] In one embodiment, the acute angle between the second diameter and the sidewall of the well region 6 is 45° to 60°. For example, the acute angle between the second diameter and the sidewall of the well region 6 is 45°, 50°, 55°, or 60°. If the angle is less than 45°, the channel left for electrons by the second insulating dielectric barrier layer 72 is too narrow, affecting the conductivity modulation effect of the insulated gate bipolar transistor. If the angle is greater than 60°, the effectiveness of the second insulating dielectric barrier layer 72 in preventing holes from entering the sidewall of the well region 6 from the drift layer 8 is weakened.

[0054] In one embodiment, the second diameter is 1 / 3 to 1 / 2 of the depth of the well region 6. For example, the second diameter is 1 / 3 or 1 / 2 of the depth of the well region 6. If the second diameter is less than 1 / 3 of the depth of the well region 6, the range of the movement trajectory of the carriers blocked by the same number of second sub-insulating dielectric barrier layers on the adjacent well region side is reduced, and the effect of the second insulating dielectric barrier layer 72 in effectively blocking holes from entering the sidewall of the well region 6 from the drift layer 8 is weakened. If the second diameter is greater than 1 / 2 of the depth of the well region, the same number of second sub-insulating dielectric barrier layers are provided on the adjacent well region side, and when the insulated gate bipolar transistor is turned off, it is easy to induce electric field concentration in the boundary region between the bottom surface of the well region 6 and the sidewall of the well region 6, which weakens the effect of reducing the turn-off loss of the insulated gate bipolar transistor.

[0055] In one embodiment, the first diameter is 1 / 5 to 1 / 3 of the depth of the well region 6. For example, the first diameter is 1 / 5, 1 / 4, or 1 / 3 of the depth of the well region 6. If the first diameter is less than 1 / 5 of the depth of the well region 6, any k-th second sub-insulating dielectric barrier layer is too thin in the direction in which holes enter the sidewall of the well region 6 from the drift layer 8. The hole current entering the well region 6 from the drift layer 8 is likely to break down any k-th second sub-insulating dielectric barrier layer, and the effective blocking effect of the second insulating dielectric barrier layer 72 on holes entering the sidewall of the well region 6 from the drift layer 8 is weakened. If the first diameter is greater than 1 / 3 of the depth of the well region 6, it will increase the complexity of the process implementation.

[0056] In one embodiment, the doping concentration of well region 6 is 3*10⁻⁶. 16 atom*cm -3 ~2*10 17 atom*cm -3 The depth of well region 6 is 0.5 μm to 5 μm.

[0057] In one embodiment, the doping concentration of source region 5 is 5*10. 18 atom*cm -3 ~1*10 20 atom*cm -3 The depth of source region 5 is 0.2μm ~ 0.5μm.

[0058] In one embodiment, the thickness of the gate dielectric layer 3 is 20 nm to 120 nm; the thickness of the gate electrode 4 is 0.5 μm to 1.5 μm.

[0059] In one embodiment, the doping concentration of the drift layer 8 is 5*10⁻⁶. 12 atom*cm -3 ~2*10 16 atom*cm -3 The thickness of drift layer 8 is 60μm ~ 700μm.

[0060] In one embodiment, the doping concentration of the electric field blocking layer 9 is 5*10⁻⁶. 15 atom*cm -3 ~5*10 17 atom*cm -3 The thickness of the electric field blocking layer 9 is 5μm ~ 20μm.

[0061] In one embodiment, the doping concentration of the collector region 10 is 1*10. 17 atom*cm -3 ~1*10 19 atom*cm -3 The thickness of the collector region 10 is 0.5μm ~ 5μm.

[0062] In one embodiment, the cell width is 10~45μm, which is the distance between the longitudinal central axes of adjacent well regions.

[0063] In one embodiment, the insulating dielectric layer 2 is made of silicon dioxide, and the thickness of the insulating dielectric layer 2 is 0.5 μm to 2 μm.

[0064] Example 2

[0065] The difference between this embodiment and Embodiment 1 is that, as Figure 4 and Figure 5 As shown, the second insulating dielectric barrier layer 72' adjacent to the well region has a continuous structure.

[0066] The second insulating dielectric barrier layer 72' is elongated.

[0067] In one embodiment, such as Figure 5 As shown, the trajectory of electrons is from the source region 5 through the channel into the drift layer 8, and the trajectory of holes is sequentially through the collector region 10, the electric field blocking layer 9, the drift layer 8, and into the trap region 6.

[0068] In this embodiment, the second insulating dielectric barrier layer 72' is in contact with the well region 6.

[0069] In other embodiments, the second insulating dielectric barrier layer is spaced apart from the well region, and the minimum distance between the second insulating dielectric barrier layer and the well region is less than or equal to the channel depth of the insulated gate bipolar transistor.

[0070] In one embodiment, the dimension of the second insulating dielectric barrier layer 72' in the direction perpendicular to the top surface of the drift layer 8 is 1 / 3 to 1 / 2 of the depth of the well region 6. For example, the dimension of the second insulating dielectric barrier layer 72' in the direction perpendicular to the top surface of the drift layer 8 is 1 / 3 or 1 / 2 of the depth of the well region 6; if the dimension of the second insulating dielectric barrier layer 72' in the direction perpendicular to the top surface of the drift layer 8 is less than 1 / 3 of the depth of the well region 6, the range by which the second insulating dielectric barrier layer 72' blocks holes from entering the sidewall of the well region 6 from the drift layer 8 is reduced, and the effectiveness of the second insulating dielectric barrier layer 72' in blocking holes from entering the sidewall of the well region 6 from the drift layer 8 is weakened; if the dimension of the second insulating dielectric barrier layer 72' in the direction perpendicular to the top surface of the drift layer 8 is greater than 1 / 2 of the depth of the well region 6, it will increase the complexity of the process implementation.

[0071] In one embodiment, the number of well regions 6 is several; the dimension of the second insulating dielectric barrier layer 72' in the direction parallel to the channel is 1 / 4 to 1 / 3 of the distance between adjacent well regions 6. For example, the dimension of the second insulating dielectric barrier layer 72' in the direction parallel to the channel is 1 / 4 or 1 / 3 of the distance between adjacent well regions 6; if the dimension of the second insulating dielectric barrier layer 72' in the direction parallel to the channel is less than 1 / 4 of the distance between adjacent well regions 6, the range by which the second insulating dielectric barrier layer 72' blocks holes from entering the sidewall of the well region 6 from the drift layer 8 is reduced, and the effective blocking effect of the second insulating dielectric barrier layer 72' on holes from entering the sidewall of the well region 6 from the drift layer 8 is weakened; if the dimension of the second insulating dielectric barrier layer 72' in the direction parallel to the channel is greater than 1 / 3 of the distance between adjacent well regions 6, the channel left for charge carriers between adjacent well regions 6 is too narrow, and the conductance modulation effect of the insulated gate bipolar transistor is weakened.

[0072] The parts in this embodiment that are the same as those in Embodiment 1 will not be described in detail.

[0073] Example 3

[0074] In this embodiment, the second insulating dielectric barrier layer adjacent to the well region has a continuous structure. The difference from Embodiment 2 is that the second insulating dielectric barrier layer is an ellipsoid.

[0075] The second insulating dielectric barrier layer is in contact with the well region. In other embodiments, the second insulating dielectric barrier layer is spaced from the well region, and the minimum distance between the second insulating dielectric barrier layer and the well region is less than or equal to the channel depth of the insulated gate bipolar transistor.

[0076] In one example, the second insulating dielectric barrier layer has a dimension of 1 / 3 to 1 / 2 of the depth of the well region in the direction perpendicular to the top surface of the drift layer.

[0077] The number of well regions is several; the dimension of the second insulating dielectric barrier layer in the direction parallel to the channel is 1 / 4 to 1 / 3 of the distance between adjacent well regions.

[0078] The parts in this embodiment that are the same as those in Embodiment 2 will not be described in detail.

[0079] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An insulated gate bipolar transistor, characterized in that, include: Drift layer; The trap region is located within the drift layer; The source region is located within the well region; A first insulating dielectric barrier layer is located in the drift layer at the bottom of the well region and is adjacent to the well region. The second insulating dielectric barrier layer is disposed in the drift layer on both sides of the well region along the length of the channel, and the distance from the second insulating dielectric barrier layer to the top surface of the drift layer is greater than zero. The first insulating dielectric barrier layer and the second insulating dielectric barrier layer expose the boundary area between the bottom surface of the well region and the sidewall of the well region; For a second insulating dielectric barrier layer located on any side of the trench length direction of the well region and adjacent to the well region, the second insulating dielectric barrier layer includes a first second sub-insulating dielectric barrier layer to an Nth second sub-insulating dielectric barrier layer arranged in sequence at intervals. The lateral distance between the first second sub-insulating dielectric barrier layer and the well region increases from the lateral distance between the Nth second sub-insulating dielectric barrier layer and the well region. The depth of the first second sub-insulating dielectric barrier layer in the drift layer increases from the depth of the Nth second sub-insulating dielectric barrier layer in the drift layer. N is an integer greater than or equal to 2. The shape of any k-th second sub-insulating dielectric barrier layer includes an ellipsoid, where k is an integer greater than or equal to 1 and less than or equal to N; In a cross-section parallel to the length of the channel and perpendicular to the top surface of the drift layer, any k-th second sub-insulating dielectric barrier layer has a first central axis and a second central axis that are perpendicular to each other. The k-th second sub-insulating dielectric barrier layer has a first diameter on the first central axis and a second diameter on the second central axis. The first diameter is smaller than the second diameter.

2. The insulated gate bipolar transistor according to claim 1, characterized in that, The materials of the second insulating dielectric barrier layer and the first insulating dielectric barrier layer include silicon dioxide.

3. The insulated gate bipolar transistor according to claim 1, characterized in that, The distance from the top surface of the second insulating dielectric barrier layer to the top surface of the drift layer is greater than the channel depth of the insulated gate bipolar transistor.

4. The insulated gate bipolar transistor according to claim 1, characterized in that, The number of well regions is several; for any two adjacent well regions, the second insulating dielectric barrier layer adjacent to one well region and the second insulating dielectric barrier layer adjacent to another well region are arranged alternately.

5. The insulated gate bipolar transistor according to claim 1, characterized in that, The first diameter of the first sub-insulating dielectric barrier layer to the first diameter of the Nth sub-insulating dielectric barrier layer are parallel to each other, and the second diameter of the first sub-insulating dielectric barrier layer to the second diameter of the Nth sub-insulating dielectric barrier layer are parallel to each other.

6. The insulated gate bipolar transistor according to claim 1, characterized in that, For the well region and the second insulating dielectric barrier layer adjacent to the well region, the distance from the vertex of any k-th second sub-insulating dielectric barrier layer to the well region is greater than the distance from the bottom point of the k-th second sub-insulating dielectric barrier layer to the well region.

7. The insulated gate bipolar transistor according to claim 6, characterized in that, The acute angle between the second diameter and the sidewall of the trap area is 45°~60°.

8. The insulated gate bipolar transistor according to claim 1, characterized in that, The second diameter is 1 / 3 to 1 / 2 of the depth of the well region.

9. The insulated gate bipolar transistor according to claim 1, characterized in that, The first diameter is 1 / 5 to 1 / 3 of the depth of the well region.

10. The insulated gate bipolar transistor according to claim 1, characterized in that, The second insulating dielectric barrier layer adjacent to the well region has a continuous structure.

11. The insulated gate bipolar transistor according to claim 10, characterized in that, The second insulating dielectric barrier layer is elongated or ellipsoidal.

12. The insulated gate bipolar transistor according to claim 10, characterized in that, The second insulating dielectric barrier layer is in contact with the well region.

13. The insulated gate bipolar transistor according to claim 10, characterized in that, The dimension of the second insulating dielectric barrier layer in the direction perpendicular to the top surface of the drift layer is 1 / 3 to 1 / 2 of the depth of the well region.

14. The insulated gate bipolar transistor according to claim 10, characterized in that, The number of well regions is several; the dimension of the second insulating dielectric barrier layer in the direction parallel to the channel is 1 / 4 to 1 / 3 of the distance between adjacent well regions.

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