An IGBT chip

Abstract

The application provides an IGBT chip, which solves the problem that when the current is large, the current shared by each bonding point on the chip increases, causing high energy accumulation near the bonding point during the switching process, increasing the local temperature rise, and thus causing latch-up failure. An embodiment of the application provides an IGBT chip, which comprises a bonding point located on one side surface of the IGBT chip; the IGBT chip comprises a first cell structure and a second cell structure; the position of the second cell structure corresponds to the position of the bonding point; the second cell structure is distributed in a strip shape on one side of the bonding point; and the structures of the first cell structure and the second cell structure are different.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an IGBT chip. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are important power devices widely used in inverters and other fields, acting as power switches. IGBT chips cannot be directly connected to specific circuits; they are typically packaged in modules to bring out the gate, emitter, and collector potentials, thus connecting to external circuits. In traditional IGBTs, when the current is low, the current shared by each bonding point on the chip is small, and heat energy can be dissipated quickly during switching. However, when the current is high, the current shared by each bonding point increases, leading to high energy accumulation near the bonding points during switching, causing increased local temperature rise. Since the front structure of the chip is connected to the bonding points, the increased temperature degrades the electrical parameters on the front of the chip, easily triggering latch-up failure. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an IGBT chip that solves the problem that when the current is large, the current shared by each bonding point on the chip increases, resulting in high energy accumulation near the bonding point during the switching process, causing local temperature rise and thus triggering latch-up failure.

[0004] An embodiment of the present invention provides an IGBT chip, comprising:

[0005] The bonding point is located on one side surface of the IGBT chip; the IGBT chip includes a first cell structure and a second cell structure; the position of the second cell structure corresponds to the position of the bonding point; the second cell structure is distributed in a strip shape on one side of the bonding point; the first cell structure and the second cell structure have different structures.

[0006] In one embodiment, the second cell structure includes a plurality of second sub-cell structures, which are arranged in a strip-like pattern on one side of the bonding point.

[0007] In one embodiment, the IGBT chip further includes a gate bus, wherein the extension direction of the second cell structure is perpendicular to the gate bus.

[0008] In one embodiment, the second cell structure includes a first feature region and a second feature region;

[0009] The first feature region includes: a first P-type doped region; the first P-type doped region is disposed between the first trench and the second trench;

[0010] The second feature region includes: a first hole blocking layer, a first P-type doped region, and a first channel region stacked together; the first hole blocking layer, the first P-type doped region, and the first channel region are disposed between the second trench and the third trench.

[0011] In one embodiment, the first cell structure includes: a second hole blocking layer, a second P-type doped region, and a second channel region stacked together; the second hole blocking layer, the second P-type doped region, and the second channel region are disposed between a fourth trench and a fifth trench.

[0012] In one embodiment, the first feature region further includes a plurality of contact holes; the contact holes extend inward to a predetermined depth on the upper surface of the first P-type doped region; the plurality of contact holes are spaced apart along the extension direction of the first P-type doped region.

[0013] In one embodiment, the first cell structure and the second cell structure have the same size.

[0014] In one embodiment, the doping dose of the first P-type doped region is 1.3 to 2 times that of the doping dose of the second P-type doped region.

[0015] In one embodiment, the doping dose of the first hole blocking layer is 1.2 to 1.5 times that of the second hole blocking layer.

[0016] In one embodiment, the width of the fourth groove is twice the width of the first groove; the width of the fourth groove is equal to the width of the fifth groove; the widths of the first groove, the second groove, and the third groove are equal.

[0017] The width of the second channel region is twice the width of the first channel region.

[0018] This invention provides an IGBT chip that enhances the anti-latch-up capability of cells near the bonding points at high junction temperatures through differentiated internal chip layout, thereby improving the chip's dynamic robustness without affecting its dynamic and static performance parameters. As the chip current density increases, the layout scheme proposed in this invention can significantly mitigate the electrical stress concentration caused by increased local junction temperature, achieving a comprehensive improvement in performance and reliability. Attached Figure Description

[0019] Figure 1 The diagram shows the current distribution near the bonding point in the prior art.

[0020] Figure 2 The diagram shows the bonding failure current and cell structure in the prior art.

[0021] Figure 3 The diagram shown is a top view of two cell structure layouts of an IGBT chip provided in an embodiment of the present invention.

[0022] Figure 4 The diagram shown is a schematic diagram of a trench gate structure with optimized cell layout provided in an embodiment of the present invention.

[0023] Figure 5 The diagram shown is a top view of two cell structure layouts of an IGBT chip provided in another embodiment of the present invention.

[0024] Figure 6 The diagram shown is a top view of two cell structure layouts of an IGBT chip provided in another embodiment of the present invention.

[0025] Figure 7 The diagram shows a layout schematic of two cell structure contact hole structures for an IGBT chip provided in an embodiment of the present invention.

[0026] Figure 8 The diagram shown is a cross-sectional view of two cell structures of an IGBT chip provided in an embodiment of the present invention.

[0027] Figure 9 The diagram shows a layout schematic of two cell structure contact hole structures for an IGBT chip provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In commonly used modular wire bonding packaging structures, several leads at the chip's emitter guide the internal current through the module terminals, and the current in cells near the bonding points must also be guided out through the bonding points. For example... Figure 1 The diagram shows the current conduction path at the bonding point in a conventional cell layout. At the bonding point, the current in nearby cells is conducted through the front metal layer, resulting in a localized temperature rise. Figure 2 As shown, when the temperature on the front side of the chip increases, the carrier mobility increases and the equivalent P-region resistance Rp increases. If there are fluctuations in the chip process (such as increased overlay, defects blocking P-type contacts, etc.) that generate thermoelectric positive feedback, Ih×Rp=0.7V, it is easy to cause local latch-up failure, which in turn leads to chip explosion.

[0030] To address the aforementioned issues, this invention proposes an IGBT chip that, through differentiated internal layout, significantly enhances the latch-up resistance of cells at bonding points. This reduces the risk of dynamic failure and improves manufacturing yield during chip process fluctuations. Specific implementation methods are described in the following embodiments.

[0031] This embodiment provides an IGBT chip, which includes: a bonding point located on one side surface of the IGBT chip; the IGBT chip includes a first cell structure and a second cell structure; the position of the second cell structure corresponds to the position of the bonding point; the second cell structure is distributed in a strip shape on one side of the bonding point; the first cell structure and the second cell structure have different structures.

[0032] like Figure 3 The diagram shows a chip with two different cell structure layouts. The second cell structure is distributed below the bonding points, while the first cell structure is distributed outside the bonding points. The second cell structure is not concentrated below the bonding points but rather distributed in a strip-like pattern. This maintains a regular cell layout on a macroscopic level, allowing electrical stress to be dispersed during switching and preventing concentration at the bonding points that could lead to failure.

[0033] like Figure 4 As shown, by using the IGBT chip described in this embodiment, the anti-latch-up capability of cells near the bonding point at high junction temperatures is enhanced by setting two different cell structures inside the chip, reducing potential failure risks and improving the dynamic robustness of the chip, while not affecting the dynamic and static performance parameters of the chip.

[0034] In one embodiment of the present invention, the second cell structure includes a plurality of second sub-cell structures, which are arranged in a strip-like parallel configuration on one side of the bonding point. In the above example ( Figure 3 Based on the layout shown, the following can be adopted: Figure 5 The layout is further optimized by using multiple second sub-cell structures arranged in a strip-like pattern near the bonding point, wherein a first cell structure is set between adjacent second sub-cell structures.

[0035] In one embodiment of the present invention, optionally, the IGBT chip further includes a gate bus, and the extension direction of the second cell structure is perpendicular to the gate bus. It can be understood that the distribution of the first cell structure and the second cell structure varies with the chip layout (see reference). Figure 6 As shown in the figure, the present invention does not limit the specific distribution of the first cell structure and the second cell structure.

[0036] In one example of the present invention, such as Figure 7 and Figure 8As shown, the second cell structure includes a first feature region and a second feature region; the first feature region includes a first P-type doped region 40; the first P-type doped region 40 is disposed between the first trench and the second trench 10; the second feature region includes a first hole blocking layer 50, the first P-type doped region 40 and the first channel region 30 stacked together; the first hole blocking layer 50, the first P-type doped region 40 and the first channel region 30 are disposed between the second trench 10 and the third trench.

[0037] The first cell structure includes: a second hole blocking layer 5, a second P-type doped region 4, and a second channel region 3 stacked together; the second hole blocking layer 5, the second P-type doped region 4, and the second channel region 3 are disposed between the fourth trench 1 and the fifth trench.

[0038] The second cell structure includes a first feature region and a second feature region. The structure of the second feature region is similar to that of the first cell structure. The first feature region has a special structural design, namely, it lacks a first hole blocking layer and a first channel region.

[0039] In one embodiment of the present invention, the first cell structure and the second cell structure have the same dimensions. To maintain similar dynamic and static properties between the first cell structure and the second cell structure, such as... Figure 7 The diagram shown is a top view of the structure. Figure 8 The diagram shows a cross-sectional view of the cells. The first cell structure is the main cell structure, and the second cell structure is a cell structure that enhances the latching capability at the bonding points. The first cell structure and the second cell structure have the same dimensions, i.e., c = d.

[0040] In one example of the present invention, such as Figure 7 and Figure 8 As shown, the first feature region further includes a first contact hole 20, which extends inward to a predetermined depth on the upper surface of the first P-type doped region 40; the second feature region further includes a second contact hole 20, which extends inward to a predetermined depth on the upper surfaces of the first channel region 30 and the first P-type doped region 40; the first cell structure includes a third contact hole 2, which extends inward to a predetermined depth on the upper surfaces of the second channel region 3 and the second P-type doped region 4.

[0041] The width of the third contact hole 2 is twice the width of the first contact hole 20; the width of the first contact hole 20 is equal to the width of the second contact hole 20.

[0042] Wherein, the width of the fourth groove 1 is twice the width of the first groove; the width of the fourth groove 1 is equal to the width of the fifth groove; the width of the first groove, the width of the second groove 10, and the width of the third groove are equal;

[0043] The width of the second channel region 3 is twice the width of the first channel region 30.

[0044] In one embodiment of the present invention, such as Figure 9 As shown, the first feature region also includes a plurality of contact holes 20; the contact holes 20 extend inward to a predetermined depth on the upper surface of the first P-type doped region; the plurality of contact holes 20 are distributed at intervals along the extension direction of the first P-type doped region.

[0045] To compromise on the chip's dynamic and static performance, compared to Figure 7 The layout shown employs a special design for the contact holes in the first feature region of the second cell structure. Unlike the contact holes in the second feature region, the contact holes 20 in the first feature region are divided into several contact holes of length m and interval n. Optionally, the size of m is 10 μm, and the size of n is taken as a compromise between 35 μm and 100 μm based on chip performance.

[0046] In one embodiment of the present invention, the doping dose of the first P-type doped region 40 is 1.3 to 2 times that of the second P-type doped region 4. Due to the influence of the process oxidation segregation coefficient, the doping dose of the first P-type doped region 40 is 1.3 to 2 times that of the second P-type doped region 4. The threshold voltage of the second cell structure is designed to be slightly lower than that of the first cell structure by 0.1V to 0.3V. This allows more holes to be shunted from nearby contact holes during turn-off, while the threshold voltage difference is small, avoiding localized concentration of electrical stress.

[0047] In one embodiment of the present invention, the doping dose of the first hole blocking layer 50 is 1.2 to 1.5 times that of the second hole blocking layer 5. The doping dose of the first hole blocking layer 50 in the second feature region is 1.2 to 1.5 times that of the second hole blocking layer 5. The doping dose is affected by the trench spacing; the smaller the trench spacing in the second feature region, the higher the doping dose of the first hole blocking layer 50 can be.

[0048] In this invention, in order not to affect the dynamic and static performance of the chip, the cell layout of the IGBT chip adopts a compensation method for matching design. By specially designing the second cell structure, the anti-latch-up capability of the bonding point cells is improved. In this way, the risk of dynamic failure is reduced when the chip process fluctuates, the process control window of the chip is widened, and the manufacturability and yield of finished products are improved.

[0049] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0050] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0051] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner.

[0052] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0053] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0054] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, top, bottom, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the figures). If the specific posture changes, the directional indication will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0055] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An IGBT chip, characterized in that, include: The bonding point is located on one side surface of the IGBT chip; the IGBT chip includes a first cell structure and a second cell structure; the position of the second cell structure corresponds to the position of the bonding point; the second cell structure is distributed in a strip shape on one side of the bonding point; the first cell structure and the second cell structure have different structures; The second cell structure includes a first feature region and a second feature region; The first feature region includes: a first P-type doped region; the first P-type doped region is disposed between the first trench and the second trench; The second feature region includes: a first hole blocking layer, a first P-type doped region, and a first channel region stacked together; the first hole blocking layer, the first P-type doped region, and the first channel region are disposed between the second trench and the third trench.

2. The IGBT chip according to claim 1, characterized in that, The second cell structure includes multiple second sub-cell structures, which are arranged in a strip-like pattern on one side of the bonding point.

3. The IGBT chip according to claim 1, characterized in that, The IGBT chip also includes a gate bus, and the extension direction of the second cell structure is perpendicular to the gate bus.

4. The IGBT chip according to claim 1, characterized in that, The first cell structure includes: a second hole blocking layer, a second P-type doped region, and a second channel region stacked together; the second hole blocking layer, the second P-type doped region, and the second channel region are disposed between the fourth trench and the fifth trench.

5. The IGBT chip according to claim 1, characterized in that, The first feature region also includes a plurality of contact holes; the contact holes extend inward to a predetermined depth on the upper surface of the first P-type doped region; the plurality of contact holes are distributed at intervals along the extension direction of the first P-type doped region.

6. The IGBT chip according to claim 4, characterized in that, include: The first cell structure and the second cell structure have the same size.

7. The IGBT chip according to claim 4, characterized in that, The doping dose of the first P-type doped region is 1.3 to 2 times that of the second P-type doped region.

8. The IGBT chip according to claim 4, characterized in that, The doping dose of the first hole blocking layer is 1.2 to 1.5 times that of the second hole blocking layer.

9. The IGBT chip according to claim 4, characterized in that, The width of the fourth groove is twice the width of the first groove; the width of the fourth groove is equal to the width of the fifth groove; the widths of the first groove, the second groove, and the third groove are equal; The width of the second channel region is twice the width of the first channel region.

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