Semiconductor element and method for manufacturing the same

Abstract

This invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a substrate and a gate structure. The substrate has a trench. The gate structure is disposed in the trench and includes a shielding gate, a control gate, a first insulating layer, a second insulating layer, and a third insulating layer. The shielding gate includes a lower gate and an upper gate. The lower gate includes a stepped structure composed of multiple electrodes, and the width of one of the electrodes decreases with distance from the upper gate. The upper gate is disposed on the lower gate, and the width of the upper gate is smaller than the width of the electrode in the lower gate closest to the upper gate. The control gate is disposed on the shielding gate. The first insulating layer is disposed between the shielding gate and the substrate. The second insulating layer is disposed on the shielding gate to separate the shielding gate from the control gate. The third insulating layer is disposed between the control gate and the substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a power semiconductor device and a method for manufacturing the same. Background Technology

[0002] Power semiconductor devices must have low gate-to-drain capacitance during operation to ensure sufficient responsiveness and avoid unnecessary losses during switching. The design of trench metal-oxide-semiconductor transistors with shielded gates effectively achieves this requirement.

[0003] As the size of manufactured power semiconductor devices continues to shrink, one of the current goals is to further increase the breakdown voltage and / or reduce the on-resistance of power semiconductor devices while maintaining low gate-to-drain capacitance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device can have an improved breakdown voltage and a reduced on-resistance while maintaining a low gate-to-drain capacitance.

[0005] The semiconductor device of the present invention includes a substrate and a gate structure. The substrate has a trench. The gate structure is disposed in the trench and includes a shielding gate, a control gate, a first insulating layer, a second insulating layer, and a third insulating layer. The shielding gate includes a lower gate and an upper gate. The lower gate includes a stepped structure composed of a plurality of electrodes, wherein the width of one of the electrodes decreases with distance from the upper gate. The upper gate is disposed on the lower gate, and the width of the upper gate is smaller than the width of the electrode in the lower gate closest to the upper gate. The control gate is disposed on the shielding gate. The first insulating layer is disposed between the shielding gate and the substrate. The second insulating layer is disposed on the shielding gate to separate the shielding gate from the control gate. The third insulating layer is disposed between the control gate and the substrate.

[0006] In one embodiment of the present invention, the lower gate includes a first conductive layer and a second conductive layer, wherein the second conductive layer is disposed on the first conductive layer and the second conductive layer includes a plurality of electrodes.

[0007] In one embodiment of the present invention, the second conductive layer includes a first electrode, a second electrode, and a third electrode stacked in sequence, wherein the width of the third electrode is greater than the width of the second electrode, and the width of the second electrode is greater than the width of the first electrode.

[0008] In one embodiment of the present invention, the width of the first electrode is greater than the width of the first conductive layer.

[0009] In one embodiment of the present invention, the semiconductor element further includes a substrate region and a source region. The substrate region is disposed in a substrate and located between adjacent trenches, and has a first conductivity type. The source region is disposed in the substrate region and has a second conductivity type. The first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

[0010] In one embodiment of the present invention, the height from the top surface of the first conductive layer to the bottom surface of the first conductive layer is 1.5 μm to 2.0 μm.

[0011] In one embodiment of the present invention, the height from the top surface of the first electrode to the bottom surface of the first electrode is 0.7 μm to 1.2 μm, the height from the top surface of the second electrode to the bottom surface of the second electrode is 0.7 μm to 1.2 μm, and the height from the top surface of the third electrode to the bottom surface of the third electrode is 0.3 μm to 0.6 μm.

[0012] In one embodiment of the present invention, the distance between the first electrode and the sidewall of the trench is... The distance between the second electrode and the sidewall of the trench is And the distance between the third electrode and the sidewall of the trench is

[0013] The method for manufacturing a semiconductor device according to the present invention includes the following steps. First, a substrate including a trench is provided, and an insulating material layer is formed on the substrate, wherein the trench includes a first accommodating space. Next, a shielding gate is formed in the trench, which includes the following steps. Step (a): Fill a first conductive material layer into the trench; Step (b): Remove a portion of the first conductive material layer into the trench to expose a portion of the first accommodating space; Step (c): Remove a portion of the insulating material layer into the trench using an isotropic etching process; Step (d): Repeat steps (b) to (c) multiple times to form a first conductive layer and a second accommodating space having a stepped structure in the trench; Step (e): Form a second conductive layer into the trench, wherein the second conductive layer partially fills the second accommodating space, and the second conductive layer includes a stepped structure composed of multiple electrodes; Step (f): Form a sacrificial layer in the second accommodating space of the trench, wherein the sacrificial layer is disposed on the sidewall of the trench to form a third accommodating space; and Step (g): Form a third conductive layer into the trench, wherein the third conductive layer partially fills the third accommodating space. Then, remove the sacrificial layer and a portion of the insulating material layer into the trench. Next, form a control gate in the trench. The width of one of the multiple electrodes included in the second conductive layer decreases as it moves further away from the third conductive layer, and the width of the third conductive layer is smaller than the width of the electrode in the second conductive layer that is closest to the third conductive layer.

[0014] In one embodiment of the present invention, the above-described step of forming the shielding gate in the trench is performed in a cycle of three steps (b) to (c).

[0015] In one embodiment of the invention, after the above steps of removing the sacrificial layer and a portion of the insulating material layer in the trench, an inter-gate insulating layer is further formed on the shielding gate, wherein the inter-gate insulating layer separates the shielding gate from the control gate.

[0016] In one embodiment of the present invention, after forming the control gate in the trench, the following steps are further performed. First, a substrate region having a first conductivity type is formed in the substrate, wherein the substrate region is located between adjacent trenches. Next, a source region having a second conductivity type is formed in the substrate region. The first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

[0017] Based on the above, in the semiconductor device and its manufacturing method provided by the present invention, the lower gate of the shielding gate has a stepped structure composed of multiple electrodes. Therefore, the semiconductor device of the present invention can have an improved breakdown voltage and a reduced on-resistance. Furthermore, by making the width of the upper gate of the shielding gate smaller than the width of the electrode in the lower gate closest to it, the present invention avoids an increase in gate-to-drain capacitance, thereby maintaining the electrical properties of the semiconductor device of the present invention. Attached Figure Description

[0018] Figures 1A to 1O This is a cross-sectional schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0019] Symbol Explanation

[0020] 10: Semiconductor components

[0021] 100: Base

[0022] 100T: Top surface

[0023] 110, 400, IL: Insulation layer

[0024] 110a, 110b, 110c, 110d, 110e: Insulating material layers

[0025] 112: First insulating layer

[0026] 114: Second Insulation Layer

[0027] 116: Third Insulation Layer

[0028] 118: Fourth Insulation Layer

[0029] 120: First conductive layer

[0030] 120a, 120b, 120c: Conductive material layers

[0031] 130: Second conductive layer

[0032] 132: First electrode

[0033] 134: Second electrode

[0034] 136: Third electrode

[0035] 140: Third conductive layer

[0036] 200: Basal region

[0037] 300: Source Region

[0038] 500A, 500B: Contact Window

[0039] 600A, 600B: Interconnect layer

[0040] CG: Control Gate

[0041] G: Gate structure

[0042] SA: Sacrificial Layer

[0043] SG: Shielding gate

[0044] SG1: Lower gate

[0045] SG2: Upper gate

[0046] SP1: First Compartment Space

[0047] SP21, SP22, SP23: Second Accommodation Space

[0048] SP3: Third Compartment Space

[0049] T: Trench

[0050] W1: First width

[0051] W21, W22_1, W22_2, W23_1, W23_2, W23_3: Second width

[0052] W3: Third width Detailed Implementation

[0053] In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type; however, the invention is not limited thereto. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. The P-type doping is, for example, boron, and the N-type doping is, for example, phosphorus or arsenic.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0055] The schematic diagrams in this document are merely illustrative of embodiments of some parts of the invention. Therefore, the shape, number, and scale of the various elements shown in the schematic diagrams should not be used to limit the invention.

[0056] Figures 1A to 1O This is a cross-sectional schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0057] Please refer to Figure 1A First, a substrate 100 is provided. In this embodiment, the substrate 100 is an epitaxial layer, but the invention is not limited thereto. The substrate 100 may be formed, for example, in a silicon substrate (not shown) via a selective epitaxial growth (SEG) process, and the invention is not limited thereto. In some embodiments, the doping concentration of the epitaxial layer may be less than the doping concentration of the silicon substrate.

[0058] Subsequently, a plurality of trenches T are formed in the substrate 100. In some embodiments, the method for forming the plurality of trenches T may, for example, perform the following steps, but the invention is not limited thereto. First, a mask layer (not shown) is formed on the substrate 100; then, a patterning process is performed using the mask layer as a mask to remove a portion of the substrate 100; next, the mask layer is removed.

[0059] Next, an insulating material layer 110a is conformally formed on the substrate 100. Specifically, the insulating material layer 110a may be formed, for example, in a trench T and extend from the surface of the trench T, covering the top surface 100T of the substrate 100. In some embodiments, the method of forming the insulating material layer 110a may include thermal oxidation or chemical vapor deposition, wherein the material of the insulating material layer 110a may include silicon oxide. After the insulating material layer 110a is conformally formed on the substrate 100, the trench T has a first accommodating space SP1. The first accommodating space SP1 mentioned herein refers to an accommodating space in the trench T where no conductive material layer has been formed or is not occupied by a conductive material layer, which, for example, has a substantially fixed first width W1.

[0060] The following embodiment will describe the steps of forming a shielding gate in the trench T. Please refer to... Figure 1BA conductive material layer 120a is filled into the trench T. In this embodiment, in addition to being formed in the trench T, the conductive material layer 120a may also cover the top surface 100T of the substrate 100, such as... Figure 1B As shown, but not limited thereto. In some embodiments, the method of forming the conductive material layer 120a may include performing a chemical vapor deposition process, wherein the material of the conductive material layer 120a may include doped polycrystalline silicon.

[0061] Please refer to Figure 1C A portion of the conductive material layer 120a is removed from the trench T. Removing the portion of the conductive material layer 120a from the trench T can be performed, for example, the following steps, but the invention is not limited thereto. First, a planarization process is performed on the conductive material layer 120a (if the conductive material layer 120a is formed on the top surface 100T of the substrate 100; conversely, this step can be omitted if the conductive material layer 120a is not formed on the top surface 100T of the substrate 100 in other embodiments), so that the top surface of the conductive material layer 120a is substantially flush with the top surface 100T of the substrate 100. Next, an etching process is performed to remove a portion of the conductive material layer 120a from the trench T, forming a conductive material layer 120b and exposing a portion of the first accommodating space SP1. The etching process described above can include a wet etching process or a dry etching process, and the invention is not particularly limited thereto. In this embodiment, the first accommodating space SP1 has a first width W1 that is substantially the same as the width of the conductive material layer 120b, but the invention is not limited thereto. In some embodiments, the trench T may have an arc-shaped bottom surface, and therefore, the conductive material layer 120b may also have an arc-shaped bottom surface.

[0062] Please refer to Figure 1DA portion of the insulating material layer 110a is removed from the trench T using an isotropic etching process. Specifically, a portion of the insulating material layer 110a located on the top surface 100T of the substrate 100 and a portion of the insulating material layer 110a located on the sidewalls of the trench T are removed. The isotropic etching process described above may include, for example, a wet etching process, and the present invention is not particularly limited thereto. After removing a portion of the insulating material layer 110a from the trench T, an insulating material layer 110b and a second accommodating space SP21 are formed. The second accommodating space SP21 mentioned herein refers to the accommodating space in the trench T where the conductive material layer 120b is not formed after the removal of a portion of the insulating material layer 110a, and has a second width W21. By using an isotropic etching process to remove a portion of the insulating material layer 110a, the second width W21 of the second accommodating space SP21 can be greater than the first width W1 of the first accommodating space SP1. Additionally, it should be noted that although this embodiment uses an isotropic etching process to remove part of the insulating material layer 110a, the present invention is not limited thereto. That is, any removal process that can remove at least part of the insulating material layer 110a located on the sidewall of the trench T can be used.

[0063] Please refer to Figure 1E A portion of the conductive material layer 120b is removed from the trench T. Removing the portion of the conductive material layer 120b from the trench T can be achieved, for example, by using an insulating material layer 110b as a mask in an etching process, but this invention is not limited thereto. The etching process described above can include wet etching or dry etching, and this invention is not particularly limited thereto. After removing the portion of the conductive material layer 120b from the trench T, a conductive material layer 120c is formed, exposing a portion of the first accommodating space SP1.

[0064] Please refer to Figure 1FA portion of the insulating material layer 110b is removed from the trench T using an isotropic etching process. Specifically, a portion of the insulating material layer 110b on the top surface 100T of the substrate 100 and a portion of the insulating material layer 110b on the sidewalls of the trench T are removed. The isotropic etching process described above may include, for example, a wet etching process, and the present invention is not particularly limited thereto. After removing a portion of the insulating material layer 110b from the trench T, an insulating material layer 110c and a second accommodating space SP22 are formed. The second accommodating space SP22 mentioned herein refers to the accommodating space in the trench T where the conductive material layer 120c is not formed after the removal of a portion of the insulating material layer 110b. The second accommodating space SP22 has a stepped shape including a step, wherein the platform segment has a second width W22_1 and the first step segment has a second width W22_2, and the second width W22_1 is greater than the second width W22_2. Furthermore, because an isotropic etching process is used to remove a portion of the insulating material layer 110b, both the second width W22_1 and the second width W22_2 are greater than the first width W1. From another perspective, the trench T may have, for example, an annular stepped shape, but this invention is not limited thereto. It should also be noted that although this embodiment utilizes an isotropic etching process to remove a portion of the insulating material layer 110b, this invention is not limited thereto; that is, any removal process capable of removing at least a portion of the insulating material layer 110b located on the sidewalls of the trench T can be used.

[0065] Please refer to Figure 1G A portion of the conductive material layer 120c is removed from the trench T. Removing the portion of the conductive material layer 120c from the trench T can be achieved, for example, by using an insulating material layer 110c as a mask for an etching process, but this invention is not limited thereto. The etching process described above can include wet etching or dry etching, and this invention is not particularly limited thereto. After removing the portion of the conductive material layer 120c from the trench T, a first conductive layer 120 is formed, exposing a portion of the first accommodating space SP1. In this embodiment, the first conductive layer 120 also has a first width W1.

[0066] Please refer to Figure 1HA portion of the insulating material layer 110c is removed from the trench T using an isotropic etching process. Specifically, a portion of the insulating material layer 110c located on the top surface 100T of the substrate 100 and a portion of the insulating material layer 110c located on the sidewalls of the trench T are removed. The isotropic etching process described above may include, for example, a wet etching process, and the present invention is not particularly limited thereto. After removing a portion of the insulating material layer 110c from the trench T, an insulating material layer 110d and a second accommodating space SP23 are formed. The second accommodating space SP23 mentioned herein refers to the accommodating space in the trench T where the first conductive layer 120 is not formed after the removal of a portion of the insulating material layer 110c from the sidewalls of the trench T. The second accommodating space SP23 has a stepped shape including two steps, wherein the platform segment has a second width W23_1, the first stepped segment has a second width W23_2, and the second stepped segment has a third width W23_3, wherein the second width W23_1 is greater than the second width W23_2, and the second width W23_2 is greater than the second width W23_3. Furthermore, due to the isotropic etching process used to remove a portion of the insulating material layer 110c, the second widths W23_1, W23_2, and W23_3 are all greater than the first width W1. From another perspective, the trench T may have, for example, an annular stepped shape, but the present invention is not limited thereto. It should also be noted that although this embodiment utilizes an isotropic etching process to remove a portion of the insulating material layer 110c, the present invention is not limited thereto; that is, any removal process capable of removing at least a portion of the insulating material layer 110a located on the sidewall of the trench T can be used.

[0067] It is worth noting here that, in the above... Figures 1C to 1H The fabrication process shown repeats the following steps three times: removing a portion of the conductive material layer in the trench T; and removing a portion of the insulating material layer using an isotropic etching process. However, the present invention does not limit the number of times the above-mentioned cycles are performed; that is, in other embodiments, the above steps may be repeated two (the minimum number of times to form the second accommodating space with a stepped shape) or four or more times.

[0068] Please refer to Figure 1IA second conductive layer 130 is formed in the trench T. The second conductive layer 130 is, for example, partially filled in the second accommodating space SP23. The formation of the second conductive layer 130 in the trench T may be performed by, for example, the following steps, but the present invention is not limited thereto. First, a second conductive material layer (not shown) is formed to fill the trench T. The second conductive material layer is planarized (if the second conductive material layer is formed on the top surface 100T of the substrate 100; otherwise, this step may be omitted if the second conductive material layer is not formed on the top surface 100T of the substrate 100) so that the top surface of the second conductive material layer is substantially flush with the top surface 100T of the substrate 100. Next, an etching process is performed to remove a portion of the second conductive material layer in the trench T, thereby forming the second conductive layer 130 and exposing a portion of the second accommodating space SP23. The etching process described above may include a wet etching process or a dry etching process, and the present invention is not particularly limited thereto. In this embodiment, the shape of the second conductive layer 130 is similar to that of the second accommodating space SP23, and it also has a stepped structure including two steps. The platform segment of the second conductive layer 130 has a second width W23_1, the first stepped segment of the second conductive layer 130 has a second width W23_2, and the second stepped segment of the second conductive layer 130 has a third width W23_3. The second width W23_1 is greater than the second width W23_2, and the second width W23_2 is greater than the second width W23_3. The material of the second conductive layer 130 is, for example, the same as that of the first conductive layer 120; that is, the material of the second conductive layer 130 may include, for example, doped polycrystalline silicon.

[0069] Please refer to Figure 1J A sacrificial layer SA is formed in the second accommodating space SP23 of the trench T. Forming the sacrificial layer SA in the second accommodating space SP23 of the trench T can be performed, for example, by the following steps, but the invention is not limited thereto. First, a sacrificial material layer (not shown) is conformally formed on the substrate 100. Specifically, the sacrificial material layer can be formed, for example, in the trench T and extends from the surface of the trench T and covers the top surface 100T of the substrate 100. In some embodiments, the method of forming the sacrificial material layer may include thermal oxidation or chemical vapor deposition. After the sacrificial material layer is conformally formed on the substrate 100, an etching process is performed to remove the sacrificial material layer located on the top surface 100T of the substrate 100 and at the bottom of the second accommodating space SP23 of the trench T, thereby forming the sacrificial layer SA on the sidewall of the trench T, wherein the sacrificial layer SA is disposed on the insulating material layer 110d. In this embodiment, the sacrificial layer SA on the sidewall of the trench T may define a third accommodating space SP3 having a third width W3. Because of the additional sacrificial layer SA compared to the second accommodating space SP23, the third width W3 of the third accommodating space SP3 is smaller than the second width W23_1 of the second accommodating space SP23.

[0070] Please refer to Figure 1K A third conductive layer 140 is formed in the trench T. The third conductive layer 140, for example, partially fills the third accommodating space SP3. Forming the third conductive layer 140 in the trench T may involve, for example, the following steps, but the invention is not limited thereto. First, a third conductive material layer (not shown) is formed to fill the trench T. A planarization process is performed on the third conductive material layer (if the third conductive material layer is formed on the top surface 100T of the substrate 100; conversely, if the third conductive material layer is not formed on the top surface 100T of the substrate 100, this step can be omitted) so that the top surface of the third conductive material layer is substantially flush with the top surface 100T of the substrate 100. Next, an etching process is performed to remove a portion of the third conductive material layer in the trench T, thereby forming the third conductive layer 140 and exposing a portion of the third accommodating space SP3. The etching process described above may include a wet etching process or a dry etching process, and the invention is not particularly limited thereto. In this embodiment, the third width W3 of the third accommodating space SP3 is substantially the same as the width of the third conductive layer 140, but the invention is not limited thereto. Furthermore, in this embodiment, the width of the third conductive layer 140 is smaller than the width of the electrode closest to the third conductive layer 140 in the second conductive layer 130. Specifically, the third width W3 of the third conductive layer 140 is smaller than the second width W23_1 of the platform segment of the second conductive layer 130. The material of the third conductive layer 140 is, for example, the same as the material of the first conductive layer 120 and the second conductive layer 130; that is, the material of the third conductive layer 140 may also include, for example, doped polysilicon.

[0071] Thus, the fabrication of the shielding gate SG in this embodiment is complete. The shielding gate SG can, for example, be composed of the aforementioned first conductive layer 120, second conductive layer 130, and third conductive layer 140. However, while the fabrication method of the shielding gate SG in this embodiment is described using the above method as an example, it is not limited thereto.

[0072] Please refer to Figure 1L The sacrificial layer SA and a portion of the insulating material layer 110d are removed from the trench T. Removing the sacrificial layer SA and a portion of the insulating material layer 110d from the trench T can be performed, for example, using an isotropic etching process, and can include either a wet etching process or a dry etching process; the invention is not particularly limited in this respect. After removing the sacrificial layer SA and a portion of the insulating material layer 110d from the trench T, an insulating material layer 110e is formed.

[0073] Please refer to Figure 1MAn insulating layer IL is formed on the shielding gate SG. In some embodiments, the method of forming the insulating layer IL may include thermal oxidation or chemical vapor deposition, wherein the material of the insulating layer IL may include silicon oxide. In this embodiment, in addition to being formed on the shielding gate SG in the trench T, the insulating layer IL may also extend, for example conformally, to the top surface of the shielding gate SG to the top surface 100T of the substrate 100, and cover the top surface 100T of the substrate 100.

[0074] Please refer to Figure 1N A control gate CG is formed in a trench T. Forming the control gate CG in the trench T may involve, for example, the following steps, but the invention is not limited thereto. First, a control gate material layer (not shown) is formed to fill the trench T. A planarization process is performed on the control gate material layer (if the control gate material layer is formed on the top surface 100T of the substrate 100; conversely, if the control gate material layer is not formed on the top surface 100T of the substrate 100, this step can be omitted) to make the top surface of the control gate material layer substantially flush with the top surface 100T of the substrate 100. Next, an etching process is performed to remove a portion of the control gate material layer in the trench T, thereby forming the control gate CG. The etching process described above may include a wet etching process or a dry etching process, and the invention is not particularly limited thereto. The material of the control gate CG is, for example, the same as the material of the shielding gate SG; that is, the material of the control gate CG may also include, for example, doped polysilicon. In this embodiment, the control gate CG and the shielding gate SG may constitute the gate portion of the gate structure G. In addition, the aforementioned insulating layer IL and insulating material layer 110e can together form insulating layer 110, wherein insulating layer 110 includes: a first insulating layer 112 located between shielding gate SG and substrate 100; a second insulating layer 114 located between control gate CG and shielding gate SG; a third insulating layer 116 located between control gate CG and substrate 100; and a fourth insulating layer 118 located on the top surface 100T of substrate 100, wherein the first insulating layer 112, the second insulating layer 114 and the third insulating layer 116 can, for example, form the insulating layer of gate structure G.

[0075] Please refer to Figure 10A substrate region 200 having a first conductivity type and a source region 300 having a second conductivity type are sequentially formed in a substrate 100. The substrate region 200 can be formed, for example, by performing an ion implantation process followed by a heat treatment process, wherein the dopant implanted in the ion implantation process is, for example, boron, but this invention is not limited thereto. Similarly, the source region 300 can also be formed, for example, by performing an ion implantation process followed by a heat treatment process, wherein the dopant implanted in the ion implantation process is, for example, phosphorus or arsenic, but this invention is not limited thereto. In some embodiments, the substrate region 200 is disposed between adjacent trenches T, and the source region 300 is disposed within the substrate region 200.

[0076] Please continue to refer to Figure 10 After a substrate region 200 having a first conductivity type and a source region 300 having a second conductivity type are sequentially formed in a substrate 100, an insulating layer 400 is formed on the substrate 100. The insulating layer 400 may, for example, cover the top surface of the insulating layer 110 and fill the trench T. In some embodiments, the method of forming the insulating layer 400 may include thermal oxidation or chemical vapor deposition, wherein the material of the insulating layer 400 may include silicon oxide. In this embodiment, the insulating layer 400 is used as an interlayer dielectric layer, but the invention is not limited thereto.

[0077] Please continue to refer to Figure 10 After forming an insulating layer 400 on a substrate 100, contact windows 500A and 500B are formed through the insulating layer 400 and the insulating layer 110, wherein contact windows 500A and 500B are each electrically connected to the source region 300 and the control gate CG, respectively. In some embodiments, the method of forming contact windows 500A and 500B may include performing the following steps: First, a mask layer (not shown) is formed on the top surface of the insulating layer 400; then, a patterning process is performed using the mask layer as a mask to remove portions of the insulating layer 400 and the insulating layer 110 to form a plurality of openings, wherein the plurality of openings expose portions of the source region 300 and portions of the control gate CG; next, the mask layer is removed; then, a conductor layer is filled into the plurality of openings to form contact windows 500A electrically connected to the source region 300 and contact windows 500B electrically connected to the control gate CG, respectively. In some embodiments, the method of forming the conductor layer may include performing a chemical vapor deposition process, wherein the material may include a metal, which may be tungsten.

[0078] Please continue to refer to Figure 10After forming contact windows 500A and 500B on the substrate 100, interconnect layers 600A and 600B are formed. Interconnect layers 600A and 600B are each electrically connected to contact windows 500A and 500B. In some embodiments, the method of forming interconnect layers 600A and 600B may include the following steps: First, an interconnect material layer (not shown) is formed on the insulating layer 400; then, a mask layer (not shown) is formed on the top surface of the insulating layer 400; next, a patterning process is performed using the mask layer as a mask to remove portions of the interconnect material layer, thereby forming interconnect layers 600A and 600B. In some embodiments, the method of forming interconnect layers 600A and 600B may include a chemical vapor deposition process or a physical vapor deposition process, wherein the material may include a metal, such as copper, aluminum, aluminum-copper, or other suitable metals.

[0079] This completes the fabrication of the semiconductor element 10 of the present invention.

[0080] Although the manufacturing method of the semiconductor element 10 in this embodiment is described using the above method as an example, the manufacturing method of the semiconductor element 10 of the present invention is not limited thereto.

[0081] Please continue to refer to Figure 10 , Figure 10 A cross-sectional schematic diagram of a semiconductor element 10 according to an embodiment of the present invention is shown. It should be noted that the following description of omitted parts can be referred to the foregoing description and effects of the embodiments, and will not be repeated in the following embodiments.

[0082] In some embodiments, the semiconductor element 10 includes a substrate 100, a gate structure G, a substrate region 200, and a source region 300.

[0083] The substrate 100 is, for example, an epitaxial layer having a second conductivity type. For example, the substrate 100 may be an N-type epitaxial layer, but the present invention is not limited thereto. The substrate 100 has, for example, a plurality of trenches T, and the gate structure G, which will be described later, is disposed in the trenches T.

[0084] The gate structure G is disposed in a trench T, for example, and includes a shielding gate SG, a control gate CG, a first insulating layer 112, a second insulating layer 114, and a third insulating layer 116. The shielding gate SG includes, for example, a lower gate SG1 and an upper gate SG2 disposed on the lower gate SG1, wherein the lower gate SG1 is, for example, composed of the aforementioned first conductive layer 120 and second conductive layer 130, and the upper gate SG2 is, for example, composed of the aforementioned third conductive layer 140. In this embodiment, the lower gate SG1 includes a stepped structure composed of multiple electrodes, and the width of one of the electrodes decreases as it moves further away from the upper electrode SG2. More specifically, the lower gate SG1 includes a stepped structure composed of the aforementioned first conductive layer 120 and second conductive layer 130.

[0085] The first conductive layer 120 is, for example, approximately rectangular in shape and has a first width W1. In some embodiments, the height from the top surface to the bottom surface of the first conductive layer 120 is 1.5 μm to 2.0 μm. The first conductive layer 120 may, for example, have an arc-shaped bottom surface, but the invention is not limited thereto.

[0086] The second conductive layer 130, for example, has a stepped structure. In this embodiment, the second conductive layer 130 has a stepped structure including two steps, and includes a first electrode 132, a second electrode 134, and a third electrode 136 stacked sequentially, but the invention is not limited thereto. In some embodiments, the height from the top surface of the first electrode 132 to the bottom surface of the first electrode 132 is 0.7 μm to 1.2 μm, the height from the top surface of the second electrode 134 to the bottom surface of the second electrode 134 is 0.7 μm to 1.2 μm, and the height from the top surface of the third electrode 136 to the bottom surface of the third electrode 136 is 0.3 μm to 0.6 μm. Additionally, in some embodiments, the distance between the first electrode 132 and the sidewall of the trench T is... The distance between the second electrode 134 and the sidewall of the trench T is And the distance between the third electrode 136 and the sidewall of the trench T is

[0087] The third conductive layer 140 is also, for example, approximately rectangular in shape and has a third width W3. In some embodiments, the height from the top surface to the bottom surface of the third conductive layer 140 is 0.1 μm to 0.3 μm. Additionally, in some embodiments, the distance between the third conductive layer 140 and the sidewall of the trench T is...

[0088] From another perspective, in this embodiment, the third electrode 136 (the platform segment of the second conductive layer 130) has a second width W23_1, the second electrode 134 (the first step segment of the second conductive layer 130) has a second width W23_2, and the first electrode 132 (the second step segment of the second conductive layer 130) has a second width W23_3, wherein the second width W23_1 is greater than the second width W23_2, the second width W23_2 is greater than the second width W23_3, and the second width W23_3 is greater than the first width W1. In this embodiment, the width of the upper gate SG2 is smaller than the width of the electrode in the lower gate SG1 closest to the upper gate SG2. Specifically, the electrode closest to the upper gate SG2 is the third electrode 136 in the second conductive layer 130, such as... Figure 10 As shown, the upper gate SG2 has a third width W3 that is smaller than the second width W23_1 of the third electrode 136. The control gate CG is disposed on, for example, the shielding gate SG and separated by a second insulating layer 114. In some embodiments, the control gate CG and the shielding gate SG may comprise similar materials, which may be doped polysilicon.

[0089] A first insulating layer 112 is disposed, for example, between the shielding gate SG and the substrate 100; a second insulating layer 114 is disposed, for example, on the shielding gate SG and serves as an inter-gate insulating layer to separate the shielding gate SG from the control gate CG; and a third insulating layer 116 is disposed, for example, between the control gate CG and the substrate 100. In some embodiments, the first insulating layer 112, the second insulating layer 114, and the third insulating layer 116 may comprise similar materials, such as silicon oxide.

[0090] A substrate region 200 is disposed, for example, in a substrate 100 and located between adjacent trenches T. In some embodiments, the substrate region 200 has a first conductivity type. For example, the substrate region 200 may be a P-type well region and include boron. A source region 300 is disposed, for example, in the substrate region 200. In some embodiments, the source region 300 has a second conductivity type. For example, the source region 300 may be an N-type well region and include phosphorus or arsenic.

[0091] In some embodiments, the semiconductor element 10 may further include contact window 500A, contact window 500B, interconnect layer 600A, and interconnect layer 600B. The materials, functions, and manufacturing methods of contact window 500A, contact window 500B, interconnect layer 600A, and interconnect layer 600B can be referred to the foregoing embodiments, and will not be repeated here.

[0092] In this embodiment, by having the second conductive layer 130, including the shielding gate SG, have a stepped structure and the parameter design described above, the electric field distribution of the semiconductor element 10 in this embodiment can be improved, thereby increasing the breakdown voltage of the semiconductor element 10. Furthermore, since the second conductive layer 130 has a stepped structure, it means that the first insulating layer 112 disposed between the sidewall of the trench T and the shielding gate SG is also thinner than the corresponding insulating layer in prior art semiconductor elements. Therefore, the element spacing between the semiconductor elements 10 in this embodiment can be shortened, thereby reducing the on-resistance of the semiconductor element 10. Moreover, by making the third width W3 of the third conductive layer 140 smaller than the width of the electrode in the lower gate SG1 closest to the upper gate SG2 (the second width W23_1 of the third electrode 136), the semiconductor element 10 in this embodiment can avoid generating excessively high gate-to-drain capacitance due to the stepped structure design of the second conductive layer 130, thereby avoiding increased losses during switching of the semiconductor element 10.

[0093] In summary, this invention provides a semiconductor device with a novel shielded gate design, wherein the shielded gate includes a lower gate and an upper gate, the lower gate comprising a stepped structure of multiple electrodes, and the width of the upper gate being smaller than the width of the electrode closest to it in the lower gate. Based on this, the semiconductor device of this invention can have an improved breakdown voltage and a reduced on-resistance, and can avoid an increase in gate-to-drain capacitance, thereby maintaining the electrical properties of the semiconductor device of this invention and improving its clamping capability.

Claims

1. A semiconductor element, comprising: The base has grooves; as well as A gate structure, disposed in the trench, includes: The shielding gate includes a lower gate and an upper gate disposed on the lower gate. The lower gate comprises a stepped structure consisting of multiple electrodes, and the width of one of the electrodes decreases with increasing distance from the upper gate. The width of the upper gate is smaller than the width of the electrode in the lower gate closest to the upper gate; A control gate is disposed on the shielding gate; A first insulating layer is disposed between the shielding gate and the substrate; A second insulating layer is conformally disposed on the shielding gate to separate the shielding gate from the control gate; and A third insulating layer is disposed between the control gate and the substrate. The lower gate includes a first conductive layer and a second conductive layer, wherein the second conductive layer is disposed on the first conductive layer and includes the plurality of electrodes. The second conductive layer includes a first electrode, a second electrode, and a third electrode stacked sequentially, wherein the width of the third electrode is greater than the width of the second electrode, and the width of the second electrode is greater than the width of the first electrode. The upper gate includes a third conductive layer, which is rectangular in shape and has a width smaller than that of the third electrode.

2. The semiconductor device of claim 1, wherein the width of the first electrode is greater than the width of the first conductive layer.

3. The semiconductor device of claim 1, further comprising: A substrate region, disposed in the substrate and located between adjacent trenches, has a first conductivity type; as well as The source region is disposed in the substrate region and has a second conductivity type. Wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

4. The semiconductor device of claim 1, wherein the height from the top surface of the first conductive layer to the bottom surface of the first conductive layer is 1.5 μm to 2.0 μm.

5. The semiconductor device of claim 1, wherein the height from the top surface of the first electrode to the bottom surface of the first electrode is 0.7 μm to 1.2 μm, the height from the top surface of the second electrode to the bottom surface of the second electrode is 0.7 μm to 1.2 μm, and the height from the top surface of the third electrode to the bottom surface of the third electrode is 0.3 μm to 0.6 μm.

6. The semiconductor device of claim 1, wherein the distance between the first electrode and the sidewall of the trench is 4000 Å to 4500 Å, the distance between the second electrode and the sidewall of the trench is 3000 Å to 3500 Å, and the distance between the third electrode and the sidewall of the trench is 2000 Å to 2500 Å.

7. A method for manufacturing a semiconductor device, comprising: A substrate including trenches is provided, on which an insulating material layer is formed, wherein the trenches include a first accommodating space; Forming a shielding gate in the trench includes the following steps: Step (a): Fill the trench with a first conductive material layer; Step (b): Remove a portion of the first conductive material layer in the trench to expose a portion of the first accommodating space; Step (c): Remove a portion of the insulating material layer in the trench using an isotropic etching process; Step (d): Repeat steps (b) to (c) multiple times to form a first conductive layer and a second accommodating space having a stepped structure in the trench; Step (e): A second conductive layer is formed in the trench, wherein the second conductive layer partially fills the second accommodating space, and the second conductive layer includes a stepped structure composed of a plurality of electrodes; Step (f): A sacrificial layer is formed in the second accommodating space of the trench, wherein the sacrificial layer is disposed on the sidewall of the trench to form a third accommodating space; and Step (g): A third conductive layer is formed in the trench, wherein the third conductive layer partially fills the third accommodating space; Remove the sacrificial layer and a portion of the insulating material layer in the trench; and A control gate is formed in the trench. The width of one of the plurality of electrodes included in the second conductive layer decreases as it moves further away from the third conductive layer, and the width of the third conductive layer is smaller than the width of the electrode in the second conductive layer that is closest to the third conductive layer.

8. The method of manufacturing a semiconductor element as claimed in claim 7, wherein in the step of forming the shielding gate in the trench, steps (b) to (c) are performed three times.

9. The method of manufacturing a semiconductor device as claimed in claim 7, wherein after the step of removing the sacrificial layer and a portion of the insulating material layer in the trench, the method further comprises forming an inter-gate insulating layer on the shielding gate, wherein the inter-gate insulating layer separates the shielding gate from the control gate.

10. The method of manufacturing a semiconductor device as claimed in claim 7, wherein after forming the control gate in the trench, the method further comprises: A substrate region having a first conductivity type is formed in the substrate, wherein the substrate region is located between adjacent trenches; as well as A source region having a second conductivity type is formed in the substrate region. Wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

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