A micro light-emitting diode, a micro light-emitting element and a display device thereof

Abstract

This invention discloses a micro light-emitting diode, a micro light-emitting element and a display device thereof, which combines the design of the matching positions of the double insulating layer material, the opening of the insulating layer and the electrode stack. The first insulating layer is not set at the opening of the insulating layer under the second electrode, thereby taking into account both the size of the active area and the chip manufacturing yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing, specifically relating to micro light-emitting diodes, micro light-emitting elements, and display devices thereof. Background Technology

[0002] Micro-LEDs (mLEDs) are currently a hot research topic for next-generation display light sources. They boast advantages such as low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, low energy consumption, and long lifespan. Furthermore, their power consumption is approximately 10% of that of LCDs and 50% of that of OLEDs. Compared to OLEDs, which are also self-emissive, mLEDs offer several times the brightness and can achieve high pixel density. These significant advantages make mLEDs a promising candidate to replace current OLEDs and LCDs as the light source for next-generation displays. However, mLEDs cannot yet be mass-produced due to numerous technical challenges that need to be overcome, one of the most important being improving the yield rate of micron-sized LED chips. Summary of the Invention

[0003] To address the issue of process yield in micro-light-emitting diodes (LEDs), such as chip yield or transfer yield, this invention proposes a micro-LED that can effectively improve process yield. The micro-LED has a semiconductor layer sequence, including a front side and a back side disposed opposite each other. From the front side to the back side, the semiconductor layer sequence sequentially includes: a first type semiconductor layer, a second type semiconductor layer, and an active layer between the two. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between the two.

[0004] The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer.

[0005] It also includes a first insulating layer and a second insulating layer. The first insulating layer has a first opening disposed on a first platform. A first metal electrode is at least partially disposed on the first platform and extends from the first platform within the first opening to the first insulating layer. The second insulating layer is disposed on a second platform and includes a portion of the first insulating layer. The first insulating layer extends from the first platform along the sidewall of the groove to the second platform. The second insulating layer has a second opening disposed on the second platform. A second metal electrode is at least partially disposed on the second platform and extends from the second platform within the second opening to the second insulating layer. The second insulating layer includes a first portion on which the second metal electrode is disposed and a second portion on which the second metal electrode is not disposed. The first portion of the second insulating layer does not include the first insulating layer.

[0006] The present invention also provides a micro-light-emitting element, comprising a substrate serving as a support and a micro-light-emitting diode (LED) serving as the main body. The substrate and the micro-light-emitting diode are connected by a bridge arm. The micro-light-emitting diode includes a semiconductor layer sequence, which includes a front side and a back side disposed opposite to each other. From the front side to the back side, the semiconductor layer sequence sequentially includes: a first type semiconductor layer, a second type semiconductor layer, and an active layer between the two. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer.

[0007] The bridge arm is a first insulating layer, which includes a first dielectric layer and a second dielectric layer. The material of the first dielectric layer is different from that of the second dielectric layer. The first dielectric layer is located between the second dielectric layer and the semiconductor layer sequence. The second dielectric layer is used to connect the bridge arm and the main body. The first dielectric layer is located on the surface of the second dielectric layer. There is a gap between the main body and the upper surface of the substrate. The thickness of the second dielectric layer is greater than that of the first dielectric layer. It also includes a second insulating layer. The second insulating layer is disposed on a second platform. The second insulating layer includes a portion of the first insulating layer. The first insulating layer extends from the first platform along the sidewall of the groove to the second platform. The second insulating layer has a second opening. The second opening is disposed on the second platform. The second metal electrode is at least partially disposed on the second platform. The second metal electrode extends from the second platform within the second opening to the second insulating layer. The second insulating layer includes a first portion on which the second metal electrode is disposed and a second portion on which the second metal electrode is not disposed. The first portion of the second insulating layer does not include the first insulating layer.

[0008] The present invention also provides a display device, including a circuit board on which any of the aforementioned micro light-emitting diodes are electrically connected. The micro light-emitting diodes described in this invention refer to light-emitting diode chips with dimensions of 100μm × 150μm or less, produced or obtained by removing a support substrate.

[0009] The beneficial effects of this invention include, but are not limited to, improving the reliability of micro light-emitting diodes, reducing process difficulty, and improving the overall product yield. Attached Figure Description

[0010] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. Furthermore, the figures are descriptive outlines and are not drawn to scale.

[0011] Figure 1 and Figure 2 These are cross-sectional and top views of the first embodiment of the present invention.

[0012] Figure 3 This is a cross-sectional view of the second embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of the background structure of the third embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of a partial cross-sectional structure of a wafer according to the third embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram of the core structure according to the fourth embodiment of the present invention;

[0016] Figure 7 This is a partial schematic diagram of the mass transfer in the fourth embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of the external structure of the fifth embodiment of the present invention;

[0018] Figure 9 This is a cross-sectional structural diagram of some embodiments of the fifth embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in the various embodiments of the present invention can be combined with each other, and the resulting technical solutions are all within the protection scope of the present invention.

[0020] To better implement the technology of the present invention, the transfer process involved in the present invention will be explained, and the existing transfer process will be briefly described.

[0021] See Figure 1 and Figure 2In a first embodiment of the present invention, a micro-light-emitting diode is provided, having a semiconductor layer sequence 110. The semiconductor layer sequence 110 includes a front side and a back side disposed opposite to each other. From the front side to the back side, the semiconductor layer sequence 110 includes a first type semiconductor layer 111 and a second type semiconductor layer 112, with an active layer 113 disposed between them. In this embodiment, the first type semiconductor layer 111 is an N-type semiconductor layer, and the second type semiconductor layer 112 is a P-type semiconductor layer. The back side of the semiconductor layer sequence 110 has a first groove G1, which includes a closed opening or a non-closed opening. The first groove G1 penetrates the second type semiconductor layer 112 and the active layer 113, exposing the first type semiconductor layer 111. The back side of the semiconductor layer sequence 110 includes a first mesa M1 within the first groove G1, a second mesa M2 on the second type semiconductor layer 112, and a first groove sidewall S1 located between them. In some micro-light-emitting diode manufacturing processes, the front surface of the first type semiconductor layer 111 is used to cooperate with the imprint 200 for mass transfer.

[0022] The back side of the semiconductor layer sequence 110 is provided with a first metal electrode 310 electrically connected to the first type semiconductor layer 111 and a second metal electrode 320 electrically connected to the second type semiconductor layer 112. In this embodiment, the first metal electrode 310 is connected to the first type semiconductor layer 111 and the second metal electrode 320 is connected to the second type semiconductor layer 112. As one implementation, a current spreading layer may also be provided between the second metal electrode 320 and the second type semiconductor layer 112, for example, a transparent conductive layer may be provided between them.

[0023] It also includes a first insulating layer 410 and a second insulating layer 420, which are made of silicon oxide, silicon nitride, or titanium oxide. The first insulating layer 410 has a first opening K1, which is disposed on a first mesa M1. The angle between the sidewall of the first opening K1 and the first mesa M1 is θ1. A first metal electrode 310 is at least partially disposed on the first mesa M1, extending from the first mesa M1 within the first opening K1 to the first insulating layer 410. The second insulating layer 420 is disposed on a second mesa M2. The dashed lines in the figure are only for illustrative purposes regarding the arrangement of the second insulating layer 420. The second insulating layer 420 includes a portion of the first insulating layer 410. The first insulating layer 410 extends from the first mesa M1 along the sidewall S1 of the first groove to the second mesa M2. The second insulating layer 420 has a second opening K2 disposed on the second mesa M2. A second metal electrode 320 is at least partially disposed on the second mesa M2, extending from the second mesa M2 within the second opening K2 to the second insulating layer 420. The aperture of the second opening K2 is 1 micrometer to 5 micrometers. By appropriately enlarging the aperture of the second opening K2, etching conditions can be improved, and the angle between the sidewall of the second opening K2 and the horizontal plane can be reduced. In this embodiment, the thickness of the second insulating layer 420 is greater than that of the first insulating layer 410, and the thickness of the first insulating layer 410 is 1 / 4 to 2 / 3 of the thickness of the second insulating layer 420. In this embodiment, the thickness of the first insulating layer 410 is 0.5 to 2 micrometers, and the thickness of the second insulating layer 420 is 1 to 3 micrometers. Reducing the thickness of the first insulating layer 410 helps improve the manufacturing yield of the first metal electrode 310 and avoids cracking around the first opening K1.

[0024] To more clearly illustrate the concept of this embodiment, the first insulating layer 410 and the second insulating layer 420 are distinguished by a dashed line. The second insulating layer 420 includes a first portion 421 on which the second metal electrode 320 is disposed and a second portion 422 on which the second metal electrode 320 is not disposed. The first portion of the second insulating layer 420 does not include the first insulating layer 410, that is, there is no first insulating layer 410 under the second metal electrode 320. For example, the first portion 421 of the second insulating layer 420 does not include the first insulating layer 410, and the material is silicon dioxide and titanium dioxide. The second portion 422 of the second insulating layer 420 includes the first insulating layer 410, and the material is silicon nitride, silicon dioxide and titanium dioxide. In this embodiment, the material composition of the first insulating layer 410 is not entirely the same as that of the second insulating layer 420. For example, the first insulating layer 410 is silicon oxide and silicon nitride, while the second insulating layer 420 includes silicon nitride, silicon oxide, and titanium oxide. Reducing the thickness and / or types of dielectric materials under the second metal electrode 320 increases the difficulty of process control when fabricating the angle between the sidewall of the second opening K1 and the second mesa M2. When the aperture of the second opening K2 is 1 to 5 micrometers, the etching conditions can be improved by appropriately enlarging the aperture of the second opening K2, thereby reducing the angle θ2 between the sidewall of the second opening K2 and the horizontal plane. If both the first insulating layer 410 and the second insulating layer 420 are simultaneously provided under the second metal electrode 320, the angle control of the second opening K2 becomes more difficult due to the different removal characteristics of different materials. Therefore, in this embodiment, the first insulating layer 410 is not provided in the dielectric layer under the second metal electrode 320. A third opening K3 is formed on the second insulating layer 420.

[0025] In this embodiment, the micro-LED is rectangular, with a short side length of no more than 15 micrometers, and the single-side dimension of the first mesa M1 is no more than 15 micrometers. Micrometer-scale LEDs, limited by application size requirements, cannot provide the same first mesa area as conventional LEDs. The area of ​​the first mesa M1 is smaller than the area of ​​the second mesa M2, which is 1 / 2 to 4 / 5 the area of ​​the second mesa M2. The second mesa M2 is the main light-emitting area. In this embodiment, the first mesa M1 is reduced in size, further increasing the area of ​​the light-emitting region.

[0026] Since the first opening K1 is located on the first mesa M1, the smaller the area of ​​the first mesa M1, the larger the light-emitting area and the higher the device efficiency. Therefore, the area of ​​the first opening M1 is smaller than the area of ​​the second opening M2. The aperture of the first opening K1 is 1 micrometer to 3 micrometers, and the aperture of the second opening K2 is 1 micrometer to 5 micrometers. Here, aperture refers to the maximum distance of the opening when viewed from above. The second opening K2 is located on the second mesa M2, and the aperture of the second opening K2 is greater than or equal to the aperture of the first opening K1, further reducing the manufacturing difficulty of the second opening K2. The angle between the first opening K1 and the horizontal plane is θ1, and the angle between the second opening K2 and the horizontal plane is θ2, where θ1 is not greater than θ2. The angle θ1 between the first opening K1 and the horizontal plane is 20° to 45°, and the angle θ2 between the second opening K2 and the horizontal plane is 20° to 60°. This embodiment reduces the angle between the first opening K1 and the horizontal plane in the dry etching process by controlling the type and thickness of the insulating layer dielectric material, especially reducing the difficulty of angle control.

[0027] In some embodiments of this example, the dielectric material of the first insulating layer 410 is one type, and the dielectric material of the second insulating layer 420 is two or more types. The dielectric material of the first insulating layer 410 is different from the dielectric material of the second insulating layer 420.

[0028] See Figure 3 In the second embodiment of the present invention, the second insulating layer 420 is located on the second mesa M2. The second insulating layer 420 includes an insulating reflective layer 423. The insulating reflective layer 423 is made of DBR, for example, composed of a periodic dielectric stack of silicon dioxide and titanium dioxide, with a period number greater than 3. The first insulating layer 410 extends from the first mesa M1 from the first groove sidewall S1 to the second mesa M2 and covers the insulating reflective layer 423, forming part of the second insulating layer 420. The first insulating layer 410 has a third opening K3, which exposes the insulating reflective layer 423. The third opening K3 is disposed on the insulating reflective layer 423. From the projection of the back side, the second opening K2 is disposed within the third opening K3. The second metal electrode 320 is disposed within the third opening K3. By reducing the thickness and / or material type of the dielectric layer below the second metal electrode 320, the removal process window is expanded, and removal is carried out by, for example, wet etching or dry etching. In order to further reduce the process difficulty of the second opening K2 and improve the controllability of the angle of the second opening K2, the present invention, as an example, adopts dry etching.

[0029] See Figure 4In conventional MicroLED transfer processes, such as high-pixel display chip manufacturing, the size of the microLED 100 is within 100μm × 150μm. This requires lamination and imprinting for the pickup and placement of ultra-thin and / or small devices. The design of this invention allows for the selection and application of these ultra-thin, fragile, and / or small devices through micro-transfer printing without damaging the chip itself.

[0030] The mass transfer method of micro-transfer printing allows for the decisive assembly and integration of arrays of microscale, high-performance devices onto non-native substrates. In its simplest embodiment, micro-transfer printing is analogous to using a rubber impression tool to transfer fluid-based ink from an inkpad onto paper. However, in micro-transfer printing, the "ink" is composed of high-performance solid-state semiconductor devices, and the "paper" can be a substrate containing circuit boards, films, plastics, or other semiconductors. The micro-transfer printing process utilizes a designed elastomer impression 200 coupled to a high-precision controlled printhead to selectively pick up and print large arrays of microscale devices onto non-native destination substrates.

[0031] refer to Figure 5 In the third embodiment of the present invention, based on embodiments 1 and 2, a micro-light-emitting element is provided to match micro-transfer printing. This element includes a fixed substrate 500 and a micro-light-emitting diode 100 as the main body. The fixed substrate 500 and the micro-light-emitting diode 100 are connected by a bridge arm 600. The micro-light-emitting diode 100 includes a semiconductor layer sequence 110, which includes a front side and a back side disposed opposite to each other. From the front side to the back side, the semiconductor layer sequence 110 sequentially includes: a first type semiconductor layer 111, a second type semiconductor layer 112, and an active layer between them. 113, the back side of the semiconductor layer sequence 110 has a first groove G1, the first groove G1 penetrates the second type semiconductor layer 112 and the active layer 113, exposing the first type semiconductor layer 111, the back side of the semiconductor layer sequence 110 includes a first mesa M1 in the first groove G1, a second mesa M2 on the second type semiconductor layer 112 and a groove sidewall S1 located between the two, the back side of the semiconductor layer sequence 110 is provided with a first metal electrode 310 electrically connected to the first type semiconductor layer 111 and a second metal electrode 320 electrically connected to the second type semiconductor layer 112.

[0032] The bridge arm 600 is made of the same material as the first insulating layer 410. The first insulating layer 410 includes a first dielectric layer 411 and a second dielectric layer 412. The material of the first dielectric layer 411 is different from that of the second dielectric layer 412. The first insulating layer 410 is disposed on the semiconductor layer sequence 110. The first dielectric layer 411 is located between the second dielectric layer 412 and the semiconductor layer sequence 110. The second dielectric layer 412 is used to connect the bridge arm 600 and the main body (micro-LED 100). For the sake of simplicity, the main body and the micro-LED 100 are integrated here. The micro-LED 100 is not limited to including the bridge arm 600. The first dielectric layer 411 is located on the surface of the second dielectric layer 412. There is a gap between the main body and the upper surface of the fixed substrate 500. The thickness of the second dielectric layer 412 is greater than the thickness of the first dielectric layer 411. The bridge arm 600 can directly contact the fixed substrate 500 or indirectly contact the fixed substrate 500 through the bridge pier 610.

[0033] It also includes a second insulating layer 420 disposed on the second platform M2. The second insulating layer 420 includes a portion of the first insulating layer 410. The first insulating layer 410 extends from the first platform M1 along the sidewall S1 of the first groove to the second platform M2. The second insulating layer 420 has a second opening K2 disposed on the second platform M2. The second metal electrode 320 is at least partially disposed on the second platform M2. The second metal electrode 320 extends from the second platform M2 within the second opening K2 to the second insulating layer 420. The second insulating layer 420 includes a first portion 421 on which the second metal electrode 320 is disposed and a second portion 422 on which the second metal electrode 320 is not disposed. The first portion 421 of the second insulating layer 420 does not include the first insulating layer 410.

[0034] The first insulating layer 410 has a first opening K1, which is disposed on the first platform M1. The first metal electrode 310 is at least partially disposed on the first platform M1 and extends from the first platform M1 within the first opening K1 to the first insulating layer 410.

[0035] In this embodiment, the thickness of the second dielectric layer 412 is 1.5 to 10 times the thickness of the first dielectric layer 411. The material of the first dielectric layer 411 is silicon oxide, and the first dielectric layer 411 is connected to the semiconductor layer sequence 110 of the main body. The material of the second dielectric layer 412 is silicon nitride. The thickness of the first dielectric layer 411 is 0.1 micrometer to 0.5 micrometer; the thickness of the second dielectric layer 412 is 0.15 micrometer to 0.3 micrometer, 0.3 micrometer to 0.8 micrometer, or 0.8 micrometer to 2 micrometer; and the width of the first dielectric layer 411 and the second dielectric layer 412 is 1 micrometer to 20 micrometers.

[0036] In this embodiment, the material of the first dielectric layer 411 is silicon oxide, such as silicon dioxide, and the material of the second dielectric layer 412 is silicon nitride. The first dielectric layer 411 includes at least the material in the negative stress direction, and the material of the second dielectric layer 412 includes at least the material in the normal stress direction.

[0037] In this embodiment, a first dielectric layer 411, which is thinner than the second dielectric layer 412 and is disposed on the main body, is used as a stress control layer to adjust the contact stress between the second dielectric layer 412 and the semiconductor layer sequence 110. In fact, the thickness of the bridging portion has a significant impact on the transfer yield. By removing the first dielectric layer 411 at the bridging portion between the bridge arm 600 (support structure) and the semiconductor layer sequence 110, the goal of balancing transfer yield is achieved. The arrangement and material selection of the first insulating layer 410 and the second insulating layer 420 as a whole balance electrode yield and transfer yield.

[0038] See Figure 6 In a fourth embodiment of the present invention, a schematic diagram is disclosed of a structure in which the micro-light-emitting element of Embodiment 3, after being mass-transfer imprinted, has a previously broken bridge arm 601 partially remaining on the main body. The first insulating layer 410 includes the remaining bridge arm 601, and the dielectric material of the second insulating layer 420 includes silicon oxide and titanium oxide, for example, silicon dioxide and titanium dioxide, or includes silicon oxide, silicon nitride, and titanium oxide, for example, silicon dioxide, silicon nitride, and titanium dioxide. In this embodiment, the remaining bridge arm 601 is the second dielectric layer 412.

[0039] See Figure 7 During the mass transfer process, the imprint 200 extrudes and prints on the micro LED 100. When the micro LED 100 has a first groove G1 on the side away from the imprint 200, for example, the N-type window layer of the semiconductor layer sequence 110 is provided with a first groove G1, especially when the side of the micro LED close to the imprint 200 is thinned, roughened or patterned etched and removed, the micro LED 100 is prone to breakage C1 at the first groove sidewall S1 and the first mesa M1.

[0040] See Figure 8In a fifth embodiment of the present invention, the back side of the semiconductor layer sequence has a first groove G1 with a Mesa mesa. In this embodiment, the patterned first groove G1 is used to provide a current injection window to the first type semiconductor layer 111. The first groove G1 sequentially penetrates the second type semiconductor layer 112, the active layer 113, and a portion of the first type semiconductor layer 111, exposing the first type semiconductor layer 111. Since the first type semiconductor layer 111 has a large thickness, a portion of the first type semiconductor layer 111 can serve as a support layer 120. On the vertical projection plane PD1 of the long side L1 of the support layer, at least a portion of the semiconductor layer sequence is penetrated by the first groove. This design is particularly suitable for vertical projection surfaces PD1 along the long side L1, where the length D1 of the semiconductor layer sequence through the region is 25% to 60% of the length of the long side L1. Due to the large-scale removal of the semiconductor layer sequence laterally, in this embodiment, the first metal electrode 310 is extended from the first mesa M1 along the groove sidewall S1 to the second mesa to provide support for the body. The first metal electrode 310 is further designed with stress, comprising multiple metal layers. The first metal layer of the first metal electrode 310 is in contact with the back side, and the deformation modulus of the first metal layer is not less than 100 GPa. The thickness of the first metal layer is 30 angstroms to 1000 angstroms. The first metal layer includes ruthenium, rhodium, or chromium.

[0041] A first metal electrode 310 and a second metal electrode 320 are disposed on the back side of the semiconductor layer sequence 110. The first metal electrode 310 and the second metal electrode 320 are used to connect to an external circuit. The back side of the semiconductor layer sequence 110 includes a first mesa M1, a second mesa M2 in the first groove G1, and a first groove sidewall S1 located between the two. The first metal electrode 310 is disposed on the first mesa M1, which is located on the bottom surface of the first groove G1. The second metal electrode 320 is disposed on the second mesa M2. The first metal electrode 310 is directly connected to the first type semiconductor layer 111, and the second metal electrode 320 is electrically connected to the second type semiconductor layer 112. For example, the second metal electrode 320 is connected to the second type semiconductor layer 112 through a transparent current spreading layer (not shown in the figure in this embodiment).

[0042] The first type semiconductor layer 111 serves as a support layer 120, providing support for the semiconductor layer sequence 110. Viewed from above, the support layer 120 is generally rectangular, with a length ratio of 1.5 to 5 for its long side L1 to its short side. This elongated design provides holding force. Considering the minimum thickness of the support layer and that the length-to-short side ratio is less than 1.5, the probability of breakage under stress is low. However, when the ratio is greater than 5, the probability of breakage increases significantly due to the increased torque. Vertically, the distance from at least a portion of the first groove G1 to the front side of the semiconductor layer sequence 110 is no greater than 4 micrometers, meaning the thickness of the first type semiconductor layer 111 within at least a portion of the first groove G1 is no greater than 4 micrometers. For example, the thickness of the first type semiconductor layer 111 within at least a portion of the first groove G1 is between 1 and 4 micrometers. On the top-view projection surface, the area of ​​the first groove G1 is 25% to 60% of the area of ​​the first type semiconductor layer 111. Here, the area refers to the area of ​​the entire first groove G1 region, excluding the boundary area of ​​the second mesa M2. When it is less than 25%, the problem of support layer breakage during the transfer process is basically not present due to the relatively small torque. When it exceeds 60%, the area loss of the light-emitting area is too large.

[0043] The first metal electrode 310 extends along the long side L1 of the support layer 120, and the extension covers the second mesa M2 from the first groove sidewall S1, reinforcing the stress concentration area where the thickness of the semiconductor layer sequence 110 varies significantly. The first metal electrode 310 comprises multiple metal layers, wherein the total thickness of the metal layers with a deformation modulus of not less than 100 GPa is 30 angstroms to 1000 angstroms. The high deformation modulus of the first metal layer ensures that the semiconductor layer sequence is prevented from being cut when subjected to shear force torque.

[0044] A dielectric passivation layer 400 is provided between the first metal electrode 310 and the second mesa M2, and between the first metal electrode 310 and the first groove sidewall S1. The dielectric passivation layer 400 electrically isolates the first metal electrode 310 and the second mesa M2. The material of the dielectric passivation layer 400 includes silicon oxide, silicon nitride, or a distributed Bragg reflector (DBR). For example, if the material of the dielectric passivation layer 400 is silicon dioxide, the thickness of the dielectric passivation layer 400 is 1,000 angstroms to 10,000 angstroms. When the first metal electrode 310 and the second mesa M2 are viewed from the short side projection plane, the coverage width D2 of the first metal electrode 310 on the second mesa M2 exceeds 20% of the length of the short side L2. For example, the coverage width D2 is 20% to 90% of the length of the short side L2, ensuring sufficient holding force.

[0045] The dielectric passivation layer 400 has a first opening K1 on the first mesa M1 and a second opening K2 on the second mesa M2. A first metal electrode 310 extends from the first mesa M1 within the first opening K1 to the dielectric passivation layer 400. A second metal electrode 320 extends from the second mesa M2 within the second opening K2 to the dielectric passivation layer 400. The dielectric passivation layer 400 is an insulating layer, and the number of dielectric material types in the dielectric passivation layer 400 on the first mesa M1 is less than the number of dielectric material types in the dielectric passivation layer 400 on the second mesa M2.

[0046] The first metal electrode 310 includes multiple metal layers. The first metal layer of the first metal electrode 310 is in contact with the back side. The deformation modulus of the first metal layer is not less than 100 GPa, and the thickness of the first metal layer is from 30 angstroms to 1000 angstroms. The first metal layer includes ruthenium, rhodium, or chromium.

[0047] See Figure 9 In some embodiments of this example, the micro-light-emitting diode undergoes a substrate removal process, exposing the front side of the semiconductor layer sequence 110. The front side of the semiconductor layer sequence 110 is a first-type semiconductor layer 111 or an undoped semiconductor layer, and at least part of the front side of the semiconductor layer sequence is removed. For example, the front side of the semiconductor layer sequence 110 may have a patterned or roughened surface.

[0048] As an example, to increase light emission from the front side and reduce total internal reflection, a common method involves using an etchant to remove a portion of the semiconductor material on the front side of the semiconductor layer sequence 110, forming a roughened second groove G2 on the surface. After roughening, the first type semiconductor layer 111 has a region with a thickness of no more than 4 micrometers in the vertical direction, for example, a thickness of 1 to 4 micrometers at the junction of the first mesa M1 and the second mesa M2.

[0049] The removal of some semiconductor layer sequences may improve optical performance, such as controlling the light pattern. However, it may cause some damage or potential problems to the front side of the first type semiconductor layer 111, i.e., the support layer. The front side of the semiconductor layer sequence 110 is covered by an insulating protective layer 700, which is exposed. In this embodiment, it is completely exposed, and the thickness of the insulating protective layer 700 is 2000 angstroms to 10000 angstroms. According to this embodiment, although independently setting the insulating protective layer 700 in the micro-light-emitting diode has the potential to reduce the probability of fracture anomalies and provide retention force on the front side, it is still difficult to completely avoid fracture anomalies.

[0050] In this embodiment, based on the insulating protective layer 700 covering the front side, combined with the reinforcement design of the first metal electrode 310, the first metal electrode 310 includes multiple metal layers. The first metal layer of the first metal electrode 310 (not shown in the figure of this embodiment) is in contact with the back side. The deformation modulus of the first metal layer is not less than 100 GPa, and the thickness of the first metal layer is 10 angstroms to 30 angstroms. The front side of the semiconductor layer sequence 110 is covered with an insulating protective layer 700. The thickness of the insulating protective layer 700 is 2000 angstroms to 10000 angstroms, which can reduce the thickness requirement of the first metal layer and help improve the flexibility of electrode thickness design, such as reducing the light absorption of the first metal layer.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A micro light-emitting diode having a semiconductor layer sequence, the semiconductor layer sequence including a front side and a back side disposed opposite to each other, the semiconductor layer sequence comprising, from the front side to the back side, the following: A first type semiconductor layer, a second type semiconductor layer, and an active layer between them are provided. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between them. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to a first type of semiconductor layer and a second metal electrode electrically connected to a second type of semiconductor layer. The feature is that it further includes a first insulating layer and a second insulating layer. The first insulating layer has a first opening disposed on a first platform. A first metal electrode is at least partially disposed on the first platform and extends from the first platform within the first opening to the first insulating layer. The second insulating layer is disposed on a second platform and includes a portion of the first insulating layer. The first insulating layer extends from the first platform along the sidewall of the groove to the second platform. The second insulating layer has a second opening disposed on the second platform. A second metal electrode is at least partially disposed on the second platform and extends from the second opening. The second insulating layer extends from the second platform inside the second insulating layer. The second insulating layer includes a first part on which a second metal electrode is disposed and a second part on which no second metal electrode is disposed. The first part of the second insulating layer does not include the first insulating layer. The thickness of the second insulating layer is greater than that of the first insulating layer. The thickness of the first insulating layer is 1 / 4 to 2 / 3 of the thickness of the second insulating layer. The angle between the first opening and the horizontal plane is θ1, and the angle between the second opening and the horizontal plane is θ2, wherein θ1 is not greater than θ2. The angle between the first opening and the horizontal plane θ1 is 20° to 45°, and the angle between the second opening and the horizontal plane θ2 is 20° to 60°.

2. A micro light-emitting diode according to claim 1, characterized in that, The second insulating layer has more types of dielectric materials than the first insulating layer.

3. A micro light-emitting diode according to claim 1, characterized in that, The thickness of the first insulating layer is 0.5 to 2 micrometers, and the thickness of the second insulating layer is 1 to 3 micrometers.

4. A micro light-emitting diode according to claim 1, characterized in that, The first insulating layer has one dielectric material, and the second insulating layer has two or more dielectric materials.

5. A micro light-emitting diode according to claim 1, characterized in that, The dielectric material of the first insulating layer is silicon oxide and / or silicon nitride, and the first insulating layer includes a residual bridge arm. The dielectric material of the second insulating layer includes silicon oxide and titanium oxide, or includes silicon oxide, silicon nitride and titanium oxide.

6. A micro light-emitting diode according to claim 1, characterized in that, The second opening is located on the second platform, and the diameter of the second opening is greater than or equal to the diameter of the first opening.

7. A micro light-emitting diode according to claim 1, characterized in that, The aperture of the first opening is 1 to 3 micrometers, and the aperture of the second opening is 1 to 5 micrometers.

8. A micro light-emitting diode according to claim 1, characterized in that, The micro-LED is rectangular, with the shorter side of the micro-LED not exceeding 15 micrometers, and the single-side dimension of the first mesa not exceeding 15 micrometers.

9. A micro light-emitting diode according to claim 1, characterized in that, The area of ​​the first countertop is smaller than the area of ​​the second countertop, and the area of ​​the first countertop is between 1 / 2 and 4 / 5 of the area of ​​the second countertop.

10. A micro light-emitting diode according to claim 1, characterized in that, The micro-light-emitting diode is rectangular, and the first metal electrode extends along the long side of the first type of semiconductor layer, with the extension covering the second mesa from the sidewall of the groove.

11. A micro light-emitting diode according to claim 1, characterized in that, Viewed from the vertical projection plane where the short side is located, the width of the coverage area of ​​the first metal electrode on the second platform exceeds 20% of the length of the short side.

12. A micro light-emitting diode according to claim 11, characterized in that, The width of the first metal electrode covering the second mesa is 20% to 90% of the length of the shorter side.

13. A micro light-emitting diode according to claim 11, characterized in that, The first type of semiconductor layer is a support layer for the micro light-emitting diode. When viewed from above, the support layer is rectangular. At least part of the groove is no more than 4 micrometers away from the front side of the semiconductor layer sequence. The thickness of the first type of semiconductor layer in the groove is 1 micrometer to 4 micrometers. The ratio of the long side to the short side of the rectangle is 1.5 to 5.

14. A micro light-emitting diode according to claim 11, characterized in that, After a substrate removal process, the front side of the semiconductor layer sequence is exposed, and the front side of the semiconductor layer sequence is a first type semiconductor layer or an undoped semiconductor layer, and at least part of the front side of the semiconductor layer sequence is removed.

15. A micro light-emitting diode according to claim 11, characterized in that, The front side of the semiconductor layer sequence has a patterned or roughened surface.

16. A micro light-emitting diode according to claim 11, characterized in that, The first metal electrode comprises multiple layers of metal, the first metal layer of the first metal electrode is in contact with the back side, the deformation modulus of the first metal layer is not less than 100 GPa, the thickness of the first metal layer is 30 angstroms to 1000 angstroms, and the first metal layer comprises ruthenium, rhodium or chromium.

17. A micro light-emitting diode according to claim 11, characterized in that, On the horizontal projection surface of the long side of the micro light-emitting diode, the semiconductor layer sequence includes a through region, the length of which is 25% to 60% of the length of the long side.

18. A micro light-emitting diode according to claim 1, characterized in that, The first insulating layer has a third opening, which is disposed on the second platform. From the projection of the rear side, the second opening is disposed within the third opening, and the second metal electrode is disposed within the third opening.

19. A micro-light-emitting element, comprising a fixed substrate and a micro-light-emitting diode as the main body, the fixed substrate and the micro-light-emitting diode being connected by a bridge arm, the micro-light-emitting diode comprising a semiconductor layer sequence, the semiconductor layer sequence comprising a front side and a back side disposed opposite to each other, the semiconductor layer sequence comprising, from the front side to the back side, the following: A first type semiconductor layer, a second type semiconductor layer, and an active layer between them are provided. The back side of the semiconductor layer sequence has a groove that penetrates the second type semiconductor layer and the active layer, exposing the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa within the groove, a second mesa on the second type semiconductor layer, and a groove sidewall located between them. A first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer are disposed on the back side of the semiconductor layer sequence. The feature is that the bridge arm is a first insulating layer, which includes a first dielectric layer and a second dielectric layer. The material of the first dielectric layer is different from that of the second dielectric layer. The first dielectric layer is located between the second dielectric layer and the semiconductor layer sequence. The second dielectric layer is used to connect the bridge arm and the main body. The first dielectric layer is located on the surface of the second dielectric layer. There is a gap between the main body and the upper surface of the fixed substrate. The thickness of the second dielectric layer is greater than that of the first dielectric layer. The system also includes a second insulating layer, which is disposed on a second platform. The second insulating layer includes a portion of the first insulating layer. The first insulating layer extends from the first platform along the sidewall of the groove to the second platform. The second insulating layer has a second opening, which is disposed on the second platform. At least a portion of the metal electrode is disposed on the second platform. The second metal electrode extends from the second platform within the second opening to the second insulating layer. The second insulating layer includes a first portion on which the second metal electrode is disposed and a second portion on which the second metal electrode is not disposed. The first portion of the second insulating layer does not include the first insulating layer. The thickness of the second insulating layer is greater than that of the first insulating layer. The thickness of the first insulating layer is 1 / 4 to 2 / 3 of the thickness of the second insulating layer. The angle between the first opening and the horizontal plane is θ1, and the angle between the second opening and the horizontal plane is θ2, wherein θ1 is not greater than θ2. The angle θ1 between the first opening and the horizontal plane is 20° to 45°, and the angle θ2 between the second opening and the horizontal plane is 20° to 60°.

20. A micro-light-emitting element according to claim 19, characterized in that, The first insulating layer has a first opening disposed on a first platform, and a first metal electrode is at least partially disposed on the first platform, extending from the first platform within the first opening to the first insulating layer.

21. A micro-light-emitting element according to claim 19, characterized in that, The thickness of the second dielectric layer is 1.5 to 10 times that of the first dielectric layer. The material of the first dielectric layer is silicon oxide. The first dielectric layer is sequentially connected to the semiconductor layer of the main body. The material of the second dielectric layer is silicon nitride. The thickness of the first dielectric layer is 0.1 micrometer to 0.5 micrometers. The thickness of the second dielectric layer is 0.15 micrometers to 0.3 micrometers, 0.3 micrometers to 0.8 micrometers, or 0.8 micrometers to 2 micrometers. The width of the first dielectric layer and the second dielectric layer is 1 micrometer to 20 micrometers.

22. A micro-light-emitting element according to claim 19, characterized in that, The first dielectric layer is made of silicon oxide, and the second dielectric layer is made of silicon nitride. The first dielectric layer includes at least the material in the negative stress direction, and the second dielectric layer includes at least the material in the normal stress direction.

23. A display device, comprising a circuit board, characterized in that, The invention includes a micro light-emitting diode as described in any one of claims 1 to 18, wherein the micro light-emitting diode is electrically connected to a circuit board.

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