Flip LED and its fabrication method

Abstract

This invention discloses a flip-chip light-emitting diode, comprising: a semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially, the semiconductor stack including a first region and a second region not overlapping the first region; a plurality of holes including a plurality of first holes and a plurality of second holes, the first holes and the second holes passing through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to expose a portion of the surface of the first semiconductor layer, the first holes being located in the first region, and the second holes being located in the second region; a first pad electrode formed on the first region of the semiconductor stack and electrically connected to the first semiconductor layer; a second pad electrode formed on the second region of the semiconductor stack and electrically connected to the second semiconductor layer; wherein, the area of ​​the surface of the first semiconductor layer in the first hole is smaller than the area of ​​the surface of the first semiconductor layer in the second hole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that emits light by releasing energy when charge carriers recombine. In particular, flip-chip LEDs have advantages such as no need for wire bonding, high luminous efficiency, and good heat dissipation, and their applications are becoming increasingly widespread.

[0003] Currently, flip-chip LEDs, due to their high current handling capability, have expanded their applications from conventional lighting to rail transportation, showing great promise and further market demand expected in the future. However, their unique P / N structure design results in a low lifespan, which remains a major bottleneck. In flip-chip LEDs, the N-bond electrodes are electrically connected to the N-GaN layer through multiple channels. Under high current injection, the current at the N-bond electrodes follows the shortest path, concentrating electrons on the N-side and diverting less to the P-side mesa, generating localized high heat and causing a decrease in the chip's reflectivity.

[0004] US Patent 9412907 discloses a vertical LED structure with non-uniform apertures to address current congestion effects in order to improve the luminous efficiency and uniformity of the light-emitting diode. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention provides a flip-chip light-emitting diode, comprising: a semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially, the semiconductor stack including a first region and a second region not overlapping the first region; a plurality of holes including a plurality of first holes and a plurality of second holes, the first holes and the second holes passing through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to expose a portion of the surface of the first semiconductor layer, the first holes being located in the first region, and the second holes being located in the second region; a first pad electrode formed on the first region of the semiconductor stack and electrically connected to the first semiconductor layer; a second pad electrode formed on the second region of the semiconductor stack and electrically connected to the second semiconductor layer; wherein, the area of ​​the surface of the first semiconductor layer in the first hole is smaller than the area of ​​the surface of the first semiconductor layer in the second hole.

[0006] The present invention provides yet another flip-chip light-emitting diode, comprising: a semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially, the semiconductor stack including a first region and a second region not overlapping the first region; a first insulating layer located above the first region and the second region of the semiconductor stack, including a first opening to expose a portion of the first semiconductor layer; a connection electrode including electrodes formed on the first insulating layer and within the first opening, and contacting the first semiconductor layer via the first opening; a first pad electrode formed on the first region of the semiconductor stack and electrically connected to the first semiconductor layer; and a second pad electrode formed on the second region of the semiconductor stack and electrically connected to the second semiconductor layer; wherein the area of ​​the connection electrode contacting the first semiconductor layer in the first region is smaller than the area of ​​the connection electrode contacting the first semiconductor layer in the second region. Attached Figure Description

[0007] Figure 1a This is a top view of the light-emitting diode disclosed in the first embodiment of the present invention;

[0008] Figure 1b for Figure 1a A magnified view of a top view of a light-emitting diode (LED).

[0009] Figure 2a for Figure 1a A cross-sectional view of the light-emitting diode of the first embodiment taken along the region A-A';

[0010] Figure 2b for Figure 2a A partially enlarged view of the cross-sectional view of a light-emitting diode;

[0011] Figures 3-10b This is a schematic diagram of the manufacturing method and structure of a light-emitting diode disclosed in the second embodiment of the present invention.

[0012] Figure 11 This is a top view of the hole distribution in a light-emitting diode disclosed in the third embodiment of the present invention;

[0013] Figure 12 This is a top view of the hole distribution in a light-emitting diode disclosed in the fourth embodiment of the present invention;

[0014] Figure 13 This is a top view of the hole distribution in a light-emitting diode disclosed in the fifth embodiment of the present invention.

[0015] Figure label:

[0016] 110 Substrate; 120 Semiconductor stack; 121 First semiconductor layer; 122 Second semiconductor layer; 123 Third semiconductor layer; 130 Transparent conductive layer; 140 Metal layer; 141 Reflective layer; 142 Barrier layer; 151 First insulating layer; 152 Second insulating layer; 160 Connecting electrode; 171 First pad electrode; 172 Second pad electrode; Q1 First region; Q2 Second region; 120a First hole; 120b Second hole; 1200 Surrounding portion; 151a First opening; 151b Second opening; 152a Third opening; 152b Fourth opening; 160a Fifth opening; 1101 First surface; 1211 First semiconductor layer surface; 1201 Semiconductor stack side; 130a Outer edge of transparent conductive layer; 141a Outer edge of reflective layer; 142a Outer edge of barrier layer; 1401 Metal layer surface. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0018] Figure 1a To illustrate a top view of a light-emitting diode according to a first embodiment of the present invention, Figure 1b for Figure 1a A magnified view of a top view of a light-emitting diode (LED). Figure 2a for Figure 1a A cross-sectional view of the light-emitting diode of the first embodiment taken along the region A-A'; Figure 2b for Figure 2a A magnified view of a section of a light-emitting diode.

[0019] Reference Figures 1a to 2b According to an exemplary embodiment of the present invention, the light-emitting diode 100 may include: a substrate 110, a semiconductor stack 120, a transparent conductive layer 130, a metal layer 140, a first insulating layer 151, a second insulating layer 152, a connecting electrode 160, a first pad electrode 171, and a second pad electrode 172.

[0020] The substrate 110 may have a first surface 1101. The substrate 110 may be formed using a carrier wafer suitable for semiconductor material growth. Furthermore, the substrate 110 may be formed of a material with excellent thermal conductivity or may be a conductive or insulating substrate. Additionally, the substrate 110 may be formed of a light-transmitting material and may have mechanical strength that does not cause bending of the entire semiconductor stack 120 and allows for effective division into separate chips through scribing and breaking processes. For example, the substrate 110 may use a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide (GaP) substrate, etc., with sapphire (Al2O3) substrates being particularly preferred. In this embodiment, the substrate 110 is a sapphire substrate with a series of protrusions on its surface, including, for example, protrusions without a fixed slope formed by dry etching, or protrusions with a certain slope formed by wet etching.

[0021] A semiconductor stack 120 may be disposed on a first surface 1101 of a substrate 110. The semiconductor stack 120 includes a first semiconductor layer 121, an active layer 122, and a second semiconductor layer 123, which are sequentially stacked on the substrate 110. The first semiconductor layer 121 and the second semiconductor layer 123 may have different conductivity types. If the first semiconductor layer 121 is an n-type semiconductor layer, then the second semiconductor layer 123 is a p-type semiconductor layer, or vice versa. The active layer 122 is located between the first semiconductor layer 121 and the second semiconductor layer 123.

[0022] The first semiconductor layer 121, the active layer 122, and the second semiconductor layer 123 may be formed of a group III gallium nitride (GaN) series compound semiconductor, such as GaN, AlN, InGaN, AlGaN, InAlGaN, and at least one thereof. The first semiconductor layer 121 is an electron-providing layer and can be formed by implanting an n-type dopant (e.g., Si, Ge, Se, Te, C, etc.). The second semiconductor layer 123 is a hole-providing layer and can be formed by implanting a p-type dopant (e.g., Mg, Zn, Be, Ca, Sr, Ba, etc.).

[0023] On the other hand, the first semiconductor layer 121 and the second semiconductor layer 123 may have a single-layer structure or a multi-layer structure, wherein layers with different compositions, thicknesses, etc., are stacked on top of each other. For example, each of the first semiconductor layer 121 and the second semiconductor layer 123 may include a carrier injection layer capable of improving the injection efficiency of electrons and holes, and may further have a superlattice structure formed in various ways.

[0024] The first semiconductor layer 121 may also include a current spreading layer (not shown) adjacent to the active layer 122. The current spreading layer may have a structure in which multiple AlxInyGa1-x-yN layers with different compositions or different impurity contents are repeatedly stacked, or it may be partially formed of an insulating material layer.

[0025] The second semiconductor layer 123 may also include an electron blocking layer (not shown) adjacent to the active layer 122. The electron blocking layer may have a structure in which multiple AlxInyGa1-x-yN layers with different compositions are stacked, or it may have at least one layer configured with AlyGa1-yN. The second semiconductor layer 123 may have a band gap larger than that of the active layer 122 to prevent electrons from crossing the second semiconductor layer 123.

[0026] The active layer 122 is a layer in which electrons provided by the first semiconductor layer 121 and holes provided by the second semiconductor layer 123 recombine to output light of a predetermined wavelength. It can be formed from a multilayer semiconductor thin film having a single-layer or multilayer quantum well structure with alternating stacked well and barrier layers. The active layer 122 may be formed with different material compositions or ratios depending on the wavelength of the output light. For example, the emission wavelength of the light-emitting diode in this embodiment is between 420 nm and 580 nm. The active layer 122 may be formed as a pair of well and barrier layers using group III to group V compound semiconductor materials (e.g., InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs(InGaAs) / AlGaAs, or GaP(InGaP) / AlGaP), but this disclosure is not limited thereto. The well layer may be formed from a material having a band gap smaller than that of the barrier layer.

[0027] Typically, in a flip-chip LED, the current injected into the second pad electrode 172 achieves good lateral current spread on the second semiconductor layer 123 through the all-surface metal layer 140 / transparent conductive layer 130. Current injection into the first pad electrode 171 is achieved through the contact between the connecting electrode 160 and the holes exposing a portion of the first semiconductor layer 121, where all holes are equally spaced and have the same diameter. However, as the size of the flip-chip LED increases, the current propagation capability of the entire flip-chip LED is affected under high current injection. Specifically, the current injected into the first pad electrode 171 will choose the shortest path, resulting in concentrated injection into the holes under the first pad electrode 171, with less extension to the holes under the second pad electrode 172. This causes the current injected into the first pad electrode 171 to not diffuse sufficiently across the entire first semiconductor layer 121, thus failing to produce a uniform current distribution and resulting in a higher current density in the semiconductor stack 120 under the first pad electrode 171. The high current density region can cause localized heating of the semiconductor stack 120 under the first pad electrode 171, which affects the reflectivity of the metal layer 140 due to localized overheating, thus reducing the light extraction efficiency of the LED. In addition, flip-chip LEDs will experience severe light decay due to localized overheating during long-term aging.

[0028] To address the above problems, the present invention proposes the following improvements, such as... Figures 1a to 2b As shown, the semiconductor stack 120 includes a first region Q1 and a second region Q2 that does not overlap with the first region Q1. The semiconductor stack 120 in the first region Q1 may include one or more first holes 120a formed through the second conductor layer 123, the active layer 122, and a portion of the first semiconductor layer 121 to expose a portion of the surface 1211 of the first semiconductor layer 121. The semiconductor stack 120 in the second region Q2 may include one or more second holes 120b formed through the second conductor layer 123, the active layer 122, and a portion of the first semiconductor layer 121 to expose a portion of the surface 1211 of the first semiconductor layer. The first holes 120a and the second holes 120b may be disposed on the semiconductor stack 120, and the bottom of the first holes 120a and the second holes 120b is located in the first semiconductor layer 121.

[0029] In one embodiment of the present invention, the area of ​​the first hole 120a of the first region Q1 exposing the surface 1211 of the first semiconductor layer is smaller than the area of ​​the second hole 120b of the second region Q2 exposing the surface 1211 of the first semiconductor layer. This is beneficial to “force” the current injected by the first pad electrode 171 to flow to the second hole 120b of the second region Q2, thereby mitigating the “current crowding” effect of the semiconductor stack 120 in the first region Q1. This can suppress the reduction in light efficiency caused by the decrease in reflectivity of the metal layer 140 due to local overheating of the semiconductor stack 120 in the first region Q1 and the serious light decay problem caused by long-term aging.

[0030] In one embodiment of the present invention, such as Figures 1a to 2b As shown, the aperture L1 of the first hole 120a in the first region Q1 is smaller than the aperture L2 of the second hole 120b in the second region Q2. This is beneficial for "forcing" the current injected into the first pad electrode 171 to flow to the second hole 120b in the second region Q2, thereby mitigating the "current crowding" effect of the semiconductor stack 120 in the first region Q1 and suppressing the decrease in reflectivity of the metal layer 140 due to local overheating of the semiconductor stack 120 in the first region Q1.

[0031] In one embodiment of the present invention, the opening shape of the first hole 120a and / or the second hole 120b includes a circle, an ellipse, a rectangle, a polygon, or any other shape. The first hole 120a and / or the second hole 120b can be arranged in multiple columns, and the first hole 120a and / or the second hole on any two adjacent columns or on each two adjacent columns can be aligned or staggered.

[0032] A transparent conductive layer 130 is formed on the semiconductor stack 120, and contacts the upper surface of the second semiconductor layer 123 to form an ohmic contact. The transparent conductive layer 130 can substantially contact almost the entire upper surface of the second semiconductor layer 123. In some embodiments, the transparent conductive layer 130 can contact the entire upper surface of the second semiconductor layer 123. In this structure, when current is supplied to the light-emitting diode, it can be distributed horizontally through the transparent conductive layer 130, and thus can be uniformly supplied to the entire second semiconductor layer 123.

[0033] The transparent conductive layer 130 can be made of ITO, InO, SnO, CTO, ATO, ZnO, GaP, or a combination thereof. The transparent conductive layer 130 can be formed by vapor deposition or sputtering. In this embodiment, the thickness of the transparent conductive layer 130 is selected from the range of 5 nm to 100 nm. Preferably, it is selected from the range of 10 nm to 50 nm.

[0034] A metal layer 140 is formed on the transparent conductive layer 130, wherein the metal layer 140 includes a reflective layer 141 and / or a barrier layer 142, and the reflective layer 141 is located between the transparent conductive layer 130 and the barrier layer 142. In one embodiment of the present invention, the outer edge 141a of the reflective layer 141 may be disposed inside or outside the outer edge 130a of the transparent conductive layer 130, or disposed to coincide with and align with the outer edge 130a of the transparent conductive layer 130, and the outer edge 142a of the barrier layer 142 may be disposed inside or outside the outer edge 141a of the reflective layer 141, or disposed to coincide with and align with the outer edge 141a of the reflective layer 141. In this embodiment, the outer edge 141a of the reflective layer 141 does not overlap with the outer edge 130a of the transparent conductive layer 130. The outer edge 130a of the transparent conductive layer 130 is outside the outer edge 141a of the reflective layer 141, allowing the area of ​​the transparent conductive layer 130 covering the semiconductor stack 120 to be larger than the area of ​​the reflective layer 141. This increases the contact area between the semiconductor light-emitting stack 120 and the transparent conductive layer 130, thereby reducing voltage. The outer edge 142a of the barrier layer 142 covers both the outer edge 141a of the reflective layer 141 and the outer edge 130a of the transparent conductive layer 130, thus strengthening the boundary adhesion of the barrier layer 142. This avoids the risk of ESD breakdown caused by the weak adhesion characteristics of the transparent conductive layer 130 and the unevenness of the interface.

[0035] In one embodiment of the present invention, the metal layer 140 may be formed as a single-layer or multi-layer structure of a conductive material having ohmic properties with the transparent conductive layer 130. The metal layer 140 may be formed of one or more materials and alloys thereof, including materials with a reflectivity greater than 60%, such as gold (Au), tungsten (W), platinum (Pt), silicon (Si), iridium (Ir), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), chromium (Cr), etc. Therefore, the current applied to the metal layer 140 can diffuse through the transparent electrode layer 130.

[0036] In one embodiment of the present invention, the barrier layer 142 covers the reflective layer 141 to prevent oxidation of the surface of the reflective layer 141 and thus deterioration of its reflectivity. The material of the barrier layer 142 includes metallic materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or alloys thereof. The barrier layer 142 may be a single layer or a stacked structure, such as titanium (Ti) / aluminum (Al) and / or titanium (Ti) / tungsten (W). In one embodiment of the present invention, the barrier layer 142 comprises a titanium (Ti) / tungsten (W) stacked structure on the side near the reflective layer 141 and a titanium (Ti) / aluminum (Al) stacked structure on the side away from the reflective layer 141. In one embodiment of the present invention, the materials of the reflective layer 141 and the barrier layer 142 include metal materials other than gold (Au) or copper (Cu), which can prevent the metal in the encapsulation solder, such as tin (Sn), from diffusing into the light-emitting diode during subsequent manufacturing processes and forming a co-metal with the metal materials inside the light-emitting diode, such as gold (Au) or copper (Cu), which would cause structural deformation of the light-emitting diode.

[0037] A first insulating layer 151 is located over a first region Q1 and a second region Q2 of the semiconductor stack 120. The first insulating layer 151 may cover the metal layer 140 and the adjacent semiconductor stack sidewalls 1201. Specifically, the first insulating layer 151 covers the sidewalls of the metal layer 140, the side surface of the second semiconductor layer 123, the side surface of the active layer 122, and a portion of the side surface of the first semiconductor layer 121. The first insulating layer 151 may include a first opening 151a that partially exposes the first semiconductor layer 121 and a second opening 151b that partially exposes the metal layer 140. The second opening 151b is located in the second region Q2. Additionally, the first insulating layer 151 may cover a portion of the sides and bottom surfaces of the first and second holes 120a and 120b, such that the first semiconductor layer 121 is partially exposed through the first and second holes 120a and 120b. That is, the first opening 151a can be positioned corresponding to the first hole 120a and the second hole 120b. In the semiconductor stack growth direction, the first opening 151a at least partially overlaps with either the first hole 120a or the second hole 120b. When the first hole 120a and the second hole 120b have inclined sides, the first insulating layer 151 disposed on the sides of the first hole 120a and the second hole 120b can be formed more stably.

[0038] In one embodiment of the present invention, such as Figures 1a to 2b As shown, in the plan view, the first opening 151a is located inside the first hole 120a or the second hole 120b.

[0039] In one embodiment of the present invention, such as Figures 1a to 2b As shown, the width W1 of the first opening 151a located above the first region Q1 is smaller than the width W2 of the first opening 151a located above the second region Q2.

[0040] The first insulating layer 151 can be a single layer or a stacked structure. When the first insulating layer 151 is a single layer, it can protect the sidewalls 1201 of the semiconductor stack 120 from damage to the active layer 122 by subsequent fabrication processes. When the first insulating layer 151 is a stacked structure, in addition to protecting the semiconductor stack 120, it can also form a Bragg mirror (DBR) structure by alternately stacking two or more materials with different refractive indices, selectively reflecting light of a specific wavelength. The first insulating layer 151 is formed of a non-conductive material, including organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic materials such as silicone, glass, or dielectric materials such as alumina (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

[0041] A connection electrode 160 is formed on a first region and a second region of the semiconductor stack 120. The connection electrode 160 may be disposed on a first insulating layer 151 and within a first opening 151a, and may at least partially cover the first insulating layer 151. The connection electrode 160 fills the first hole 120a and / or the second hole 120b and covers the first opening 151a to contact the first semiconductor layer 121, and extends to cover the surfaces of the first insulating layer 151 and the second semiconductor layer 123, wherein the connection electrode 160 is insulated from the second semiconductor layer 123 through the first insulating layer 151. The connection electrode 160 may contact the first semiconductor layer 121 to form an ohmic contact therewith.

[0042] In one embodiment of the present invention, the contact area between the connecting electrode 160 and the first semiconductor layer 121 through the first hole 120a in the first region Q1 is smaller than the contact area between the connecting electrode 160 and the first semiconductor layer 121 through the second hole 120b in the second region Q2. This facilitates the "forced" flow of current injected into the first pad electrode 171 to the second hole 120b in the second region Q2, preventing the connecting electrode 160 from melting and overflowing due to local overheating of the semiconductor stack 120 in the first region Q1 during high-current operation, or from poor contact and excessive voltage due to cracking. At the same time, this structure also enhances the current expansion of the light-emitting diode, further reducing the voltage of the light-emitting diode and improving the luminous efficiency.

[0043] In one embodiment of the present invention, such as Figures 1a to 2b As shown, the connecting electrode 160 includes a fifth opening 160a, which has a shape or number corresponding to the shape or number of the second opening 150b located above the second region Q2. The second opening 150b located above the second region may be surrounded by the fifth opening 160a. The fifth opening 160a has a width greater than the width of the second opening 150b. In the semiconductor stack growth direction, the fifth opening 160a and the second opening 151b at least partially overlap.

[0044] In one embodiment of this aspect, the top view of the fifth opening 160a shows an annular opening shape.

[0045] In one embodiment of the present invention, the connecting electrode 160 may be a single-layer or multi-layer structure. To reduce the resistance in contact with the first semiconductor layer 121, the material of the connecting electrode 160 includes metallic materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or alloys thereof. In another embodiment of the present invention, the material of the connecting electrode 160 includes metallic materials other than gold (Au) and copper (Cu). This prevents the metal in the encapsulation solder, such as tin (Sn), from diffusing into the light-emitting diode during subsequent manufacturing processes and forming an eutectic alloy with the internal metallic materials of the light-emitting diode, such as gold (Au) and copper (Cu), which could lead to structural deformation of the light-emitting diode.

[0046] In one embodiment of the invention, the material of the connecting electrode 160 comprises a metal with high reflectivity, such as aluminum (Al) or platinum (Pt).

[0047] In one embodiment of the present invention, the side of the connecting electrode 160 that contacts the first semiconductor layer 121 contains chromium (Cr) or titanium (Ti) to increase the bonding strength between the connecting electrode 160 and the first semiconductor layer 121.

[0048] The second insulating layer 152 is located on the first region Q1 and the second region Q2 of the semiconductor stack 120. The second insulating layer 152 can be disposed on the connecting electrode 160 and the first insulating layer 151. In this embodiment, the second insulating layer 152 can be located on the upper surface of the connecting electrode 160 and can extend continuously along the side surfaces of the connecting electrode 160 and the first insulating layer 151. The second insulating layer 152 may include a third opening 152a exposing a portion of the surface of the connecting electrode 160 and a fourth opening 152b exposing a portion of the surface of the metal layer 140. The third opening 152a is located on the first region Q1 of the semiconductor stack 120, and the fourth opening 152b is located on the second region Q2 of the semiconductor stack 120.

[0049] In one embodiment of the present invention, such as Figures 1a to 2b As shown, the third opening 152a and the fourth opening 152b are offset from the first hole 120a and the second hole 120b, and do not overlap. In other words, the third opening 152a and the fourth opening 152b are offset from the first opening 151a, and do not overlap. The fourth opening 152b can be positioned at the location corresponding to the second opening 151b, at least partially overlapping in the growth direction of the semiconductor stack 120. The width of the fourth opening 152b can be set to be larger, smaller, or the same as the width of the second opening 151b. In this embodiment, the width of the fourth opening 152b is set to be the same as the width of the second opening 151b. However, the width of the fourth opening 152b must be set to be smaller than the width of the fifth opening 160a in order to cover the connection electrode 160, so that the second pad electrode 172 is electrically insulated from the connection electrode 160.

[0050] The second insulating layer 152 may include an insulating material, such as SiO2, SiNx, MgF2, etc. Furthermore, the second insulating layer 152 may be composed of multiple layers and may include a distributed Bragg reflector in which insulating materials with different refractive indices are alternately stacked. The structure of the second insulating layer 152 including the distributed Bragg reflector reflects light that has passed through the omnidirectional reflector but is not reflected, thereby improving the luminous efficiency of the light-emitting device.

[0051] The first pad electrode 171 and the second pad electrode 172 can be disposed on the semiconductor stack 120 and partially cover the second insulating layer 152. The first pad electrode 171 can be disposed on a first region Q1 of the semiconductor stack 120 and electrically connected to the first semiconductor layer. The second pad electrode 172 can be disposed on a second region Q2 of the semiconductor stack 120 and electrically connected to the second semiconductor layer.

[0052] The first pad electrode 171 and the second pad electrode 173 are separated from each other and can be connected to the electrode 160 and the metal layer 140 through the third opening 152a and the fourth opening 152b of the second insulating layer 152. With this structure, the first pad electrode 171 and the second pad electrode 172 can be connected to an external power source to supply current to the semiconductor stack 120.

[0053] The first pad electrode 171 and the second pad electrode 172 may be composed of a single layer or multiple layers, and may include conductive materials. For example, each of the first pad electrode 171 and the second pad electrode 172 may include Au, Ti, Ni, Al, Ag, etc.

[0054] Each of the first pad electrode 171 and the second pad electrode 172 can have a thickness of tens of micrometers or more, for example, about 70 μm to about 80 μm. Using the first pad electrode 171 and the second pad electrode 172 within this thickness range, the light-emitting diode itself can be used as a chip-scale package. Furthermore, at least one side of each of the first pad electrode 171 and the second pad electrode 172 can be substantially parallel to the side of the semiconductor stack 120. However, it should be understood that the invention is not limited thereto, and other embodiments are possible.

[0055] Next, refer to Figures 3 to 10b The process for manufacturing a light-emitting diode according to this embodiment is described below.

[0056] like Figure 3 As shown, a method for manufacturing a light-emitting diode includes the step of forming a semiconductor stack 120, which includes providing a substrate 110 having a first surface 1101; and forming the semiconductor stack 120 on the first surface 1101 of the substrate 110, wherein the semiconductor stack 120 includes a first semiconductor layer 121, a second semiconductor layer 123, and an active layer 122 located between the first semiconductor layer 121 and the second semiconductor layer 123. The first semiconductor layer 121, the active layer 122, and the second semiconductor layer 123 may include the aforementioned layers formed on the substrate 110 using processes such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), etc.

[0057] like Figure 4a Top view and Figure 4b along Figure 4aAs shown in the cross-sectional view along line segment A-A', after the semiconductor stack 120 is formed on the substrate 110, the method for manufacturing the light-emitting diode includes a platform formation step. The semiconductor stack 120 is patterned by photolithography and etching, and the second semiconductor layer 123, the active layer 122, and a portion of the first semiconductor layer 121 are partially removed to form a surrounding portion 1200 around the semiconductor stack 120 to expose a portion of the surface 1211 of the first semiconductor layer 121, as well as a plurality of first holes 120a and second holes 120b to expose the side surfaces 1201 of the semiconductor stack 120 and a portion of the surface 1211 of the first semiconductor layer 121.

[0058] In one embodiment of the present invention, the semiconductor stack 120 includes a first region Q1 and a second region Q2 that does not overlap with the first region. A first hole 120a is located in the first region Q1, and a second hole 120b is located in the second region Q2.

[0059] In one embodiment of the present invention, the aperture L1 of the first hole 120a in the first region Q1 is smaller than the aperture L2 of the second hole 120b in the second region Q2. When a large external current is injected into the light-emitting diode, the current can be forced to the second hole 120b located in the second region Q2, which can alleviate the "current crowding" effect of the semiconductor stack 120 in the first region Q1 and suppress the decrease in reflectivity of the metal layer 140 due to local overheating of the semiconductor stack 120 in the first region Q1.

[0060] In one embodiment of the present invention, the surrounding portion 1200 is composed of... Figure 4a The top view of the light-emitting diode shown is a rectangular or polygonal ring.

[0061] The steps to form a successor platform, such as Figure 5a Top view and Figure 5b along Figure 5a As shown in the cross-sectional view along line segment A-A', the manufacturing method of a light-emitting diode includes a step of forming a transparent conductive layer 130. The transparent conductive layer 130 is formed on the conductive light-emitting stack 120 by means of physical vapor deposition or chemical vapor deposition. The area of ​​the transparent conductive layer 130 covering the semiconductor light-emitting stack 120 can be larger than the area of ​​the subsequent reflective layer 141, thereby increasing the contact area between the semiconductor light-emitting stack 120 and the transparent conductive layer 130, and thus reducing the voltage.

[0062] In one embodiment of the present invention, the step of forming the transparent conductive layer 130 is followed by, for example... Figure 6a Top view, Figure 6b Enlarged view of region D and Figure 6c along Figure 6aAs shown in the cross-sectional view along line segment A-A', the manufacturing method of a light-emitting diode includes a metal layer formation step. A metal layer 140 is directly formed on a transparent conductive layer 130 using methods such as physical vapor deposition or chemical vapor deposition. The metal layer 140 includes a reflective layer 141 and / or a barrier layer 142, with the reflective layer 141 located between the transparent conductive layer 130 and the barrier layer 142. The outer edge 141a of the reflective layer 141 does not overlap with the outer edge 130a of the transparent conductive layer 130. The outer edge 130a of the transparent conductive layer 130 is outside the outer edge 141a of the reflective layer 141, allowing the area of ​​the transparent conductive layer 130 covering the semiconductor light-emitting stack 120 to be larger than the area of ​​the reflective layer 141. This increases the contact area between the semiconductor light-emitting stack 120 and the transparent conductive layer 130, thereby reducing voltage. The outer edge 142a of the barrier layer 142 covers the outer edge 141a of the reflective layer 141 and the outer edge 130a of the transparent conductive layer 130. The barrier layer 142 encapsulates the transparent conductive layer 130, thereby strengthening the adhesion of the barrier layer 142 at its boundary. This prevents the reflective layer 141 from peeling and detaching due to the weak adhesion of the transparent conductive layer 130, and avoids the risk of ESD breakdown caused by uneven interface. The barrier layer 142 can prevent the components of the metal layer 141 (such as silver or aluminum) from diffusing when heated or electrically conductive (such as metallic aluminum or silver), and it can further enhance the reflective effect of the metal layer 141.

[0063] The following steps are followed by the formation of the metal layer 140, such as... Figure 7a Top view, Figure 7b Enlarged view of region E and Figure 7c along Figure 7a As shown in the cross-sectional view along line segment A-A', the manufacturing method of the light-emitting diode includes the step of forming a first insulating layer 151. The first insulating layer 151 is formed on the metal layer 140 by means of physical vapor deposition or chemical vapor deposition, and then the first insulating layer 151 is patterned by photolithography and etching to form a first opening 151a to expose the surface 1211 of the first semiconductor layer, and a second opening 151b to expose the surface 1401 of the metal layer. The second opening 151b is located on the second region Q2. The first insulating layer 151 may cover the metal layer 140 and the sidewalls 1201 of the adjacent semiconductor stack 120. Specifically, the first insulating layer 131 covers the sidewalls of the metal layer 140, the side surface of the second semiconductor layer 123, the side surface of the active layer 122, and a portion of the side surface of the first semiconductor layer 121.

[0064] In this embodiment, as Figure 7a Top view and Figure 7bAs shown in the cross-sectional view, the first opening 151a can be positioned corresponding to the first hole 120a and the second hole 120b. Therefore, the shape or number of the first opening 151a corresponds to the shape or number of the first hole 120a and the second hole 120b. The first opening 151a and the second opening 151b can have different shapes, widths, and numbers. When the first hole 120a and the second hole 120b have inclined sides, the first insulating layer 151 disposed on the sides of the first hole 120a and the second hole 120b can be formed more stably.

[0065] In one embodiment of this aspect, the width W1 of the first opening 151a located above the first region Q1 is smaller than the width W2 of the first opening 151a located above the second region Q2.

[0066] Following the formation step of the first insulating layer 151, in one embodiment of the present invention, as follows: Figure 8a Top view and Figure 8b along Figure 8a As shown in the cross-sectional view along line segment A-A', the manufacturing method of a light-emitting diode includes a step of forming a connecting electrode. A connecting electrode 160 is formed on a semiconductor stack 120 using methods such as physical vapor deposition or chemical vapor deposition. The connecting electrode 160 is then patterned using photolithography and etching to form a fifth opening 160a. The connecting electrode 160 is disposed on a first insulating layer 151 and may at least partially cover the first insulating layer 151. The connecting electrode 160 can contact the first semiconductor layer 121 through a first hole 120a and a second hole 120b that expose a portion of the surface 1211 of the first semiconductor layer. At this time, the connecting electrode 160 and the first semiconductor layer 121 form an ohmic contact.

[0067] In one embodiment of the present invention, the connecting electrode 160 can be configured such that the contact area of ​​the first semiconductor layer 121 partially exposed in the first hole 120a of the first region Q1 is smaller than the contact area of ​​the first semiconductor layer 121 partially exposed in the second hole 120b of the second region Q2. This is beneficial for "forcing" the current injected into the first pad electrode 171 to flow to the second hole 120b of the second region Q2, thus avoiding short circuits caused by the melting and overflow of the connecting electrode 160 due to local overheating of the semiconductor stack 120 of the first region Q1 during high-current use, or poor contact and excessive voltage due to cracking. At the same time, this structure also enhances the current expansion of the light-emitting diode, further reducing the voltage of the light-emitting diode and improving the luminous efficiency.

[0068] In one embodiment of the present invention, such as Figure 8a and 8bAs shown, the fifth opening 160a includes a shape or number corresponding to the shape or number of the second opening 150b located above the second region Q2. The second opening 150b located above the second region may be surrounded by the fifth opening 160a. The fifth opening 160a includes a width greater than the width of the second opening 150b. In the semiconductor stack growth direction, the fifth opening 160a at least partially overlaps with the second opening 151b. The top view of the fifth opening 160a shows an annular opening shape.

[0069] In one embodiment of the present invention, the step of forming the connecting electrode 160 is as follows: Figure 9a Top view and Figure 9b along Figure 9a As shown in the cross-sectional view along line segment A-A', the method for manufacturing a light-emitting diode includes a step of forming a second insulating layer 152. The second insulating layer 152 is formed on the semiconductor stack 120 by means of physical vapor deposition or chemical vapor deposition, and then patterned by photolithography and etching. The second insulating layer 152 can be disposed on the connecting electrode 160. In this embodiment, the second insulating layer 152 can be located on the upper surface of the connecting electrode 160 and can extend continuously along the side surfaces of the connecting electrode 160 and the first insulating layer 151. The second insulating layer 152 may include a third opening 152a partially exposing the connecting electrode 160 and a fourth opening 152b partially exposing the surface of the metal layer 140. The third opening 152a is located above the first region Q1 of the semiconductor stack 120, and the fourth opening 152b is located above the second region Q2 of the semiconductor stack 120. The fourth opening 152b can be disposed at a position corresponding to the second opening 151b, at least partially overlapping the second opening 151b in the growth direction of the semiconductor stack 120. The width of the fourth opening 152b can be set to be larger, smaller, or the same as the width of the second opening 151b. In this embodiment, the width of the fourth opening 152b is set to be the same as the width of the second opening 151b. However, the width of the fourth opening 152b must be set to be smaller than the width of the fifth opening 160a in order to cover the connecting electrode 160 and make the second pad electrode 172 electrically insulated from the connecting electrode 160.

[0070] Following the second insulating layer 152 formation step, in one embodiment of the present invention, as follows: Figure 10a Top view and Figure 10b along Figure 10aAs shown in the cross-sectional view along line segment A-A', the method for manufacturing a light-emitting diode includes the steps of forming a first pad electrode 171 and a second pad electrode 172. The first pad electrode 171 and the second pad electrode 172 are formed on a semiconductor stack 120 by means of electroplating, physical vapor deposition, or chemical vapor deposition. The first pad electrode 171 may be disposed on a first region Q1 of the semiconductor stack 120 and electrically connected to a first semiconductor layer. The second pad electrode 172 may be disposed on a second region Q2 of the semiconductor stack 120 and electrically connected to a second semiconductor layer.

[0071] In one embodiment of this aspect, the first pad electrode 171 covers the third opening 152a to contact the connection electrode 160 and forms an electrical connection with the first semiconductor layer 121 through the connection electrode 160. The second pad electrode 172 covers the fourth opening 152b to contact the metal layer 140 and forms an electrical connection with the second semiconductor layer 123 through the metal layer 140 and the transparent conductive layer 130.

[0072] This embodiment also provides a light-emitting diode. The similarities with the first and second embodiments will not be repeated here, but the differences are:

[0073] Figure 11 This is a top view illustrating the hole distribution in the light-emitting diode according to the third embodiment of the present invention.

[0074] like Figure 11 As shown, the aperture of the second hole 120b in the second region Q2 can gradually increase with the distance away from the first region Q1. In this case, the increase rate of the aperture of the second hole 120b in the second region Q2 can be increased linearly, non-linearly, or gradually, but the embodiment is not limited to this.

[0075] This embodiment also provides a light-emitting diode, and the similarities with the above embodiments will not be repeated. The differences are as follows:

[0076] Figure 12 This is a top view illustrating the hole distribution in the light-emitting diode according to the fourth embodiment of the present invention.

[0077] In one embodiment of the present invention, such as Figure 12 As shown, the number of first holes 120a in the first region Q1 is less than the number of second holes 120b in the second region Q2. This is beneficial for "forcing" the current injected into the first pad electrode 171 to flow to the second holes 120b in the second region Q2, thereby mitigating the "current crowding" effect of the semiconductor stack 120 in the first region Q1 and suppressing the decrease in reflectivity of the metal layer 140 due to local overheating of the semiconductor stack 120 in the first region Q1.

[0078] In one embodiment of the present invention, the number of first openings 151a located in the first region Q1 is less than the number of first openings 151a located in the second region Q2.

[0079] This embodiment also provides a light-emitting diode, and the similarities with the above embodiments will not be repeated. The differences are as follows:

[0080] Figure 13 This is a top view illustrating the hole distribution in the light-emitting diode according to the fifth embodiment of the present invention.

[0081] In one embodiment of the present invention, such as Figure 13 As shown, the spacing between the second holes 120b in the second region Q2 can gradually decrease with increasing distance from the first region Q1. In this case, the rate of decrease in the spacing between the second holes 120b in the second region Q2 can be decreased linearly, non-linearly, or gradually, but the embodiment is not limited to this.

Claims

1. A flip-chip light-emitting diode, comprising: A semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The semiconductor stack includes a first region and a second region that does not overlap with the first region. The semiconductor stack includes a portion of the surface of the second semiconductor layer and a portion of the surface of the first semiconductor layer exposed. The first region includes a portion of the surface of the second semiconductor layer and a portion of the surface of the first semiconductor layer exposed. The second region includes a portion of the surface of the second semiconductor layer and a portion of the surface of the first semiconductor layer exposed. Connecting electrodes are formed on the semiconductor stack and are in surface contact with the first semiconductor layer portion via the first region and the second region; A first pad electrode is formed on the first region of the semiconductor stack, and the first pad electrode is electrically connected to the first semiconductor layer through the connection electrode. The second pad electrode is formed on the second region of the semiconductor stack and is electrically connected to the second semiconductor layer; Wherein, the area of ​​the connection electrode in contact with the first semiconductor layer of the first region is smaller than the area of ​​the connection electrode in contact with the first semiconductor layer of the second region.

2. The flip-chip light-emitting diode according to claim 1, characterized in that, It also includes a first insulating layer located between the semiconductor stack and the connection electrode. The first insulating layer includes a first opening to expose a portion of the surface of the first semiconductor layer. The connection electrode is electrically insulated from the second semiconductor layer through the first insulating layer and electrically connected to the first semiconductor layer through the first opening.

3. The flip-chip light-emitting diode according to claim 2, characterized in that, It also includes a metal layer located between the semiconductor stack and the first insulating layer, the metal layer having a reflectivity greater than 60%.

4. The flip-chip light-emitting diode according to claim 2, characterized in that, The area of ​​the first opening located in the first region is smaller than the area of ​​the first opening located in the second region.

5. The flip-chip light-emitting diode according to claim 2, characterized in that, The width of the first opening located in the first region is smaller than the width of the first opening located in the second region.

6. The flip-chip light-emitting diode according to claim 1, characterized in that, The semiconductor stack includes a plurality of holes that pass through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to expose a portion of the surface of the first semiconductor layer.

7. The flip-chip light-emitting diode according to claim 6, characterized in that, In a plan view, a virtual line is drawn parallel to the edge of the flip-chip LED. The virtual line is located at the center line of the flip-chip LED and between the first pad and the second pad. There are no holes on the virtual line.

8. A flip-chip light-emitting diode, comprising: A semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially, wherein the semiconductor stack includes a first region and a second region that does not overlap with the first region; Multiple holes, including multiple first holes and multiple second holes, the first holes and the second holes passing through the second semiconductor layer, the active layer and a portion of the first semiconductor layer to expose a portion of the surface of the first semiconductor layer, the first holes being located in the first region and the second holes being located in the second region; Connecting electrodes are formed on the semiconductor stack and are in surface contact with the first semiconductor layer portion via the first region and the second region; A first pad electrode is formed on the first region of the semiconductor stack, and the first pad electrode is electrically connected to the first semiconductor layer through the connection electrode. The second pad electrode is formed on the second region of the semiconductor stack and is electrically connected to the second semiconductor layer; The width of the first hole is smaller than the width of the second hole.

9. The flip-chip light-emitting diode according to claim 8, characterized in that, The area of ​​the connection electrode in contact with the first semiconductor layer in the first region is smaller than the area of ​​the connection electrode in contact with the first semiconductor layer in the second region.

10. The flip-chip light-emitting diode according to claim 8, characterized in that, The spacing between the second holes decreases as they move away from the first region.

11. The flip-chip light-emitting diode according to claim 8, characterized in that, The number of the first holes is less than the number of the second holes.

12. The flip-chip light-emitting diode according to claim 8, characterized in that, It also includes a first insulating layer located between the semiconductor stack and the connection electrode. The first insulating layer includes a first opening to expose a portion of the surface of the first semiconductor layer. The connection electrode is electrically insulated from the second semiconductor layer through the first insulating layer and electrically connected to the first semiconductor layer through the first opening.

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