A pulse width modulation generation method, apparatus and electronic device

Abstract

The application discloses a pulse width modulation generation method and device and electronic equipment. The method comprises the following steps: at the starting moment of a pulse modulation period, a first pulse waveform port outputs a first level signal; at a first preset moment, an enable gate signal is enabled, a digital-to-analog conversion module is triggered to compare an acquired current value with a reference value, and it is determined whether the acquired current value matches the reference value; if yes, the first pulse waveform port outputs a second level signal; if no, the first pulse waveform port outputs the second level signal after waiting for a preset time; wherein the first level signal and the second level signal are high and low level signals respectively. The technical scheme of the embodiment of the application executes the pre-set control logic by the hardware module in the pulse width modulation generation device, and outputs the pulse waveform. The output of the pulse waveform does not need to be controlled by the CPU by executing additional codes or detecting the state of the input signal, so that the CPU intervention on the pulse width modulation is reduced, and the CPU load rate is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of pulse width modulation technology, and in particular to a pulse width modulation generation method, apparatus, and electronic device. Background Technology

[0002] Pulse Width Modulation (PWM) is a highly effective technique that uses the digital output of a microprocessor to control analog circuits. It has wide applications in power control and conversion, motor control, servo control, dimming, and switching power supplies. With the increasing popularity of intelligent and connected vehicles, the functions of automotive Electronic Control Units (ECUs) are becoming increasingly complex. At the same time, the electronic and electrical architecture surrounding the area controller and central computing unit in vehicles is reducing the number of ECUs. The deployment of more functions inevitably increases the processor load on the ECUs significantly; therefore, how to reduce the processor load is a pressing issue.

[0003] Existing PWM generation strategies typically require the CPU to control the generation of the PWM waveform. The CPU's intervention and frequent interruptions significantly increase the processor's load, reduce ECU performance, and lead to poor ECU real-time performance, overheating, and even ECU malfunction. Summary of the Invention

[0004] This invention provides a pulse width modulation generation method, apparatus, and electronic device to reduce CPU intervention in pulse width modulation and effectively reduce CPU load.

[0005] According to one aspect of the present invention, a pulse width modulation generation method is provided, the method comprising:

[0006] At the beginning of the pulse modulation period, the first pulse waveform port is controlled to output a first level signal;

[0007] At the first preset moment, the enable gate signal is activated, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0008] If so, then control the first pulse waveform port to output the second level signal;

[0009] If not, wait until the preset time, and then control the first pulse waveform port to output the second level signal; wherein the first level signal and the second level signal are high and low level signals respectively.

[0010] Optionally, after controlling the first pulse waveform port to output a second level signal after waiting for a preset time, the method further includes:

[0011] Determine whether the pulse waveform edge generation condition is met. If it is met, control the first pulse waveform port to output a first level signal and repeat the above steps. The pulse waveform edge generation condition includes matching the timer time with the preset pulse waveform edge generation time.

[0012] Optionally, before controlling the first pulse waveform port to output the first level signal at the beginning of the pulse modulation period, the method further includes:

[0013] The enable gate signal is disabled, and the analog-to-digital converter module is controlled to collect the current value.

[0014] Optionally, at the beginning of the pulse modulation period, after controlling the first pulse waveform port to output a first-level signal, and before enabling the gate signal and triggering the analog-to-digital conversion module to compare the acquired current value with the reference value, the method further includes:

[0015] The waveform output from the first pulse waveform port is de-shadowed.

[0016] Optionally, the first level is high and the second level is low; the control output second level signal includes:

[0017] If the acquired current value matches the reference value, a matching signal is output.

[0018] Upon receiving the matching signal, an output shutdown event is generated to control the first pulse waveform port to output a second level signal.

[0019] Optionally, after waiting for a preset time, the first pulse waveform port is controlled to output a second level signal, including:

[0020] If the collected current value does not match the reference value, determine whether the preset time has been reached;

[0021] If not, continue comparing the collected current value with the reference value;

[0022] If so, then force the first pulse waveform port to output the second level signal.

[0023] Optionally, after waiting for a preset time to control the pulse waveform to output a second-level signal, the method further includes:

[0024] The enable gate signal is invalidated to suspend the analog-to-digital converter module from performing current comparison.

[0025] Optionally, the method further includes:

[0026] At the beginning of the pulse modulation period, the second pulse waveform port is controlled to output a second level signal;

[0027] At the first preset moment, the enable gate signal is activated, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0028] If so, then control the second pulse waveform port to output the first level signal;

[0029] If not, wait until the preset time to control the second pulse waveform port to output the first level signal;

[0030] The second pulse waveform port has a dead time before the first pulse waveform port outputs the first level signal and after the first pulse waveform port outputs the second level signal.

[0031] According to another aspect of the present invention, a pulse width modulation (PWM) generation apparatus is provided, characterized in that the PWM generation apparatus is used to implement the PWM generation method as described in the first aspect of the present invention, the PWM generation apparatus comprising:

[0032] The timer module is used for timing. The timer module also includes a waveform output module and a signal capture module.

[0033] The waveform output module is used to output level signals and perform timing.

[0034] The analog-to-digital conversion module is used to acquire current values ​​and compare them with reference values ​​to determine whether the acquired current values ​​match the reference values.

[0035] The signal acquisition module is used to receive the matching signal and send it to the dead zone generation module;

[0036] The dead-time generation module is used to generate output shutdown events based on the matching signal and to generate the dead-time.

[0037] According to another aspect of the present invention, an electronic device is provided, characterized in that it includes a pulse width modulation generation device as described in the second aspect of the present invention.

[0038] The technical solution of this invention pre-sets the times when the pulse waveform needs to be controlled according to the pulse modulation requirements, including the start time of the pulse modulation period, a first preset time, and a preset time, and stores the pre-set control logic in the pulse width modulation generation device. At the start time of the pulse modulation period, the first pulse waveform port outputs a first level signal. At the first preset time, the gate signal is enabled. The gate signal triggers the analog-to-digital conversion module to compare the acquired current value with a reference value, determining whether the acquired current value matches the reference value. Based on the determination result, the level signal output by the first pulse waveform port is controlled. The hardware module in the pulse width modulation generation device executes the pre-set control logic to output the pulse waveform. This eliminates the need for the CPU to execute additional code or detect the state of the input signal to control the output of the pulse waveform, thus reducing CPU intervention in pulse width modulation and effectively lowering the CPU load.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of a pulse width modulation generation method provided in an embodiment of the present invention;

[0042] Figure 2 This is a flowchart of another pulse width modulation generation method provided in an embodiment of the present invention;

[0043] Figure 3 This is a flowchart of another pulse width modulation generation method provided in the embodiments of the present invention;

[0044] Figure 4 This is a flowchart of another pulse width modulation generation method provided in the embodiments of the present invention;

[0045] Figure 5 This is a waveform diagram generated by pulse width modulation according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a pulse width modulation generation device provided in an embodiment of the present invention;

[0047] Figure 7This is a schematic diagram of the structure of an electronic device that implements the pulse width modulation generation method of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] This invention provides a pulse width modulation (PWM) generation method, which can be executed by a PWM generation device and is suitable for controlling analog circuits. The PWM generation device can be implemented in hardware and / or software and can be integrated into a processor. Figure 1 This is a flowchart of a pulse width modulation generation method provided in an embodiment of the present invention. See also... Figure 1 The method includes:

[0051] S101. At the beginning of the pulse modulation period, control the first pulse waveform port to output a first level signal.

[0052] Specifically, the start time of the pulse modulation period can be set according to the pulse modulation requirements. The first pulse waveform port can be any channel of any logarithmic complementary waveform output by the pulse width modulation generator, used to control the MOSFET in the analog circuit to turn on or off. The first level signal can be a high-level signal or a low-level signal. For example, if the first level signal is a high-level signal, then at the start time of the pulse modulation period, the pulse width modulation generator controls the first pulse waveform port to output the first level signal, used to control the MOSFET corresponding to the first pulse waveform port in the analog circuit to turn on; wherein, there can be multiple MOSFETs corresponding to the first pulse waveform port.

[0053] S102. At the first preset time, the enable gate signal is valid, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0054] Specifically, the first preset time can be set according to the pulse modulation requirements. Only after reaching the first preset time is the analog-to-digital converter (ADC) allowed to compare the acquired current value with the reference value, thus eliminating the influence of current or voltage jitter on pulse modulation. The first preset time is later than the start time of the pulse modulation cycle; in other words, within one pulse modulation cycle, the first preset time is after the start time of the pulse modulation cycle. The pulse width modulation (PWM) generation device includes multiple waveform output modules, which simultaneously generate multiple pulse waveforms. The pulse waveforms used to control the analog circuit are output from various pulse waveform ports, and the gating signal can be provided by pulse waveforms not used to control the analog circuit. The reference value is set after actual testing according to different control requirements. For example, control requirements may include controlling the forward and reverse drive and braking of a motor, controlling the on and off of a switching power supply, etc. At the first preset time, the PWM generation device enables the gating signal. Upon receiving the valid gating signal, the ADC is triggered and compares the real-time acquired current value from the analog circuit with the reference value to determine whether the acquired current value matches the reference value.

[0055] S103. If so, control the first pulse waveform port to output the second level signal.

[0056] Specifically, if the acquired current value matches the reference value, the first pulse waveform port is immediately controlled to output a second level signal; the second level signal can be a high level signal or a low level signal.

[0057] S104. If not, wait until the preset time and then control the first pulse waveform port to output the second level signal; wherein the first level signal and the second level signal are high and low level signals respectively.

[0058] Specifically, the preset time can be set as needed and is used as a protective measure to prevent the MOSFET in the analog circuit from overheating and burning out due to prolonged current flow. If the sampled current value does not match the reference value, the system waits until the preset time to control the first pulse waveform port to output a second level signal. The first and second level signals are high and low level signals respectively; that is, when the first level signal is high, the second level signal is low.

[0059] The technical solution of this embodiment pre-sets the times when the pulse waveform needs to be controlled according to the pulse modulation requirements, including the start time of the pulse modulation period, the first preset time, and the preset time, and stores the pre-set control logic in the pulse width modulation generation device. At the start time of the pulse modulation period, the first pulse waveform port is controlled to output a first level signal. At the first preset time, the gate signal is enabled. The gate signal triggers the analog-to-digital conversion module to compare the sampled current value with the reference value, and determines whether the sampled current value matches the reference value. Based on the determination result, the level signal output by the first pulse waveform port is controlled. The hardware module in the pulse width modulation generation device executes the pre-set control logic to output the pulse waveform. It does not require the CPU to execute additional code or detect the state of the input signal to control the output of the pulse waveform, thereby reducing the CPU's intervention in pulse width modulation and effectively reducing the CPU load rate.

[0060] Figure 2 This is a flowchart of another pulse width modulation generation method provided in an embodiment of the present invention. Optionally, see [link to flowchart]. Figure 2 The method includes:

[0061] S201. At the beginning of the pulse modulation period, control the first pulse waveform port to output a first level signal.

[0062] S202. At the first preset time, the enable gate signal is valid, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0063] S203. If so, control the first pulse waveform port to output the second level signal.

[0064] S204. If not, wait until the preset time and then control the first pulse waveform port to output the second level signal; wherein the first level signal and the second level signal are high and low level signals respectively.

[0065] S205. Determine whether the pulse waveform edge generation condition is met. If it is met, control the first pulse waveform port to output a first level signal and repeat the above steps. The pulse waveform edge generation condition includes matching the timer time with the preset pulse waveform edge generation time.

[0066] Specifically, the preset pulse waveform edge generation time can be set according to the pulse modulation requirements. The preset pulse waveform edge generation time is the start time of the second cycle of the pulse waveform. The pulse width modulation generation device includes a timer module, and the timer time is obtained by the timer module. It is determined whether the timer time has reached the preset pulse waveform edge generation time. If so, it indicates that the start time of the second pulse modulation cycle has been reached. The first pulse waveform port is controlled to output a first level signal, and the above steps are repeated to control the subsequent pulse modulation cycles.

[0067] The technical solution of this embodiment pre-sets the times when the pulse waveform needs to be controlled according to the pulse modulation requirements, including the start time of the pulse modulation period, the first preset time, and the preset time, and stores the pre-set control logic in the pulse width modulation generation device. At the start time of the pulse modulation period, the first pulse waveform port is controlled to output a first-level signal. At the first preset time, the gate signal is enabled. The gate signal triggers the analog-to-digital conversion module to compare the acquired current value with a reference value, determining whether the acquired current value matches the reference value. Based on the determination result, the level signal output by the first pulse waveform port is controlled. After the pulse waveform edge generation condition is met, the first pulse waveform port is controlled to output a first-level signal, and the above steps are repeated, thereby obtaining the desired pulse waveform. The hardware module in the pulse width modulation generation device executes the pre-set control logic to output the pulse waveform, eliminating the need for the CPU to execute additional code or detect the state of the input signal to control the output of the pulse waveform. This reduces CPU intervention in pulse width modulation and effectively lowers the CPU load.

[0068] Figure 3 This is a flowchart of another pulse width modulation generation method provided by an embodiment of the present invention. Optionally, when the first level is high and the second level is low, see [link to relevant documentation]. Figure 3 The method includes:

[0069] S301 enables the gate signal to be invalid, and simultaneously controls the analog-to-digital converter module to acquire the current value.

[0070] Specifically, the enable gate signal is invalidated, while simultaneously controlling the analog-to-digital converter (ADC) to acquire the current value. When the gate signal is invalid, the ADC outputs a default value, which is a manually set invalid value. This invalid value cannot be compared with the reference value, preventing the sampled current from matching the reference value when the current is unstable, thus avoiding inaccurate pulse waveform modulation.

[0071] S302. At the beginning of the pulse modulation period, control the first pulse waveform port to output a first level signal.

[0072] S303, Perform shadow removal on the waveform output from the first pulse waveform port.

[0073] Specifically, the turn-off and release of the pulse waveform are closely related to the loop current. When the level signal of the pulse waveform switches, that is, when the MOSFET is turned on or off, the gate and drain of the MOSFET may oscillate, causing loop current or voltage fluctuations. The purpose of shadow cancellation is to shield interference. That is, during the shadow cancellation time, due to the fluctuation of the loop current or voltage of the analog circuit, the current value collected by the analog-to-digital conversion module is unstable and cannot be used as the sampled current value for comparison with the reference value. Shadow cancellation is performed on the waveform output from the first pulse waveform port, that is, between the start of the pulse modulation period and the first preset time, the collected current value is not compared with the reference value to avoid the influence of loop current or voltage fluctuations on the modulation of the pulse waveform.

[0074] S304. At the first preset time, the enable gate signal is valid, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0075] S305. If the acquired current value matches the reference value, then output a matching signal.

[0076] Specifically, if the acquired current value matches the reference value, the analog-to-digital converter module outputs a matching signal.

[0077] S306. After receiving the matching signal, an output shutdown event is generated to control the first pulse waveform port to output a second level signal.

[0078] Specifically, the pulse width modulation generation device also includes a signal acquisition module and a dead-time generation module. The signal acquisition module is used to capture and transmit the matching signal, and the dead-time generation module is used to generate an output shutdown event. The signal acquisition module captures the matching signal output by the analog-to-digital conversion module and transmits it to the dead-time generation module. After receiving the matching signal, the dead-time generation module generates an output shutdown event to control the first pulse waveform port to output a second-level signal, i.e., a low-level signal.

[0079] S307. If the collected current value does not match the reference value, determine whether the preset time has been reached.

[0080] Specifically, if the sampled current value does not match the reference value, it is determined whether a preset time has been reached. This can be determined based on the timer duration, which can be obtained from the timer module.

[0081] S308. If not, continue to compare the collected current value with the reference value.

[0082] Specifically, if the preset time has not been reached, the current value collected will continue to be compared with the reference value, and it will be determined whether the current value collected matches the reference value.

[0083] S309. If so, then force the first pulse waveform port to output the second level signal.

[0084] Specifically, if the preset time is reached, the first pulse waveform port is forced to output a second level signal, i.e., a low level. This indicates that the MOSFET in the analog circuit is turned off, preventing the MOSFET from overheating and burning out due to prolonged current flow.

[0085] S310, enable gate signal invalid, to suspend analog-to-digital conversion module for current comparison.

[0086] Specifically, after the first pulse waveform port outputs a second-level signal, it indicates that it is no longer necessary to compare the sampled current value with the reference value. At this time, the enable gate signal is invalid, so as to suspend the analog-to-digital conversion module from performing current comparison.

[0087] The technical solution of this embodiment pre-sets the time when the pulse waveform needs to be controlled according to the pulse modulation requirements, including the start time of the pulse modulation period, the first preset time, the preset time, etc., and pre-sets the control logic and stores it in the pulse width modulation generation device. The hardware module in the pulse width modulation generation device executes the pre-set control logic and outputs the pulse waveform. It does not require the CPU to execute additional code or detect the state of the input signal to control the output of the pulse waveform, thereby reducing the CPU's intervention in pulse width modulation and effectively reducing the CPU load rate.

[0088] Figure 4 This is a flowchart of another pulse width modulation generation method provided in an embodiment of the present invention. Optionally, see [link to flowchart]. Figure 4 The method includes:

[0089] S401. At the beginning of the pulse modulation period, control the second pulse waveform port to output a second level signal.

[0090] Specifically, the second pulse waveform port can be any channel from any logarithmic complementary waveform output by the pulse width modulation generator, used to control the MOSFET in the analog circuit to turn on or off, and the waveforms output by the second pulse waveform port and the first pulse waveform port are a pair of complementary waveforms. The second level signal can be a high level signal or a low level signal, and the second level signal and the first level signal are high and low level signals respectively. For example, if the first level signal is a high level signal, then the second level signal is a low level signal. At the beginning of the pulse modulation period, the pulse width modulation generator controls the second pulse waveform port to output a second level signal, used to control the MOSFET corresponding to the second pulse waveform port in the analog circuit to turn off; wherein, there can be multiple MOSFETs corresponding to the second pulse waveform port.

[0091] S402. At the first preset time, the enable gate signal is valid, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value.

[0092] S403 If so, then control the second pulse waveform port to output the first level signal.

[0093] Specifically, if the acquired current value matches the reference value, the second pulse waveform port outputs a first-level signal after a dead time. This first-level signal can be either high or low. Dead times are set before the first pulse waveform port outputs the first-level signal and after it outputs the second-level signal. The dead time is a protection period set to prevent the MOSFETs corresponding to the two complementary pulse waveforms from simultaneously conducting and causing breakdown, thus leading to a short circuit. Therefore, during the dead time, both the upper and lower complementary pulse waveforms output a low level, meaning the MOSFETs are both off.

[0094] S404. If not, wait until the preset time to control the second pulse waveform port to output the first level signal.

[0095] Figure 5 This is a waveform diagram generated by pulse width modulation according to an embodiment of the present invention. See also... Figure 5 The pulse width modulation (PWM) generation device can output any number of complementary waveforms according to PWM requirements. When the first pulse waveform port is CH1 and the second pulse waveform port is CH2, the waveform output from the first pulse waveform port and the second pulse waveform port are a pair of complementary waveforms. CH3 and CH4, as shown in the attached figure, are another pair of complementary waveforms that lag behind the first and second pulse waveform ports by half a cycle.

[0096] For example, the embodiments of the present invention are based on Infineon TC3 series microcontrollers for pulse width modulation, and Infineon's second-generation AURIX... TM The (TC3 series) microcontroller is the world's first embedded safety controller to achieve the highest Automotive Safety Integrity Level (ASIL D) certification according to the latest version of the ISO 26262 standard, placing it at the forefront of the automotive safety field. At time t1, as shown in the attached diagram, the start of the pulse modulation period, the first pulse waveform port CH1 outputs a first-level signal. Between the start of the pulse modulation period t1 and the first preset time t2, the waveform output from the first pulse waveform port CH1 is suppressed, and the sampled current value is not compared with the reference value, avoiding the influence of loop current or voltage fluctuations on the pulse waveform modulation. At time t2, as shown in the attached diagram, the first preset time, the enable gate signal is activated, triggering the analog-to-digital converter (ADC) to compare the sampled current value with the reference value and determine if they match. At time t3, as shown in the attached diagram, if the sampled current value matches the reference value, the ADC outputs a matching signal. Upon receiving the matching signal, the dead-time generation module generates an output shutdown event and immediately controls the first pulse waveform port CH1 to output a second-level signal. If the acquired current value does not match the reference value, the first pulse waveform port CH1 continues to output a first-level signal. At time t4 (the preset time), if the acquired current value still does not match the reference value after waiting for the preset time t4, the first pulse waveform port is controlled to output a second-level signal. At time t5 (the preset time), it is determined whether the pulse waveform edge generation condition is met. If it is met, the first pulse waveform port CH1 is controlled to output a first-level signal, and the above steps are repeated to control the subsequent pulse modulation period.

[0097] This invention also provides a pulse width modulation (PWM) generation apparatus, which is used to implement the PWM generation method described in any of the above embodiments; Figure 6 This is a schematic diagram of a pulse width modulation generation device provided in an embodiment of the present invention. See also... Figure 6 The device includes:

[0098] Timer module 1 is used for timing. The timer module also includes a waveform output module and a signal capture module.

[0099] Waveform output module 2 is used to output level signals and perform timing.

[0100] The analog-to-digital conversion module 3 is used to acquire the current value and compare the acquired current value with the reference value to determine whether the acquired current value matches the reference value.

[0101] Signal acquisition module 4 is used to receive the matching signal and send it to the dead zone generation module;

[0102] Dead-time generation module 5 is used to generate output shutdown events based on the matching signal and to generate dead-time.

[0103] Specifically, timer module 1 is used for timing to determine whether the pulse waveform edge generation condition is met based on the timer duration. Waveform output module 2 is used to output level signals. Multiple waveform output modules 2 within the pulse width modulation generation device can control multiple pulse waveform ports to output different level signals, as well as output pulse waveforms for timing or providing gating signals. Analog-to-digital converter module 3 continuously acquires current values ​​and compares the acquired current value with a reference value when the gating signal is valid, determining whether the acquired current value matches the reference value. When the acquired current value matches the reference value, analog-to-digital converter module 3 also outputs a matching signal. Signal acquisition module 4 receives the matching signal output by analog-to-digital converter module 3 and sends the matching signal to dead-time generation module 5. Dead-time generation module 5 generates an output shutdown event based on the matching signal to control the first pulse waveform port to output a second level signal. Dead-time generation module 5 also generates dead time to prevent the switches corresponding to the first and second pulse waveform ports from being simultaneously turned on, thereby protecting the components.

[0104] The technical solution of this embodiment modulates and outputs the pulse waveform through various hardware modules in the pulse width modulation generation device. By controlling the pulse waveform used for timing or providing gating signals, the response of the output pulse waveform is obtained. It does not require the CPU to execute additional code or detect the state of the input signal to control the output of the pulse waveform, thereby reducing the CPU's intervention in pulse width modulation and effectively reducing the CPU load rate.

[0105] Figure 7 This is a schematic diagram of the structure of an electronic device that implements the pulse width modulation generation method of the present invention, as shown in the figure. Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0106] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as pulse width modulation generation methods.

[0108] In some embodiments, the pulse width modulation generation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the pulse width modulation generation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the pulse width modulation generation method by any other suitable means (e.g., by means of firmware).

[0109] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0112] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0113] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0114] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0115] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pulse width modulation generation method, characterized in that, The method includes: At the beginning of the pulse modulation period, the first pulse waveform port is controlled to output a first level signal; At a first preset time, the enable gate signal is activated, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value. If so, then control the first pulse waveform port to output a second level signal; If not, wait until the preset time, and then control the first pulse waveform port to output the second level signal; wherein the first level signal and the second level signal are high and low level signals respectively; The step of controlling the first pulse waveform port to output a second level signal when waiting for a preset time includes: If the acquired current value does not match the reference value, then determine whether the preset time has been reached; If not, continue comparing the acquired current value with the reference value; If so, then force the first pulse waveform port to output a second level signal.

2. The method according to claim 1, characterized in that, After controlling the first pulse waveform port to output a second level signal after waiting for a preset time, the method further includes: Determine whether the pulse waveform edge generation condition is met. If it is met, control the first pulse waveform port to output a first level signal and repeat the above steps. The pulse waveform edge generation condition includes matching the timer time with the preset pulse waveform edge generation time.

3. The method according to claim 1, characterized in that, Before controlling the first pulse waveform port to output a first level signal at the beginning of the pulse modulation period, the method further includes: The gate signal is disabled, and the analog-to-digital converter is controlled to collect the current value.

4. The method according to claim 1, characterized in that, At the beginning of the pulse modulation period, after controlling the first pulse waveform port to output a first level signal, and before enabling the gate signal and triggering the analog-to-digital conversion module to compare the acquired current value with the reference value, the method further includes: The waveform output from the first pulse waveform port is de-shadowed.

5. The method according to claim 1, characterized in that, The first level is high, and the second level is low; the control output second level signal includes: If the acquired current value matches the reference value, a matching signal is output; Upon receiving the matching signal, an output shutdown event is generated to control the first pulse waveform port to output a second level signal.

6. The method according to claim 1, characterized in that, After controlling the pulse waveform to output a second-level signal when the preset time has elapsed, the method further includes: The gate signal is disabled to suspend the analog-to-digital conversion module from performing current comparison.

7. The method according to claim 1, characterized in that, The method further includes: At the beginning of the pulse modulation period, the second pulse waveform port is controlled to output a second level signal; At the first preset time, the enable gate signal is activated, triggering the analog-to-digital conversion module to compare the acquired current value with the reference value and determine whether the acquired current value matches the reference value; If so, then control the second pulse waveform port to output a first level signal; If not, wait until the preset time, and then control the second pulse waveform port to output the first level signal; The second pulse waveform port has a dead time before the first pulse waveform port outputs the first level signal and after the first pulse waveform port outputs the second level signal.

8. A pulse width modulation generation device, characterized in that, The pulse width modulation generation apparatus is used to implement the pulse width modulation generation method according to any one of claims 1-7, and the pulse width modulation generation apparatus comprises: The timer module is used for timing. The timer module also includes a waveform output module and a signal capture module. The waveform output module is used to output level signals and perform timing. The analog-to-digital conversion module is used to acquire current values, compare the acquired current values ​​with reference values, and determine whether the acquired current values ​​match the reference values. The signal acquisition module is used to receive the matching signal and send it to the dead zone generation module; The dead-time generation module is used to generate an output shutdown event and generate a dead-time based on the matching signal.

9. An electronic device, characterized in that, Includes the pulse width modulation generation apparatus as described in claim 8.

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