A comparator circuit
By introducing a series diode and a current mirror circuit between the differential transistors of the differential pair, the problem of uneven degradation of differential transistors is solved, and the service life of the comparator circuit is extended.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOTORCOMM (SHANGHAI) ELECTRONIC TECH CO LTD
- Filing Date
- 2023-01-09
- Publication Date
- 2026-06-05
AI Technical Summary
In existing comparator circuits, the two differential transistors of the differential pair degrade unevenly under low-temperature operation, resulting in a shortened circuit lifespan.
By introducing a series diode between the two differential transistors of a differential pair, and combining it with a current mirror circuit and a voltage balancing circuit, voltage balancing and degradation suppression of the transistors can be achieved by adjusting the circuit bias voltage and control signal.
It slows down the degradation of transistors, mitigates uneven degradation, and improves the lifespan of comparator circuits.
Smart Images
Figure CN116054790B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of comparator technology, and more particularly to a comparator circuit. Background Technology
[0002] like Figure 1 The diagram shown is a circuit diagram of an existing comparator circuit, as follows: Figure 2 As shown Figure 1 The diagram shows the degradation of the circuit during the High / Low Temperature Operating Life (HTOL) test. Figure 2 The curves from right to left are before degradation, and after 1 year and 10 years, respectively. During the accelerated aging test of the comparator circuit device, it was found that the degree of degradation was inconsistent after 1 year and 10 years. The main reason for the curve change is that the two differential transistors of the differential pair in the comparator circuit are severely degraded and the degradation is uneven, which reduces the service life of the comparator circuit. Summary of the Invention
[0003] To address the above technical problems, the present invention provides a comparator circuit.
[0004] The technical problem solved by this invention can be achieved by the following technical solutions:
[0005] A comparator circuit includes:
[0006] A differential pair includes a first differential transistor for receiving a first input signal and a second differential transistor for receiving a second input signal;
[0007] A voltage balancing circuit is used to balance the voltage outputs of two differential transistors.
[0008] An output stage control circuit is connected to the drain of the second differential transistor, and can controllably output an output signal to the comparator output terminal under the action of the drain voltage of the second differential transistor.
[0009] It also includes: a first diode connected between the first differential transistor and the voltage balancing circuit;
[0010] A second diode is connected between the second differential transistor and the voltage balancing circuit.
[0011] Preferably, it further includes: a current mirror circuit, the current mirror circuit comprising: a first mirror transistor, a second mirror transistor, and a third mirror transistor connected in parallel between their gate and source;
[0012] The gate and drain of the first mirror transistor are connected, and the drain of the first mirror transistor is controllably connected to the ground terminal through an enable control circuit. The second mirror transistor is connected to the differential pair, and the third mirror transistor is connected to the output stage control circuit.
[0013] Preferably, the enable control circuit includes a first resistor, a second resistor, and a first enable transistor;
[0014] One end of the second resistor is connected to the drain of the first mirror transistor through the first resistor, and the other end of the second resistor is connected to the drain of the first enable transistor. The gate of the first enable transistor is connected to an enable signal, and the source of the first enable transistor is connected to the ground terminal.
[0015] Preferably, the voltage balancing circuit includes: a third transistor, a fourth transistor, a second enable transistor, a first filter transistor, and a third resistor;
[0016] The gate of the third transistor is connected to the gates of the first diode and the fourth transistor, respectively. The drain of the third transistor is connected to the first diode through the third resistor, and the source of the third transistor is connected to ground. The drain of the fourth transistor is connected to the second diode, and the source of the fourth transistor is connected to ground. The gate of the second enable transistor is connected to an enable signal, and the drain of the second enable transistor is connected to the drain of the third transistor. The source of the second enable transistor is connected to ground. The gate of the first filter transistor is connected to the gate of the third transistor, and the source and drain of the first filter transistor are connected to ground.
[0017] Preferably, the third transistor and the fourth transistor employ a power dissipation process.
[0018] Preferably, the output stage control circuit includes: a fifth transistor, a third enable transistor, a fourth enable transistor, and a second filter transistor;
[0019] The gate of the fifth transistor is connected to the drain of the second differential transistor, the drain of the fifth transistor is connected to the comparator output, and the source of the fifth transistor is connected to ground. The gate of the third enable transistor is connected to an enable signal, the drain of the third enable transistor is connected to the gate of the fifth transistor, and the source of the third enable transistor is connected to ground. The gate of the fourth enable transistor is connected to the enable signal, the drain of the fourth enable transistor is connected to the comparator output, and the source of the third enable transistor is connected to ground. The gate of the second filter transistor is connected to the gate of the fifth transistor, and the source and drain of the second filter transistor are connected to ground.
[0020] Preferably, it further includes:
[0021] The third filter transistor has its gate connected to the gate of the first mirror transistor, and its source and drain are connected to the power supply terminal.
[0022] The fifth enabling transistor has its gate connected to an enabling signal, and its source and drain are connected in parallel with the first mirror transistor.
[0023] Preferably, it further includes:
[0024] The fourth filter transistor has its gate, source, and drain connected together and coupled to the source of two differential transistors.
[0025] Preferably, it further includes:
[0026] A common-source gate transistor, wherein the gate of the common-source gate transistor is connected to the drain of the first enable transistor, the source of the common-source gate transistor is connected to the drain of the third mirror transistor, and the drain of the common-source gate transistor is connected to the output of the comparator.
[0027] Preferably, it further includes:
[0028] A fifth filter transistor, the source and drain of which are connected in parallel with the first mirror transistor, and the fifth filter transistor is connected to the drain of the first mirror transistor.
[0029] The advantages or beneficial effects of the technical solution of this invention are as follows:
[0030] This invention reduces the voltage drop of two differential transistors connected in series with diodes in a differential pair, thereby slowing down the degradation process and suppressing uneven degradation. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of a comparator circuit in the prior art;
[0032] Figure 2 This is a schematic diagram of the degradation of a comparator circuit in the prior art before aging, after 1 year, and after 10 years.
[0033] Figure 3 This is a schematic diagram of a comparator circuit in a preferred embodiment of the present invention;
[0034] Figure 4 This is a preferred embodiment of the present invention, showing the degradation of the comparator circuit before aging, after 1 year, and after 10 years. Detailed Implementation
[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0036] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0038] See Figure 3-4 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a comparator circuit is provided, comprising:
[0039] A differential pair includes a first differential transistor M1 for receiving a first input signal and a second differential transistor M2 for receiving a second input signal;
[0040] A voltage balancing circuit is used to balance the voltage outputs of two differential transistors.
[0041] An output stage control circuit is connected to the drain of the second differential transistor M2. Under the action of the drain voltage of the second differential transistor M2, an output signal can be controlled to be output to the comparator output terminal vout.
[0042] It also includes: a first diode M91, connected between the first differential transistor M1 and the voltage balancing circuit;
[0043] A second diode M92 is connected between the second differential transistor M2 and the voltage balancing circuit. Furthermore, the first diode M91 and the second diode M92 can be implemented using transistors, that is, by connecting the gate and drain of the transistors to achieve diode function;
[0044] In a preferred embodiment, it further includes: a current mirror circuit, which includes: a first mirror transistor M61, a second mirror transistor M62, and a third mirror transistor M63 connected in parallel with their gates and sources;
[0045] The gate and drain of the first mirror transistor M61 are connected, and the drain of the first mirror transistor M61 is controllably connected to the ground terminal through an enable control circuit. The second mirror transistor M62 is connected to the differential pair, and the third mirror transistor M63 is connected to the output stage control circuit.
[0046] In a preferred embodiment, the enable control circuit includes a first resistor R1, a second resistor R2, and a first enable transistor M71.
[0047] One end of the second resistor R2 is connected to the drain of the first mirror transistor M61 through the first resistor R1. Specifically, the circuit bias voltage is adjusted by the second resistor R2. Later, the second resistor R2 is equivalent to being short-circuited and has no effect. The other end of the second resistor R2 is connected to the drain of the first enable transistor M71. The gate of the first enable transistor M71 is connected to an enable signal, and the source of the first enable transistor M71 is connected to the ground terminal.
[0048] In a preferred embodiment, the voltage balancing circuit includes: a third transistor M3, a fourth transistor M4, a second enable transistor M72, a first filter transistor M81, and a third resistor R3, which balances the voltage drops of transistors M0 and M1 through R3.
[0049] The gate of the third transistor M3 is connected to the gates of the first diode and the fourth transistor M4, respectively. The drain of the third transistor M3 is connected to the first diode M91 through the third resistor R3, and the source of the third transistor M3 is connected to the ground terminal. The drain of the fourth transistor M4 is connected to the second diode M92, and the source of the fourth transistor M4 is connected to the ground terminal. The gate of the second enable transistor M72 is connected to an enable signal, the drain of the second enable transistor M72 is connected to the drain of the third transistor M3, and the source of the second enable transistor M72 is connected to the ground terminal. The gate of the first filter transistor M81 is connected to the gate of the third transistor M3, and the source and drain of the first filter transistor M81 are connected to the ground terminal.
[0050] In a preferred embodiment, the third transistor M3 and the fourth transistor M4 are native transistors. Since the threshold voltage of the native transistors is very small, the fifth transistor M5 is easily turned on.
[0051] In a preferred embodiment, the output stage control circuit includes: a fifth transistor M5, a third enable transistor M73, a fourth enable transistor M74, and a second filter transistor M82.
[0052] The gate of the fifth transistor M5 is connected to the drain of the second differential transistor, the drain of the fifth transistor M5 is connected to the comparator output, and the source of the fifth transistor M5 is connected to ground. The gate of the third enable transistor M73 is connected to the enable signal, the drain of the third enable transistor M73 is connected to the gate of the fifth transistor M5, and the source of the third enable transistor M73 is connected to ground. The gate of the fourth enable transistor M74 is connected to the enable signal, the drain of the fourth enable transistor M74 is connected to the comparator output, and the source of the third enable transistor M73 is connected to ground. The gate of the second filter transistor M82 is connected to the gate of the fifth transistor M5, and the source and drain of the second filter transistor M82 are connected to ground.
[0053] In a preferred embodiment, it further includes:
[0054] The third filter transistor M83 has its gate connected to the gate of the first mirror transistor M61, and its source and drain are connected to the power supply.
[0055] The fifth enable transistor M75 has an enable signal connected to its gate, and its source and drain are connected in parallel with the first mirror transistor M61.
[0056] In a preferred embodiment, it further includes:
[0057] The fourth filter transistor M84 has its gate, source, and drain connected together and coupled to the source of the two differential transistors.
[0058] In a preferred embodiment, it further includes:
[0059] The common-source gate transistor M93 has its gate connected to the drain of the first enable transistor M71, and its source connected to the drain of the third mirror transistor M63. The drain of M93 is also connected to the comparator output. M93 uses a cascode configuration to prevent degradation of the third mirror transistor M63 and to adjust its size, increasing the pull-up capability of the P-type transistor.
[0060] In a preferred embodiment, it further includes:
[0061] The fifth filter transistor M85 is a dummy transistor. The source and drain of the fifth filter transistor M85 are connected in parallel with the first mirror transistor M61. The fifth filter transistor M85 is connected to the drain of the first mirror transistor M61.
[0062] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.
Claims
1. A comparator circuit, characterized in that, include: A differential pair includes a first differential transistor for receiving a first input signal and a second differential transistor for receiving a second input signal; A voltage balancing circuit is used to balance the voltage outputs of two differential transistors. An output stage control circuit is connected to the drain of the second differential transistor, and can controllably output an output signal to the comparator output terminal under the action of the drain voltage of the second differential transistor. It also includes: a first diode connected between the first differential transistor and the voltage balancing circuit; A second diode is connected between the second differential transistor and the voltage balancing circuit; The voltage balancing circuit includes: a third transistor, a fourth transistor, a second enable transistor, a first filter transistor, and a third resistor; The gate of the third transistor is connected to the gates of the first diode and the fourth transistor, respectively. The drain of the third transistor is connected to the first diode through the third resistor, and the source of the third transistor is connected to ground. The drain of the fourth transistor is connected to the second diode, and the source of the fourth transistor is connected to ground. The gate of the second enable transistor is connected to an enable signal, the drain of the second enable transistor is connected to the drain of the third transistor, and the source of the second enable transistor is connected to ground. The gate of the first filter transistor is connected to the gate of the third transistor, and the source and drain of the first filter transistor are connected to ground.
2. The comparator circuit according to claim 1, characterized in that, Also includes: A current mirror circuit, comprising: a first mirror transistor, a second mirror transistor, and a third mirror transistor connected in parallel with their gate and source; The gate and drain of the first mirror transistor are connected, and the drain of the first mirror transistor is controllably connected to the ground terminal through an enable control circuit. The second mirror transistor is connected to the differential pair, and the third mirror transistor is connected to the output stage control circuit.
3. The comparator circuit according to claim 2, characterized in that, The enable control circuit includes a first resistor, a second resistor, and a first enable transistor; One end of the second resistor is connected to the drain of the first mirror transistor through the first resistor, and the other end of the second resistor is connected to the drain of the first enable transistor. The gate of the first enable transistor is connected to an enable signal, and the source of the first enable transistor is connected to the ground terminal.
4. The comparator circuit according to claim 1, characterized in that, The third transistor and the fourth transistor employ power consumption, although.
5. The comparator circuit according to claim 1, characterized in that, The output stage control circuit includes: a fifth transistor, a third enable transistor, a fourth enable transistor, and a second filter transistor; The gate of the fifth transistor is connected to the drain of the second differential transistor, the drain of the fifth transistor is connected to the comparator output, and the source of the fifth transistor is connected to ground. The gate of the third enable transistor is connected to an enable signal, the drain of the third enable transistor is connected to the gate of the fifth transistor, and the source of the third enable transistor is connected to ground. The gate of the fourth enable transistor is connected to the enable signal, the drain of the fourth enable transistor is connected to the comparator output, and the source of the third enable transistor is connected to ground. The gate of the second filter transistor is connected to the gate of the fifth transistor, and the source and drain of the second filter transistor are connected to ground.
6. The comparator circuit according to claim 2, characterized in that, Also includes: The third filter transistor has its gate connected to the gate of the first mirror transistor, and its source and drain are connected to the power supply terminal. The fifth enabling transistor has its gate connected to an enabling signal, and its source and drain are connected in parallel with the first mirror transistor.
7. The comparator circuit according to claim 1, characterized in that, Also includes: The fourth filter transistor has its gate, source, and drain connected together and coupled to the source of two differential transistors.
8. The comparator circuit according to claim 3, characterized in that, Also includes: A common-source gate transistor, wherein the gate of the common-source gate transistor is connected to the drain of the first enable transistor, the source of the common-source gate transistor is connected to the drain of the third mirror transistor, and the drain of the common-source gate transistor is connected to the output of the comparator.
9. The comparator circuit according to claim 2, characterized in that, Also includes: A fifth filter transistor, the source and drain of which are connected in parallel with the first mirror transistor, and the fifth filter transistor is connected to the drain of the first mirror transistor.