High speed parallel to serial conversion circuit

Abstract

The application provides a high-speed parallel-serial conversion circuit, which comprises a clock frequency division module, a low-speed CMOS parallel-serial conversion module and a high-speed bipolar parallel-serial conversion module. The low-speed CMOS parallel-serial conversion module comprises CMOS parallel-serial conversion units of N1 levels which are cascaded in sequence and have a tree structure. The high-speed bipolar parallel-serial conversion module comprises bipolar parallel-serial conversion units of N2 levels which are cascaded in sequence and have a tree structure. That is, the low-speed part is realized by CMOS devices, and the high-speed part is realized by bipolar devices. Through the combination of the two, the data transmission rate can be improved, and the power consumption and area of the parallel-serial conversion circuit are reduced. Meanwhile, the low-speed CMOS parallel-serial conversion module and the high-speed bipolar parallel-serial conversion module both use tree structures, further improving the data transmission rate.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial interface technology, and in particular to a high-speed parallel-to-serial conversion circuit. Background Technology

[0002] In recent years, with the continuous development of integrated circuits, chip integration has increased, as has chip complexity. Especially for data transmission between high-speed converters (such as AD / DA converters) and other devices, the increase in input / output data volume and transmission speed means that using traditional parallel interfaces would lead to an increase in the number of communication I / O pins, as well as parallel data skew and clock delay. Compared to parallel interfaces, the JESD204B high-speed serial interface has the advantages of minimizing the number of inter-chip communication I / O pins and reducing data transmission volume, thus gaining widespread use. Because of the 8b / 10b encoding method of the JESD204B protocol, its parallel data to serial conversion process requires first using a parallel structure to convert the data to 2b / 10b. N The data is in bit format, and then a tree structure is used for the final serialization of the data.

[0003] However, parallel circuit structures are only applicable to high-speed systems with a small number of bits, while tree circuit structures are not limited by the number of data bits. Furthermore, the JESD204B standard protocol has high requirements for digital logic, making it difficult to fabricate using bipolar technology. However, bipolar devices outperform CMOS devices in the same size and process technology, thus limiting the performance of traditional CMOS parallel-to-serial conversion circuits. For faster and more efficient chip communication, the ESIstream protocol effectively solves these problems. The ESIstream protocol provides a high-efficiency, high-speed serial interface based on 14b / 16b encoding, with simple core digital logic that is easily implemented using BiCMOS technology.

[0004] However, for the high-efficiency, high-speed serial interface of the ESIstream14b / 16b protocol, bipolar devices are required to achieve high speed. However, bipolar devices have high power consumption, small size and low integration. To reduce power consumption and process implementation difficulty, CMOS devices are required. However, CMOS devices have low speed, large size and high integration.

[0005] Therefore, there is an urgent need for a high-speed parallel-to-serial conversion technology solution that effectively balances speed, manufacturing difficulty, power consumption, and area, suitable for the ESIstream14b / 16b protocol. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-speed parallel-to-serial conversion technology solution, which combines CMOS devices and bipolar devices to design the parallel-to-serial conversion circuit. The low-speed part is implemented using CMOS devices, and the high-speed part is implemented using bipolar devices, so as to comprehensively reduce the power consumption and area of ​​the parallel-to-serial conversion circuit and improve the data transmission rate.

[0007] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0008] A high-speed parallel-to-serial conversion circuit includes:

[0009] The clock divider module receives an initial differential clock and divides the initial differential clock to obtain multiple divided clocks of different frequencies. The divided clocks include single-ended divided clocks and differential divided clocks.

[0010] A low-speed CMOS parallel-to-serial conversion module receives n bits of parallel data and the single-ended frequency divider clock. It includes N1 cascaded CMOS parallel-to-serial conversion units arranged in a tree structure. Under the control of the single-ended frequency divider clock, it performs N1-stage parallel-to-serial conversion on the n bits of parallel data to obtain n×2... -N1 Bit-parallel differential data;

[0011] High-speed bipolar parallel-to-serial converter module, connected to the n×2 -N1 The n×2 parallel differential data and the differential frequency divider clock include N2 cascaded bipolar parallel-to-serial conversion units in a tree structure. Under the control of the differential frequency divider clock, the n×2 -N1 The 1-bit parallel differential data is converted into 1-bit parallel differential data by N2-level parallel-to-serial conversion.

[0012] Where n = 2 N N = N1 + N2, where N1 and N2 are integers greater than or equal to 2.

[0013] Optionally, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, the i-th stage of the CMOS parallel-to-serial conversion unit includes n×2 -i There are CMOS parallel-to-serial conversion sub-units configured in parallel, where i is an integer from 1 to N1.

[0014] Optionally, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, in the j-th stage of the CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 selector and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2j-1th single-ended frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one with the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2j-th single-ended frequency divider clock. The data input terminals of the first and second D flip-flops serve as the data input terminals of the CMOS parallel-to-serial conversion subunit, and the data output terminal of the 2-to-1 selector serves as the data output terminal of the CMOS parallel-to-serial conversion subunit, where j is an integer from 1 to N1-1.

[0015] Optionally, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, in the N1-th stage of the CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 selector, an inverter, and three D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2N1-1th single-ended frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one to the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2N1th single-ended frequency divider clock. The data output terminal of the 2-to-1 selector is connected to the data input terminal of the third D flip-flop. The clock input terminal of the third D flip-flop is connected to the 2N1+1th single-ended frequency divider clock. The positive data output terminal of the third D flip-flop is connected to the input terminal of the inverter. The input signal and the output signal of the inverter constitute the n×2 -N1 One bit of parallel differential data.

[0016] Optionally, the frequency of the (2i-1)th single-ended divided clock is the same as the frequency of the 2ith single-ended divided clock, and the ratio of the frequency of the 2ith single-ended divided clock to the frequency of the initial differential clock is 2. i-N The ratio of the frequency of the 2N1+1th single-ended divided clock to the frequency of the initial differential clock is 2. N1+1-N .

[0017] Optionally, the 2-to-1 selector is a CMOS 2-to-1 selector, the D flip-flop is a CMOS D flip-flop, and the inverter is a CMOS inverter.

[0018] Optionally, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-to-serial converter module, the k-th stage of the bipolar parallel-to-serial converter unit includes n×2 -(N1+i) There are three parallel bipolar parallel-to-serial conversion subunits, where k is an integer from 1 to N².

[0019] Optionally, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-serial converter module, in the m-th stage of the bipolar parallel-serial converter unit, the bipolar parallel-serial converter subunit includes a 2-to-1 selector and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2m-1th differential frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one with the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2m-th differential frequency divider clock. The data input terminals of the first and second D flip-flops serve as the data input terminals of the bipolar parallel-serial converter subunit, and the data output terminal of the 2-to-1 selector serves as the data output terminal of the bipolar parallel-serial converter subunit, where m is an integer from 1 to N²-1.

[0020] Optionally, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-to-serial converter module, in the N2-stage bipolar parallel-to-serial converter unit, the bipolar parallel-to-serial converter subunit includes a 2-to-1 selector, a buffer, and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2N2-1th differential frequency divider clock. The positive data output terminal of the first D flip-flop is connected to the input terminal of the buffer. The output terminal of the buffer and the positive data output terminal of the second D flip-flop are connected one-to-one with the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2N2th differential frequency divider clock. The data output terminal of the 2-to-1 selector serves as the data output terminal of the bipolar parallel-to-serial converter subunit and outputs the 1-bit parallel differential data.

[0021] Optionally, the frequency of the (2k-1)th differential clock is the same as the frequency of the 2kth differential clock, and the ratio of the frequency of the 2kth differential clock to the frequency of the initial differential clock is 2. k+N1-N .

[0022] Optionally, the 2-to-1 selector is a bipolar 2-to-1 selector, the D flip-flop is a bipolar D flip-flop, and the buffer is a bipolar buffer.

[0023] Optionally, the 2-to-1 selector is a differential 2-to-1 selector, the D flip-flop is a differential D flip-flop, and the buffer is a differential buffer.

[0024] As described above, the high-speed parallel-to-serial conversion circuit provided by the present invention has at least the following beneficial effects:

[0025] A parallel-to-serial conversion circuit is designed by combining a clock divider module, a low-speed CMOS parallel-to-serial conversion module, and a high-speed bipolar parallel-to-serial conversion module. The low-speed CMOS parallel-to-serial conversion module consists of N1 cascaded CMOS parallel-to-serial conversion units arranged in a tree structure, while the high-speed bipolar parallel-to-serial conversion module consists of N2 cascaded bipolar parallel-to-serial conversion units arranged in a tree structure. In other words, the low-speed part is implemented using CMOS devices, and the high-speed part is implemented using bipolar devices. By combining the two, the data transmission rate can be comprehensively improved, while the power consumption and area of ​​the parallel-to-serial conversion circuit can be reduced. At the same time, the tree structure used in both the low-speed CMOS parallel-to-serial conversion module and the high-speed bipolar parallel-to-serial conversion module further improves the data transmission rate. Attached Figure Description

[0026] Figure 1 The diagram shown is a structural block diagram of the high-speed parallel-to-serial conversion circuit in this invention.

[0027] Figure 2 Displayed as Figure 1 Circuit diagram of the CMOS parallel-to-serial conversion sub-unit in the input stage and intermediate stage of the medium-low speed CMOS parallel-to-serial conversion module.

[0028] Figure 3 Displayed as Figure 1 Circuit diagram of the CMOS parallel-to-serial conversion sub-unit in the output stage of the medium-low speed CMOS parallel-to-serial conversion module.

[0029] Figure 4 Displayed as Figure 1 Circuit diagram of the input stage and intermediate stage bipolar parallel-to-serial conversion sub-unit of the medium-to-high-speed bipolar parallel-to-serial conversion module.

[0030] Figure 5 Displayed as Figure 1 Circuit diagram of the bipolar parallel-to-serial converter subunit in the output stage of the medium-to-high-speed bipolar parallel-to-serial converter module.

[0031] Figure 6 The diagram shown is a timing diagram of a serial-to-parallel conversion circuit without a buffer Td.

[0032] Figure 7 The diagram shows the timing of the serial-to-parallel conversion circuit with buffer Td added.

[0033] Figure 8The diagram shown is a circuit diagram of a 32-bit high-speed parallel-to-serial conversion circuit in an optional embodiment of the present invention. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0036] As described in the background section, the inventors have discovered that traditional parallel-to-serial conversion circuit structures have the following drawbacks:

[0037] 1. Due to the 10-bit parallel encoding data of the JESD204B protocol, the parallel-to-serial conversion circuit structure cannot fully adopt the tree structure suitable for high-speed applications, thus limiting the speed of the parallel-to-serial conversion circuit.

[0038] 2. For higher-speed chips, the traditional parallel-to-serial conversion circuit interface standard is too complex. To achieve higher performance, a large amount of digital logic is required, which cannot fully utilize the advantages of CMOS devices and bipolar devices, resulting in a complex parallel-to-serial conversion circuit structure and limited speed.

[0039] Based on this, the present invention provides a high-speed parallel-to-serial conversion technology solution: the parallel-to-serial conversion circuit is designed by combining CMOS devices and bipolar devices. The low-speed part is implemented using CMOS devices, and the high-speed part is implemented using bipolar devices, so as to comprehensively reduce the power consumption and area of ​​the parallel-to-serial conversion circuit and improve the data transmission rate. At the same time, both the low-speed part and the high-speed part adopt a tree structure to further improve the data transmission rate.

[0040] like Figure 1As shown, the present invention provides a high-speed parallel-to-serial conversion circuit, which includes:

[0041] The clock divider module receives the initial differential clock ±Fclk and divides the initial differential clock ±Fclk to obtain multiple divided clocks of different frequencies. The divided clocks include a single-ended divided clock CP and a differential divided clock ±CP.

[0042] The low-speed CMOS parallel-to-serial conversion module receives n-bit parallel data D[0]~D[n-1] and a single-ended frequency divider clock CP. It includes N1-stage cascaded CMOS parallel-to-serial conversion units in a tree structure. Under the control of the single-ended frequency divider clock CP, it performs N1-stage parallel-to-serial conversion on the n-bit parallel data D[0]~D[n-1] to obtain n×2 -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 ];

[0043] High-speed bipolar parallel-to-serial converter module, connected to n×2 -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 The differential frequency divider clock ±CP includes N2 cascaded bipolar parallel-to-serial converters in a tree structure. Under the control of the differential frequency divider clock ±CP, the n×2 -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 Perform N2-level parallel-to-serial conversion to obtain 1-bit parallel differential data ±LANEOUT;

[0044] Where n = 2 N N = N1 + N2, where N1 and N2 are integers greater than or equal to 2.

[0045] In detail, the clock divider module divides the initial differential clock ±Fclk input from the outside, resulting in a clock frequency of Fclk. The internal divider generates a single-ended clock CP and a differential clock ±CP for use in each stage of the parallel-to-serial conversion circuit. For example, the single-ended clock CP includes CP1, CP2, CP3, CP4, and CP5, with clock frequencies of 1 / 16Fclk, CP2, CP3, CP4, and CP5, respectively. 1 / 16Fclk, 1 / 8Fclk, 1 / 8Fclk and 1 / 4Fclk, differential frequency divider clock ±CP includes ±CP6, ±CP7, ±CP8, ±CP9, ±CP10 and ±CP11, the clock frequencies of differential frequency divider clocks ±CP6, ±CP7, ±CP8, ±CP9, ±CP10 and ±CP11 are 1 / 4Fclk, 1 / 4Fclk, 1 / 2Fclk, 1 / 2Fclk, Fclk and Fclk respectively.

[0046] It should be noted that the clock divider module can achieve various frequency division ratios through arbitrary superposition and cascading of internal dividers, not limited to divide-by-two, divide-by-four, divide-by-eight, etc., and can be selected according to actual needs. For details, please refer to existing technologies, which are not limited here.

[0047] Specifically, in the low-speed CMOS parallel-to-serial conversion module, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, the i-th stage CMOS parallel-to-serial conversion unit includes n×2 -i There are CMOS parallel-to-serial conversion sub-units configured in parallel, where i is an integer from 1 to N1.

[0048] More specifically, in the low-speed CMOS parallel-to-serial conversion module, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, except for the N1-th stage CMOS parallel-to-serial conversion unit, the structures of each CMOS parallel-to-serial conversion sub-unit in the first N1-1 stages of the CMOS parallel-to-serial conversion unit are the same, as follows: Figure 2 As shown, the input stage and intermediate stage of the entire low-speed CMOS parallel-to-serial conversion module have the same structure. The number of CMOS parallel-to-serial conversion sub-units decreases by a common ratio of 1 / 2 from the previous stage CMOS parallel-to-serial conversion unit to the next stage CMOS parallel-to-serial conversion unit.

[0049] More in detail, such as Figure 2 As shown, in the j-th stage CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 selector MUX2 and two D flip-flops DFF. The clock input terminals CP of the first and second D flip-flops DFF are respectively connected to the 2j-1th single-ended divided clock CP(2j-1) (not shown in the figure). The positive data output terminals Q of the first and second D flip-flops DFF are connected one-to-one with the two data input terminals of the 2-to-1 selector MUX2. The clock input terminal CP of the 2-to-1 selector MUX2 is connected to the 2jth single-ended divided clock CP(2j) (not shown in the figure). The data input terminals D of the first and second D flip-flops DFF serve as the data input terminals of the CMOS parallel-to-serial conversion subunit, and the data output terminal D of the 2-to-1 selector MUX2 serves as the data output terminal of the CMOS parallel-to-serial conversion subunit. Here, j is an integer from 1 to N1-1.

[0050] More specifically, in the low-speed CMOS parallel-to-serial conversion module, the structure of the N1-th stage CMOS parallel-to-serial conversion unit differs slightly from that of the previous N1-1 stage CMOS parallel-to-serial conversion units. This is because after completing the serialization function, it also needs to convert the full-swing single-ended output into a fully differential output for use by subsequent bipolar circuits. The structures of each CMOS parallel-to-serial conversion subunit in the N1-th stage CMOS parallel-to-serial conversion unit are the same, such as... Figure 3 As shown.

[0051] More in detail, such as Figure 3 As shown, along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, in the N1-stage CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 selector MUX2, an inverter T, and three D flip-flops DFF. The clock input terminals CP of the first and second D flip-flops DFF are respectively connected to the 2N1-1th single-ended frequency divider clock CP (2N1-1) (not shown in the figure). The positive data output terminal Q of the first and second D flip-flops DFF are also connected to the positive data output terminal Q of the second D flip-flops DFF. Q is connected one-to-one with the two data inputs of the 2-to-1 multiplexer MUX2. The clock input CP of the 2-to-1 multiplexer MUX2 is connected to the 2N1th single-ended clock divider CP(2N1) (not shown in the figure). The data output D of the 2-to-1 multiplexer MUX2 is connected to the data input of the third D flip-flop DFF. The clock input CP of the third D flip-flop DFF is connected to the 2N1+1th single-ended clock divider CP(2N1+1) (not shown in the figure). The positive output Q of the third D flip-flop DFF is connected to the input of the inverter T. The input signal and the output signal of the inverter T constitute an n×2... -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 One of them.

[0052] In this context, the frequency of the (2i-1)th single-ended clock CP(2i-1) is the same as the frequency of the 2ith single-ended clock CP(2i), and the ratio of the frequency of the 2ith single-ended clock CP(2i) to the frequency of the initial differential clock ± Fclk is 2. i-N The ratio of the frequency of the 2N1+1th single-ended divided clock CP(2N1+1) to the frequency of the initial differential clock ±Fclk is 2. N1+1-N .

[0053] like Figures 2-3As shown, each stage of the CMOS parallel-to-serial conversion sub-unit in the low-speed CMOS parallel-to-serial conversion module is a single-ended structure. In each stage of the CMOS parallel-to-serial conversion sub-unit, the input clocks of the D flip-flop (DFF) and the 2-to-1 selector (MUX2) are single-ended clocks with the same frequency. The D flip-flop (DFF) samples and temporarily stores data on the rising edge of the clock, and the 2-to-1 selector (MUX2) selects data at high and low levels respectively. Thus, two sets of parallel data can be combined into one set of serial data.

[0054] It should be emphasized that all CMOS parallel-to-serial conversion sub-units in the low-speed CMOS parallel-to-serial conversion module are CMOS structures, formed using CMOS technology or devices. That is to say, in the low-speed CMOS parallel-to-serial conversion module, the 2-to-1 selector MUX2 is a CMOS structure 2-to-1 selector, the D flip-flop DFF is a CMOS structure D flip-flop, and the inverter T is a CMOS structure inverter. For the specific process structure of the corresponding CMOS devices, please refer to the existing technology, which will not be elaborated here.

[0055] Similarly, in a high-speed bipolar parallel-to-serial converter module, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-to-serial converter module, the k-th stage bipolar parallel-to-serial converter unit includes n×2 -(N1+i) There are three parallel bipolar parallel-to-serial conversion subunits, where k is an integer from 1 to N².

[0056] In detail, in the high-speed bipolar parallel-to-serial converter module, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-to-serial converter module, except for the N2-th stage bipolar parallel-to-serial converter unit, the structures of each bipolar parallel-to-serial converter subunit in the first N2-1 stages are the same, as follows: Figure 4 As shown, the structure of the bipolar parallel-serial conversion sub-units in the input stage and intermediate stage of the entire high-speed bipolar parallel-serial conversion module is the same. The number of bipolar parallel-serial conversion sub-units decreases by a common ratio of 1 / 2 from the previous stage to the next stage.

[0057] More in detail, such as Figure 4As shown, in the m-th stage bipolar parallel-to-serial conversion unit, the bipolar parallel-to-serial conversion subunit includes a 2-to-1 selector MUX2 and two D flip-flops DFF. The clock input terminals ±CP of the first D flip-flop DFF and ±CP of the second D flip-flop DFF are respectively connected to the 2m-1th differential frequency divider clock ±CP(2m-1) (not shown in the figure). The positive data output terminals ±Q of the first D flip-flop DFF and ±Q of the second D flip-flop DFF are connected one-to-one with the two data input terminals of the 2-to-1 selector MUX2. The clock input terminal ±CP of the 2-to-1 selector MUX2 is connected to the 2m-th differential frequency divider clock ±CP(2m) (not shown in the figure). The data input terminals ±D of the first D flip-flop DFF and ±D of the second D flip-flop DFF serve as the data input terminals of the bipolar parallel-to-serial conversion subunit, and the data output terminal ±D of the 2-to-1 selector MUX2 serves as the data output terminal of the bipolar parallel-to-serial conversion subunit. Here, m is an integer from 1 to N2-1.

[0058] More specifically, in the high-speed bipolar parallel-to-serial conversion module, the N2nd stage bipolar parallel-to-serial conversion unit differs slightly in structure from the previous N2-1 stages. This is because it is the last stage of the high-speed bipolar parallel-to-serial conversion module, and the parallel-to-serial conversion circuit ultimately outputs the highest data rate, requiring strict timing. A buffer Td is added to this unit to delay the data and effectively reduce jitter in the serialized data. The N2nd stage bipolar parallel-to-serial conversion unit consists of only one bipolar parallel-to-serial conversion subunit, and its structure is as follows: Figure 5 As shown.

[0059] More in detail, such as Figure 5 As shown, along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-serial converter module, in the N2-stage bipolar parallel-serial converter unit, the bipolar parallel-serial converter subunit includes a 2-to-1 selector MUX2, a buffer Td, and two D flip-flops DFF. The clock input terminals ±CP of the first D flip-flop DFF and ±CP of the second D flip-flop DFF are respectively connected to the 2N2-1 differential frequency divider clock ±CP(2N2-1) (not shown in the figure). The positive data output terminal ±Q of the first D flip-flop DFF is connected to the input terminal of the buffer Td. The output terminal of the buffer Td and the positive data output terminal ±Q of the second D flip-flop DFF are connected one-to-one with the two data input terminals of the 2-to-1 selector MUX2. The clock input terminal ±CP of the 2-to-1 selector MUX2 is connected to the 2N2 differential frequency divider clock ±CP(2N2) (not shown in the figure). The data output terminal ±D of the 2-to-1 selector MUX2 serves as the data output terminal of the bipolar parallel-serial converter subunit and outputs 1 bit of parallel differential data ±LANEOUT (not shown in the figure).

[0060] In this context, the frequency of the (2k-1)th differential clock ±CP(2k-1) is the same as the frequency of the (2k)th differential clock ±CP(2k), and the ratio of the frequency of the (2k)th differential clock ±CP(2k) to the frequency of the initial differential clock ±Fclk is 2. k+N1-N .

[0061] like Figures 4-5 As shown, each stage of the high-speed bipolar parallel-to-serial conversion module is a differential structure. The 2-to-1 selector MUX2 is a differential 2-to-1 selector, the D flip-flop DFF is a differential D flip-flop, and the buffer Td is a differential buffer. In each stage of the bipolar parallel-to-serial conversion sub-unit, the input clocks of the D flip-flop DFF and the 2-to-1 selector MUX2 are differential clocks with the same frequency. The D flip-flop DFF samples at the rising edge of the clock and temporarily stores the data once. The 2-to-1 selector MUX2 selects the data at high and low levels respectively, thereby combining two sets of parallel data into one set of serial data.

[0062] It should be emphasized that all bipolar parallel-to-serial conversion sub-units in the high-speed bipolar parallel-to-serial conversion module are bipolar structures, formed using bipolar processes or devices. That is to say, in the high-speed bipolar parallel-to-serial conversion module, the 2-to-1 selector MUX2 is a bipolar 2-to-1 selector, the D flip-flop DFF is a bipolar D flip-flop, and the buffer Td is a bipolar buffer. For the specific process structure of the corresponding bipolar devices, please refer to the existing technology, which will not be repeated here.

[0063] Furthermore, to verify the technical effectiveness of buffer Td, a comparison was made between the technical solutions without buffer Td and those with buffer Td, resulting in the timing diagrams of the corresponding serial-to-parallel conversion circuits as follows: Figure 6 and Figure 7 As shown; Figure 6 The following is a timing diagram of the serial-to-parallel conversion circuit without a buffer Td, as shown. Figure 6 As shown, to ensure data integrity at ultra-high speeds, a certain amount of time needs to be reserved before synthesizing DATA_2, which inevitably leads to the problem that DATA_1 will experience a data jump at the end of the CLOCK_MUX clock. Figure 7 The diagram shows the timing of the serial-to-parallel conversion circuit with added buffer Td. By delaying DATA_1 for a certain period of time before serialization, both DATA_1 and DATA_2 have sufficient redundancy time, which effectively reduces the probability of data jumps.

[0064] More in detail, such as Figures 1-5 As shown, the working principle of the entire high-speed parallel-to-serial conversion circuit is as follows:

[0065] 1) The initial differential clock ±Fclk is input to the clock divider module. The clock divider module divides the initial differential clock ±Fclk to obtain single-ended divided clock CP and differential divided clock ±CP of various frequencies, which are used by each stage of the parallel-to-serial conversion circuit.

[0066] 2) The n-bit parallel data D[0]~D[n-1] is input to the low-speed CMOS parallel-to-serial conversion module. The N1-stage cascaded CMOS parallel-to-serial conversion units form a tree structure. The parallel-to-serial conversion rate of the first N1 stages is relatively low. The corresponding parallel-to-serial conversion units are implemented using CMOS circuits. The operating clock frequency increases exponentially from the input to the output. The n-bit parallel data D[0]~D[n-1] undergoes N1-stage parallel-to-serial conversion, and then passes through a single-ended to differential operation to obtain n×2 -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 ];

[0067] 3) n×2 -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 The input is fed into a high-speed bipolar parallel-to-serial converter module. The N2 stages of cascaded bipolar parallel-to-serial converters form a tree structure. The conversion rate increases exponentially with each subsequent N2 stages. Correspondingly, the parallel-to-serial converters are implemented using bipolar circuits, and their operating clock frequencies also increase exponentially with each stage. For n×2... -N1 Bit-parallel differential data ±lane1~±lane[n×2] -N1 Perform N2-level parallel-to-serial conversion to finally obtain 1-bit parallel differential data ±LANEOUT;

[0068] 4) The entire high-speed parallel-to-serial conversion circuit combines CMOS devices and bipolar devices. The low-speed part is implemented using CMOS devices, and the high-speed part is implemented using bipolar devices. Through the combination of the two, the power consumption area and speed performance are effectively balanced. At the same time, both the low-speed CMOS parallel-to-serial conversion module and the high-speed bipolar parallel-to-serial conversion module use a tree structure, which further improves the data transmission rate.

[0069] In an optional embodiment of the present invention, n = 32, N = 5, that is, the high-speed parallel-to-serial conversion circuit is specifically a 32-bit high-speed parallel-to-serial conversion circuit, such as... Figure 8 As shown, 32-bit parallel data D[0]~D

[31] are connected to the input terminal of the high-speed parallel-to-serial conversion circuit in the order shown in the figure. The high-speed parallel-to-serial conversion circuit is a 32:1 five-level tree structure. The working clock of the parallel-to-serial conversion circuit is provided by the clock divider module. The low-speed CMOS parallel-to-serial conversion module uses a full-swing single-ended clock, and the high-speed bipolar parallel-to-serial conversion module uses a fully differential clock. The specific clock frequencies are shown in CP1-CP11 in the figure.

[0070] In detail, such as Figure 8 As shown, the working principle of the five-level tree-structured parallel-to-serial conversion circuit is as follows:

[0071] 32-bit parallel data D[0]~D

[31] are sampled by the first D flip-flop DFF to generate 32 sets of intermediate data Q1. The 2-to-1 selector MUX1 performs the first serialization to generate 16 sets of parallel data D2.

[0072] The 16 sets of parallel data D2 are processed by the second D flip-flop DFF to generate 16 sets of intermediate data Q2. The 2-to-1 selector MUX2 performs a second serialization to generate 8 sets of parallel data D3.

[0073] After the 8 sets of parallel data D3 pass through the third D flip-flop DFF, they are then converted from single-ended to double-ended by the inverter T, outputting 8 sets of parallel differential data ±Q3 (i.e., Lane1-Lane8) to the subsequent bipolar circuit.

[0074] Eight sets of parallel differential data ±Q3 are processed by the fourth D flip-flop DFF to generate eight sets of intermediate data ±Q4. The two-to-one selector MUX2 performs a third serialization to generate four sets of parallel differential data ±D5.

[0075] Four sets of parallel differential data ±D5 are processed by the fourth D flip-flop DFF to generate four sets of intermediate data ±Q5. The two-to-one selector MUX2 performs the fourth serialization to generate two sets of parallel differential data ±D6.

[0076] The parallel differential data ±D6 passes through the fifth D flip-flop DFF to generate two sets of intermediate data ±Q6. One set of data is delayed by the buffer Td and then serialized for the fifth time by the 2-to-1 selector MUX2 to generate 1 bit of output differential data ±D7 (i.e. ±LANEOUT).

[0077] To further verify the above advantages of the present invention, in a BiCMOS process, as shown in... Figure 8 The parallel-to-serial conversion circuit structure shown in the figure is simulated for converting 32-bit parallel data to serial data. With initial differential clock ±Fclk inputs of 6.4 GHz and 8 GHz, respectively, the parallel data input rates are 0.4 GHz and 0.5 GHz, and the output serialized data rates are 12.8 GHz and 16 GHz, respectively. Therefore, the high-speed parallel-to-serial conversion circuit structure proposed in this invention is suitable for the ESIstream14b / 16b encoding protocol. Even with serialized output data rates of 12.8 GHz and 16 GHz, it still exhibits good serialization performance. The high-speed parallel-to-serial conversion circuit shown in this invention achieves a good balance between power consumption, area consumption, and speed performance.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed parallel-to-serial conversion circuit, characterized in that, include: The clock divider module receives an initial differential clock and divides the initial differential clock to obtain multiple divided clocks of different frequencies. The divided clocks include single-ended divided clocks and differential divided clocks. A low-speed CMOS parallel-to-serial conversion module receives n bits of parallel data and the single-ended frequency divider clock. It includes N1 cascaded CMOS parallel-to-serial conversion units arranged in a tree structure. Under the control of the single-ended frequency divider clock, it performs N1-stage parallel-to-serial conversion on the n bits of parallel data to obtain n×2... -N1 Bit-parallel differential data; High-speed bipolar parallel-to-serial converter module, connected to the n×2 -N1 The n×2 parallel differential data and the differential frequency divider clock include N2 cascaded bipolar parallel-to-serial conversion units in a tree structure. Under the control of the differential frequency divider clock, the n×2 -N1 The 1-bit parallel differential data is converted into 1-bit parallel differential data by N2-level parallel-to-serial conversion. Where n=2 N N = N1 + N2, where N1 and N2 are integers greater than or equal to 2; Along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-serial converter module, in the N2-stage bipolar parallel-serial converter unit, the bipolar parallel-serial converter subunit includes a 2-to-1 selector, a buffer, and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2N2-1th differential frequency divider clock. The positive data output terminal of the first D flip-flop is connected to the input terminal of the buffer. The output terminal of the buffer and the positive data output terminal of the second D flip-flop are connected one-to-one to the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2N2th differential frequency divider clock. The data output terminal of the 2-to-1 selector serves as the data output terminal of the bipolar parallel-serial converter subunit and outputs the 1-bit parallel differential data.

2. The high-speed parallel-to-serial conversion circuit according to claim 1, characterized in that, Along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, the i-th stage of the CMOS parallel-to-serial conversion unit includes n×2 -i There are CMOS parallel-to-serial conversion sub-units configured in parallel, where i is an integer from 1 to N1.

3. The high-speed parallel-to-serial conversion circuit according to claim 2, characterized in that, Along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, in the j-th stage of the CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 selector and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2j-1th single-ended frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one with the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2j-th single-ended frequency divider clock. The data input terminals of the first and second D flip-flops serve as the data input terminals of the CMOS parallel-to-serial conversion subunit, and the data output terminal of the 2-to-1 selector serves as the data output terminal of the CMOS parallel-to-serial conversion subunit, where j is an integer from 1 to N1-1.

4. The high-speed parallel-to-serial conversion circuit according to claim 2, characterized in that, Along the direction from the data input terminal to the data output terminal of the low-speed CMOS parallel-to-serial conversion module, in the N1-level CMOS parallel-to-serial conversion unit, the CMOS parallel-to-serial conversion subunit includes a 2-to-1 multiplexer, an inverter, and three D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2N1-1th single-ended frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one to the two data input terminals of the 2-to-1 multiplexer. The clock input terminal of the 2-to-1 multiplexer is connected to the 2N1th single-ended frequency divider clock. The data output terminal of the 2-to-1 multiplexer is connected to the data input terminal of the third D flip-flop. The clock input terminal of the third D flip-flop is connected to the 2N1+1th single-ended frequency divider clock. The positive data output terminal of the third D flip-flop is connected to the input terminal of the inverter. The input signal and the output signal of the inverter constitute the n×2 -N1 One bit of parallel differential data.

5. The high-speed parallel-to-serial conversion circuit according to claim 3 or 4, characterized in that, The frequency of the (2i-1)th single-ended frequency divider clock is the same as the frequency of the (2i)th single-ended frequency divider clock, and the ratio of the frequency of the (2i)th single-ended frequency divider clock to the frequency of the initial differential clock is 2. i-N The ratio of the frequency of the 2N1+1th single-ended frequency divider clock to the frequency of the initial differential clock is 2. N1+1-N .

6. The high-speed parallel-to-serial conversion circuit according to claim 3 or 4, characterized in that, The 2-to-1 selector is a CMOS structure 2-to-1 selector, the D flip-flop is a CMOS structure D flip-flop, and the inverter is a CMOS structure inverter.

7. The high-speed parallel-to-serial conversion circuit according to claim 1, characterized in that, Along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-to-serial converter module, the k-th stage of the bipolar parallel-to-serial converter unit includes n×2 -(N1+i) There are three parallel bipolar parallel-to-serial conversion subunits, where k is an integer from 1 to N².

8. The high-speed parallel-to-serial conversion circuit according to claim 7, characterized in that, Along the direction from the data input terminal to the data output terminal of the high-speed bipolar parallel-serial converter module, in the m-th stage of the bipolar parallel-serial converter unit, the bipolar parallel-serial converter subunit includes a 2-to-1 selector and two D flip-flops. The clock input terminals of the first and second D flip-flops are respectively connected to the 2m-1th differential frequency divider clock. The positive data output terminals of the first and second D flip-flops are connected one-to-one with the two data input terminals of the 2-to-1 selector. The clock input terminal of the 2-to-1 selector is connected to the 2m-th differential frequency divider clock. The data input terminals of the first and second D flip-flops serve as the data input terminals of the bipolar parallel-serial converter subunit, and the data output terminal of the 2-to-1 selector serves as the data output terminal of the bipolar parallel-serial converter subunit, where m is an integer from 1 to N²-1.

9. The high-speed parallel-to-serial conversion circuit according to claim 1 or 8, characterized in that, The frequency of the (2k-1)th differential clock is the same as the frequency of the (2k)th differential clock, and the ratio of the frequency of the (2k)th differential clock to the frequency of the initial differential clock is 2. k+N1-N .

10. The high-speed parallel-to-serial conversion circuit according to claim 1 or 8, characterized in that, The 2-to-1 selector is a bipolar 2-to-1 selector, the D flip-flop is a bipolar D flip-flop, and the buffer is a bipolar buffer.

11. The high-speed parallel-to-serial conversion circuit according to claim 10, characterized in that, The 2-to-1 selector is a differential 2-to-1 selector, the D flip-flop is a differential D flip-flop, and the buffer is a differential buffer.

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