PCB structure of a switch system and switch system applying same

Abstract

The application relates to the technical field of semiconductor and PCB structure, more specifically, the application relates to a PCB structure of a switch system and a switch system applying the same. The PCB structure comprises a PCB board stack and a first capacitor; the PCB board stack comprises a first signal layer, a first reference layer and a second reference layer, the first signal layer separates the first reference layer and the second reference layer, one foot of the first capacitor is connected with the first reference layer, and the other foot of the first capacitor is connected with the second reference layer, so that the first signal layer generates backflow when transmitting high-speed signals. The application can guarantee the integrity of the backflow path of signal current and the continuity of impedance, thereby improving the efficiency of signal transmission.

Description

Technical Field

[0001] This application relates to the field of semiconductor and PCB structure technology, and more specifically, to a PCB structure for a switch system and a switch system using the same. Background Technology

[0002] With the development of communication technology, the application of switching systems has become increasingly widespread. In current switch system-level designs, high-speed signals (SerDes) as striplines mostly use the ground plane (GND plane) as both the upper and lower reference planes. This results in a high number of PCB layers due to the requirement of the reference ground plane, significantly increasing the production cost of system design. At the same time, the heat loss caused by copper loss on the circuit board is also considerable.

[0003] Furthermore, due to the limitation of the total number of layers, there will be a significant voltage drop when power is supplied to the chip, which may pose a risk to the normal operation of the chip. Summary of the Invention

[0004] Based on the above-mentioned technical problems, the present invention aims to solve the high cost problem caused by the number of stacked layers in the PCB structure of the switch system by setting PCB board stacks and a first capacitor in the PCB structure, wherein the PCB board stack includes a first signal layer, a first reference layer and a second reference layer, so that the first signal layer generates return current when transmitting high-speed signals.

[0005] The first aspect of the present invention provides a PCB structure for a switch system, the PCB structure including a PCB stack and a first capacitor; the PCB stack includes a first signal layer, a first reference layer and a second reference layer, the first signal layer separating the first reference layer and the second reference layer, one leg of the first capacitor being connected to the first reference layer, and the other leg of the first capacitor being connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals.

[0006] In some embodiments of the present invention, when the first reference layer is a ground reference plane, the second reference layer is a power reference plane; when the first reference layer is a power reference plane, the second reference layer is a ground reference plane.

[0007] In some embodiments of the present invention, the PCB structure further includes a switching chip and an optical module slot, wherein the switching chip and the optical module slot are packaged at both ends of the first signal layer.

[0008] In some embodiments of the present invention, the first capacitor is located at one end close to the switching chip, so as to generate a first return current when the switching chip transmits a high-speed signal to the optical module slot.

[0009] In some embodiments of the present invention, the PCB structure further includes a second capacitor, which is located near one end of the optical module slot to generate a second return current when the optical module slot transmits a high-speed signal to the switching chip.

[0010] In some embodiments of the present invention, the first signal layer is a preset number, wherein the preset number is greater than or equal to 1.

[0011] In some embodiments of the present invention, when the preset number is greater than 1, each of the first signal layers separates the ground reference plane and the power reference plane.

[0012] In some embodiments of the present invention, when the preset number is 2, the power reference plane separates the two first signal layers.

[0013] Preferably, the first capacitor and / or the second capacitor are jumper capacitors.

[0014] A second aspect of the present invention provides a switch system that applies the PCB structure described in various embodiments of the present invention.

[0015] The technical solutions provided in this application embodiment have at least the following technical effects or advantages:

[0016] The PCB structure in various embodiments of this application includes a PCB stack and a first capacitor. The PCB stack includes a first signal layer, a first reference layer, and a second reference layer. The first signal layer separates the first reference layer and the second reference layer. One leg of the first capacitor is connected to the first reference layer, and the other leg of the first capacitor is connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals. This application can ensure the integrity of the return current path and the continuity of impedance, thereby improving the efficiency of signal transmission. The PCB structure described in this application is more suitable for the transmission of 10G / 25G NRZ high-speed SerDes signals.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Figure 1A schematic diagram of the PCB structure of a switch system in an exemplary embodiment of this application is shown;

[0020] Figure 2 A schematic diagram of the stacked arrangement of the PCB structure in an exemplary embodiment of this application is shown;

[0021] Figure 3 This diagram illustrates two ground reference planes in the prior art.

[0022] Figure 4 A schematic diagram illustrating the steps of a method for setting up the PCB structure of a switch system according to an exemplary embodiment of this application is shown.

[0023] Figure 5 This illustration shows a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0024] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application. It will be apparent to those skilled in the art that this application can be implemented without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0026] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. The drawings are not drawn to scale, and some details may be enlarged and omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0027] The following is in conjunction with the instruction manual appendix. Figure 1 -Appendix Figure 5 Several embodiments are given to describe exemplary implementations according to this application. It should be noted that the following application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementations of this application are not limited in any way. Rather, the implementations of this application can be applied to any applicable scenario.

[0028] In current switch system-level designs, high-speed signals (SerDes) are mostly transmitted as striplines using ground planes (GND planes) as both upper and lower reference planes. This results in a high number of PCB layers due to the requirement of ground planes, significantly increasing the production cost of system design. At the same time, the heat loss from copper losses on the circuit board is also considerable.

[0029] Furthermore, due to the limitation of the total number of layers, there will be a significant voltage drop when power is supplied to the chip, which may pose a risk to the normal operation of the chip.

[0030] Therefore, in some exemplary embodiments of this application, a PCB structure for a switch system is provided, with reference to... Figure 1 The PCB structure includes a PCB stack-up and a first capacitor. The PCB stack-up includes a first signal layer, a first reference layer, and a second reference layer. The first signal layer separates the first reference layer and the second reference layer. One leg of the first capacitor is connected to the first reference layer, and the other leg is connected to the second reference layer, so that the first signal layer generates return current when transmitting high-speed signals. The first signal layer contains the wiring required for high-speed signal transmission. The first capacitor is a coupling capacitor, generating AC signals as return current through coupling. Therefore, the capacitor acts as a bridge for the AC return current path.

[0031] In a preferred implementation, when the first reference layer is a ground reference plane, the second reference layer is a power reference plane; when the first reference layer is a power reference plane, the second reference layer is a ground reference plane.

[0032] In another preferred implementation, such as Figure 1As shown, the PCB structure also includes a switching chip and an optical module slot, which are packaged at opposite ends of the first signal layer. A first capacitor is located near the switching chip to generate a first return current when the switching chip transmits a high-speed signal to the optical module slot. Furthermore, the PCB structure also includes a second capacitor near the optical module slot to generate a second return current when the optical module slot transmits a high-speed signal to the switching chip. The first and second return currents here simply indicate the direction of the return current. In practical implementation, when the switching chip sends a high-speed signal to the optical module slot, half of the high-speed signal's return current will be generated between the ground reference plane and the power reference plane due to the placement of the first capacitor; similarly, as... Figure 1 As shown, when the front-end optical module slot sends a high-speed signal to the switching chip, half of the high-speed signal's return current is generated between the ground reference plane and the power reference plane due to the second capacitor. This ensures the integrity of the high-speed SerDes signal's return path and the continuity of its impedance, thereby improving signal transmission efficiency.

[0033] In some embodiments of this application, the first signal layer comprises a preset number, wherein the preset number is greater than or equal to 1. For example... Figure 2 As shown, when the preset number is greater than 1, each of the first signal layers separates the ground reference plane and the power reference plane. Figure 2 In this configuration, layer 1 is the ground reference plane, layer 2 is the signal layer, layer 3 is the power reference plane, layer 4 is the signal layer, layer 5 is the ground reference plane, layer 6 is the signal layer, layer 7 is the power reference plane, and so on. It's clear that each signal layer separates two reference layers. Reference layers are configured in pairs; when one reference layer is a power reference plane, the layer below it is a signal layer, and the layer below that is always a ground reference plane. Of course, there are also... Figure 2 As shown, the power reference plane of the third layer separates the two signal layers. That is, while one signal layer and two reference layers form a sub-stack, the third reference layer also serves as a reference layer in the second sub-stack. When the preset number is 2, the power reference plane separates the two first signal layers. Figure 2 In the diagram, the power reference plane of layer 3 is isolated from the two signal layers. This demonstrates that the reference layer, located in the middle of the stack, can simultaneously serve two signal layers. The total number of layers depends on the specific application scenario and is not limited to a single layer. Figure 3 The diagram shows 7 layers. In the prior art, the two reference planes are ground reference planes, such as... Figure 3As shown, this configuration of upper and lower ground reference planes requires more PCB layers, resulting in higher copper losses on the system board and compromising circuit performance. The PCB structure of the switch system provided in this embodiment even uses a hybrid reference plane for ground and power reference planes. Because a first capacitor is placed between them, the first signal layer separates the first reference layer and the second reference layer. One leg of the first capacitor is connected to the first reference layer, and the other leg is connected to the second reference layer, allowing the first signal layer to generate backflow when transmitting high-speed signals. This is suitable for transmitting 10G / 25G NRZ high-speed SerDes signals. Preferably, the first capacitor is a jumper capacitor, which not only acts as a bridge but also provides greater flexibility. The PCB structure of this application reduces heat generation, lowering thermal design costs. Furthermore, due to the improved power supply circuit, voltage drop losses at the PCB level are reduced, making it easier for the chip to operate within the design voltage range, thus ensuring circuit performance.

[0034] In some embodiments of the application, the PCB structure further includes a switching chip and an optical module slot. The switching chip is located at one end of the first signal layer of the PCB structure, and the optical module slot is located at the other end of the first signal layer of the PCB structure. A first capacitor is located near the switching chip to generate a first return current when the switching chip transmits a high-speed signal to the optical module slot. The PCB structure also includes a second capacitor near the optical module slot to generate a second return current when the optical module slot transmits a high-speed signal to the switching chip. Figure 1 As shown, this packaging structure facilitates signal transmission between the chip side and the optical module slot side of the switch system. For example... Figure 1 As shown, on the optical module slot side of the front port of the panel, preferably, the second capacitor is a jumper capacitor, which not only acts as a bridge but also provides greater flexibility. The jumper capacitor connecting the power supply and ground acts as a bridge, connecting the ground plane and the power plane together by using the capacitor as a bridge for the AC return path, thus forming the return path for the SerDes signal and ensuring the design impedance and signal transmission integrity of the SerDes high-speed signal.

[0035] The PCB structure in various embodiments of this application includes a PCB stack and a first capacitor. The PCB stack includes a first signal layer, a first reference layer, and a second reference layer. The first signal layer separates the first reference layer and the second reference layer. One leg of the first capacitor is connected to the first reference layer, and the other leg of the first capacitor is connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals. This application can ensure the integrity of the return current path and the continuity of impedance, thereby improving the efficiency of signal transmission. The PCB structure described in this application is more suitable for the transmission of 10G / 25G NRZ high-speed SerDes signals.

[0036] In some exemplary embodiments of this application, a switch system is also provided, which applies the PCB structure described in various embodiments of this application.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0038] In some exemplary embodiments of this application, a method for configuring the PCB structure of a switch system is also provided, such as... Figure 4 As shown, the setting method includes:

[0039] S1. The switch system is configured with a PCB board stack and a first capacitor. The PCB board stack is configured with a first signal layer, a first reference layer and a second reference layer. The first signal layer separates the first reference layer and the second reference layer. One leg of the first capacitor is connected to the first reference layer and the other leg of the first capacitor is connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals.

[0040] S2. When the first reference layer is a ground reference plane, the second reference layer is set as a power reference plane; when the first reference layer is a power reference plane, the second reference layer is set as a ground reference plane.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application.

[0042] It should also be emphasized that the system provided in this application embodiment can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results. Basic AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing technology, operating / interactive systems, and mechatronics. AI software technologies mainly include computer vision technology, robotics technology, biometrics technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0043] Please refer to the following. Figure 5 This illustrates a schematic diagram of a computer device provided by some embodiments of this application. For example... Figure 5 As shown, the computer device 2 includes: a processor 200, a memory 201, a bus 202, and a communication interface 203. The processor 200, the communication interface 203, and the memory 201 are connected via the bus 202. The memory 201 stores a computer program that can run on the processor 200. When the processor 200 runs the computer program, it executes the PCB structure setting method of the switch system provided in any of the foregoing embodiments of this application.

[0044] The memory 201 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 203 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0045] Bus 202 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. Memory 201 is used to store programs. After receiving an execution instruction, processor 200 executes the program. The PCB structure setting method of the switch system disclosed in any of the foregoing embodiments of this application can be applied to processor 200, or implemented by processor 200.

[0046] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the above method.

[0047] This application also provides a computer-readable storage medium storing a computer program thereon, which, when run by a processor, executes the PCB structure setting method of the switch system provided in any of the foregoing embodiments.

[0048] In addition, examples of the computer-readable storage medium may include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be described in detail here.

[0049] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the PCB structure configuration method for the switch system provided in any of the foregoing embodiments. The method includes: configuring a PCB stack and a first capacitor in the switch system; the PCB stack includes a first signal layer, a first reference layer, and a second reference layer; the first signal layer separates the first reference layer and the second reference layer; one leg of the first capacitor is connected to the first reference layer, and the other leg of the first capacitor is connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals; when the first reference layer is a ground reference plane, the second reference layer is configured as a power reference plane; when the first reference layer is a power reference plane, the second reference layer is configured as a ground reference plane.

[0050] It should be noted that the algorithms and displays provided herein are not inherently related to any particular computer, virtual device, or other equipment. Various general-purpose devices can also be used in conjunction with the teachings herein. The required structure for constructing such devices is obvious from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application. Numerous specific details are set forth in the specification provided herein. However, it is to be understood that embodiments of this application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0051] Those skilled in the art will understand that the various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art should understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the virtual machine creation apparatus according to embodiments of this application.

[0052] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A PCB structure for a switch system, characterized in that, The PCB structure includes a PCB stack-up and a first capacitor; the PCB stack-up includes a first signal layer, a first reference layer and a second reference layer, the first signal layer separates the first reference layer and the second reference layer, one leg of the first capacitor is connected to the first reference layer and the other leg of the first capacitor is connected to the second reference layer, so that the first signal layer generates a return current when transmitting high-speed signals; When the first reference layer is a ground reference plane, the second reference layer is a power reference plane; when the first reference layer is a power reference plane, the second reference layer is a ground reference plane; the PCB structure also includes a switching chip and an optical module slot, the switching chip and the optical module slot being packaged at both ends of the first signal layer; the first capacitor is located at one end close to the switching chip, so that a first return current is generated when the switching chip transmits a high-speed signal to the optical module slot.

2. The PCB structure of the switch system according to claim 1, characterized in that, The PCB structure also includes a second capacitor, which is located near one end of the optical module slot to generate a second return current when the optical module slot transmits high-speed signals to the switching chip.

3. The PCB structure of the switch system according to claim 1, characterized in that, The first signal layer consists of a preset number, which is greater than or equal to 1.

4. The PCB structure of the switch system according to claim 3, characterized in that, When the preset number is greater than 1, each of the first signal layers separates the ground reference plane and the power reference plane.

5. The PCB structure of the switch system according to claim 3, characterized in that, When the preset number is 2, the power reference plane separates the two first signal layers.

6. The PCB structure of the switch system according to claim 2, characterized in that, The first capacitor and / or the second capacitor are jumper capacitors.

7. A switching system, characterized in that, The switch system is configured with a PCB structure as described in any one of claims 1-6.

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