Semiconductor structure and method of forming the same
By alternately stacking support and sacrificial layers in the DRAM structure and controlling the substrate curvature and etching selectivity, the problems of capacitor deformation and short circuit during the manufacturing process are solved, thereby improving the manufacturing yield and performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-01-17
- Publication Date
- 2026-07-31
AI Technical Summary
In the existing technology, with the miniaturization of semiconductor structures such as DRAM, BPSG materials and oxide materials suffer from severe shrinkage problems during the manufacturing process, leading to capacitor bending or even short circuits, which affects capacitor performance and manufacturing yield.
By alternating stacking of support and sacrificial layers in the semiconductor structure, controlling the substrate curvature of the sacrificial layer to be no more than 30 μm, and setting the etching selectivity ratio of the support layer to the sacrificial layer to be greater than or equal to 800:1, capacitor holes are formed using a multi-pattern etching process, and the sacrificial layer is removed using a wet or ashing process to ensure that the support layer and the lower electrode layer are not damaged.
This reduces capacitor deformation, lowers the risk of short circuits between capacitors, and improves the manufacturing yield and performance of semiconductor structures.
Smart Images
Figure CN116056557B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] To improve the charge storage capacity of capacitors in semiconductor structures such as DRAM, multiple alternating support and sacrificial layers are formed during capacitor fabrication. To increase the capacitor's height, adjacent sacrificial layers are typically made of different materials; for example, the upper sacrificial layer might be made of oxide, while the lower sacrificial layer might be made of BPSG (Boro-phospho-silicate glass). However, with the further miniaturization of semiconductor structures like DRAM, BPSG and oxide materials experience significant shrinkage in subsequent processes, placing considerable stress on the capacitor manufacturing process. This can cause the capacitor to bend, and even lead to short circuits between capacitors, resulting in capacitor failure.
[0004] Therefore, how to reduce capacitor deformation and thus improve the performance of semiconductor structures is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides some embodiments of a semiconductor structure and a method for forming the same, which are used to reduce the deformation problem of capacitors, thereby improving the performance of the semiconductor structure and increasing the manufacturing yield of the semiconductor structure.
[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:
[0007] Provide substrate;
[0008] A stacked structure is formed on the top surface of the substrate. The stacked structure includes a support layer, a sacrificial layer, and a support layer that are alternately stacked along a first direction. The substrate curvature generated when forming the sacrificial layer is no greater than 30 μm. The first direction is perpendicular to the top surface of the substrate.
[0009] A capacitor hole is formed that penetrates the stacked structure along the first direction;
[0010] A lower electrode layer is formed covering the inner wall of the capacitor hole;
[0011] Remove the sacrificial layer;
[0012] A dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer are formed to form a capacitor including the lower electrode layer, the dielectric layer and the upper electrode layer.
[0013] In some embodiments, the etching selectivity ratio between the support layer and the sacrificial layer is greater than or equal to 800:1.
[0014] In some embodiments, the material of the support layer includes at least one selected from silicon carbonitride, silicon nitride, and silicon boronitride; and / or
[0015] The material of the sacrificial layer includes at least one of polycrystalline silicon, silicon carbide, and amorphous carbon.
[0016] In some embodiments, the polycrystalline silicon is crystalline polycrystalline silicon, and the grain size of the polycrystalline silicon is greater than or equal to 100 nm.
[0017] In some embodiments, the sacrificial layer is a crystalline polycrystalline silicon layer, and the method for forming the crystalline polycrystalline silicon layer includes:
[0018] Polycrystalline silicon material is deposited on the surface of the support layer to form an initial sacrificial layer;
[0019] The initial sacrificial layer is annealed at a preset temperature to form an annealed sacrificial layer.
[0020] The annealed sacrificial layer is subjected to chemical mechanical polishing.
[0021] In some embodiments, the step of forming a capacitor hole penetrating the stacked structure along the first direction includes:
[0022] The stacked structure is etched using a multi-pattern etching process to form the capacitor holes.
[0023] In some embodiments, the step of removing the sacrificial layer includes:
[0024] Forming an etched hole that penetrates the stacked structure along the first direction;
[0025] The sacrificial layer is removed along the etched hole to expose the outer surface of the lower electrode layer, which refers to the surface of the lower electrode layer that is away from the capacitor hole.
[0026] In some embodiments, the sacrificial layer is made of polycrystalline silicon; the step of removing the sacrificial layer along the etch hole includes: etching away the sacrificial layer along the etch hole using a wet etching process.
[0027] In some embodiments, tetramethylammonium hydroxide is used as the etching agent in the wet etching process.
[0028] In some embodiments, the sacrificial layer is made of amorphous carbon; the step of removing the sacrificial layer along the etched hole includes: removing the sacrificial layer along the etched hole using an ashing process.
[0029] In some embodiments, the sacrificial layer is made of silicon carbide; the step of removing the sacrificial layer along the etched hole includes: removing the sacrificial layer along the etched hole using an ashing process or a wet etching process.
[0030] In some embodiments, the step of forming a stacked structure on the top surface of the substrate includes:
[0031] A first support layer is formed on the top surface of the substrate;
[0032] A first sacrificial layer is formed on the surface of the first support layer;
[0033] A second support layer is formed on the surface of the first sacrificial layer;
[0034] A second sacrificial layer is formed on the surface of the second support layer;
[0035] A third support layer is formed on the surface of the second sacrificial layer to form the stacked structure including the first support layer, the first sacrificial layer, the second support layer, the second sacrificial layer and the third support layer.
[0036] In some embodiments, the materials of the first support layer, the second support layer, and the third support layer are all the same, the material of the first sacrificial layer is the same as the material of the second sacrificial layer, and the etching selectivity ratio between the first support layer and the first sacrificial layer is greater than or equal to 800:1.
[0037] In some embodiments, the materials of the first support layer, the second support layer, and the third support layer are all the same, the materials of the first sacrificial layer and the second sacrificial layer are different, and the substrate curvature generated when forming the first sacrificial layer and the second sacrificial layer is no greater than 30 μm.
[0038] The etching selectivity ratio between the first support layer and the first sacrificial layer, and the etching selectivity ratio between the first support layer and the second sacrificial layer are both greater than or equal to 800:1.
[0039] In some embodiments, the ratio between the depth of the capacitor aperture along the first direction and the width of the capacitor aperture along the second direction is greater than or equal to 100:1, and the second direction is parallel to the top surface of the substrate.
[0040] According to other embodiments, this disclosure also provides a semiconductor structure formed using the semiconductor structure formation method described in any of the preceding embodiments.
[0041] The semiconductor structure and its formation method provided in some embodiments of this disclosure reduce or even avoid the shrinkage and other deformations of the sacrificial layer during the capacitor manufacturing process by ensuring that the substrate curvature generated during the formation of the sacrificial layer in the stacked structure is no greater than 30 μm. This reduces or even avoids the probability of substrate curvature and other deformations caused by the sacrificial layer, thereby reducing stress generated during capacitor manufacturing and further reducing capacitor deformation problems, improving the performance of the semiconductor structure and increasing the manufacturing yield. Simultaneously, the reduced capacitor deformation also reduces the problem of short circuits between adjacent capacitors. Furthermore, some embodiments of this disclosure set the etching selectivity ratio between the sacrificial layer and the support layer inside the stacked structure to be greater than or equal to 800:1, thereby enabling the sacrificial layer in the stacked structure to be sufficiently removed without damaging the support layer and the lower electrode layer, reducing or even avoiding short circuits between the lower electrode layer and the upper electrode layer inside the capacitor, thereby further improving the manufacturing yield of the semiconductor structure. Attached Figure Description
[0042] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0043] Appendix Figure 2 - Appendix Figure 20 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. Detailed Implementation
[0044] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0045] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2 - Appendix Figure 20 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure according to a specific embodiment of this disclosure. For example... Figures 1-20 As shown, the method for forming the semiconductor structure includes the following steps:
[0046] Step S11, provide substrate 20;
[0047] Step S12: A stacked structure is formed on the top surface of the substrate 20. The stacked structure includes a support layer, a sacrificial layer, and a support layer alternately stacked along a first direction D1. The substrate curvature generated during the formation of the sacrificial layer is no greater than 30 μm. The first direction D1 is perpendicular to the top surface of the substrate 20. Figure 2 As shown;
[0048] Step S13, forming a capacitor hole 140 penetrating the stacked structure along the first direction D1, as shown below. Figure 14 As shown;
[0049] Step S14, forming a lower electrode layer 150 covering the inner wall of the capacitor hole 140, such as... Figure 15 As shown;
[0050] Step S15, remove the sacrificial layer, as follows Figure 18 As shown;
[0051] Step S16: A dielectric layer 190 covering the surface of the lower electrode layer 150 and an upper electrode layer 200 covering the surface of the dielectric layer 190 are formed to form a capacitor including the lower electrode layer 150, the dielectric layer 190, and the upper electrode layer 200, such as... Figure 20 As shown.
[0052] The substrate curvature, also known as wafer curvature, refers to the maximum distance difference between the surface of substrate 20 and a standard horizontal plane. In this specific embodiment, the semiconductor structure can be, but is not limited to, DRAM; this specific embodiment uses DRAM as an example for illustration. The substrate 20 can be, but is not limited to, a silicon substrate; this specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 20 can also be a gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI semiconductor substrate. The substrate 20 is used to support the device structure placed on it. The top surface of the substrate 20 refers to the surface of the substrate 20 facing the capacitor structure. The substrate 20 includes multiple active regions arranged in an array, and the active regions include bit line contact regions (…). Figure 1(Not shown in the diagram) and capacitor contact area 21, the bit line contact area being used for electrical connection with bit lines, and the capacitor contact area 21 being used for electrical connection with capacitor structures. The support layer, sacrificial layer, and support layer can be alternately deposited along the first direction D1 on the top surface of the substrate 20 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the stacked structure. This specific embodiment is illustrated using an example where the stacked structure includes the first support layer 22, the first sacrificial layer 25, the second support layer 23, the second sacrificial layer 26, and the third support layer 24 stacked sequentially along the first direction D1. In other specific embodiments, those skilled in the art can adjust the number of stacked support and sacrificial layers according to actual needs.
[0053] In some embodiments, the etch selectivity ratio between the support layer and the sacrificial layer is greater than or equal to 800:1. In one example, the etch selectivity ratio between the support layer and the sacrificial layer is (800:1) to (1200:1). By using an etch selectivity ratio between the support layer and the sacrificial layer greater than or equal to 800:1, it can be ensured that the support layer is not damaged during the removal of the sacrificial layer, thereby simplifying the processing of structures with high aspect ratios and achieving high aspect ratio etching.
[0054] In some embodiments, the material of the support layer includes at least one of silicon carbonitride, silicon nitride, and silicon boronitride.
[0055] In some embodiments, by combining the etching selectivity ratio between the aforementioned support layer and sacrificial layer with a ratio greater than or equal to 800:1, and by introducing a low-stress, ultra-high etching rate sacrificial layer material, the substrate curvature generated during the formation of the sacrificial layer can be made no greater than 30 μm, thereby reducing capacitor deformation. Based on this, the material of the sacrificial layer includes at least one of polycrystalline silicon, silicon carbide, and amorphous carbon.
[0056] In some embodiments, the polycrystalline silicon is crystalline polycrystalline silicon, and the grain size of the polycrystalline silicon is greater than or equal to 100 nm. In one example, the grain size of the polycrystalline silicon is 150 nm to 250 nm.
[0057] In some embodiments, the sacrificial layer is a crystalline polycrystalline silicon layer, and the method for forming the crystalline polycrystalline silicon layer includes:
[0058] Polycrystalline silicon material is deposited on the surface of the support layer to form an initial sacrificial layer;
[0059] The initial sacrificial layer is annealed at a preset temperature to form an annealed sacrificial layer.
[0060] The annealed sacrificial layer is subjected to chemical mechanical polishing.
[0061] The following description uses an example of a stacked structure comprising a first support layer 22, a first sacrificial layer 25, a second support layer 23, a second sacrificial layer 26, and a third support layer 24 stacked sequentially along the first direction D1. For example, after forming the first support layer 22 on the top surface of the substrate 20 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition, polysilicon material is deposited on the surface of the first support layer 22 to form an initial first sacrificial layer. Then, the initial first sacrificial layer is annealed at a preset temperature to form an annealed first sacrificial layer. Next, the annealed first sacrificial layer is subjected to planarization processes such as chemical mechanical polishing to obtain the first sacrificial layer 25, such that the substrate curvature generated during the formation of the first sacrificial layer 25 is no greater than 30 μm. In one example, the preset temperature is 600°C to 700°C. Then, a second support layer 23 is deposited on the surface of the first sacrificial layer 25, and the second sacrificial layer 26 is formed using the same formation process as the first sacrificial layer 25. Finally, the third support layer 24 is formed on the surface of the second sacrificial layer 26.
[0062] In some embodiments, the specific steps of forming a capacitor hole 140 penetrating the stacked structure along the first direction D1 include:
[0063] The stacked structure is etched using a multi-pattern etching process to form along the capacitor hole 140.
[0064] The following description continues to use the stacked structure comprising the first support layer 22, the first sacrificial layer 25, the second support layer 23, the second sacrificial layer 26, and the third support layer 24, which are stacked sequentially along the first direction D1. For example, after forming the stacked structure, a first capacitor mask layer 27 is formed on the top surface of the stacked structure, a second capacitor mask layer 28 is formed on the surface of the first capacitor mask layer 27, a third capacitor mask layer 29 is formed on the surface of the second capacitor mask layer 28, and a fourth capacitor mask layer 30 is formed on the surface of the third capacitor mask layer 29. This ensures the vertical morphology of the subsequently formed capacitor aperture 150 by forming multiple capacitor mask layers. The material of the first capacitor mask layer 27 can be silicon oxynitride, the material of the second capacitor mask layer 28 is silicon dioxide, the material of the third capacitor mask layer 29 is SOC (spin-coated carbon), and the material of the fourth capacitor mask layer 30 is silicon oxynitride. Next, a first etching mask layer 31 is formed on the surface of the fourth capacitor mask layer 30, and a second etching mask layer 32 is formed on the surface of the first etching mask layer 31. The material of the first etching mask layer 31 is spin-coated carbon, and the material of the second etching mask layer 32 is silicon oxynitride. Then, a first photoresist layer 33 is formed on the surface of the second etching mask layer 32, as shown below. Figure 2 As shown.
[0065] The first photoresist layer 33 is patterned by etching to form a first etching window 34 in the first photoresist layer 33 that exposes the second etching mask layer 32. Multiple first etching windows 34 are spaced apart along a second direction D2, which is parallel to the top surface of the substrate 20. Figure 3 As shown. The first etching mask layer 31 and the second etching mask layer 32 are etched downwards along the first etching window 34 to form a first trench 40 that continuously penetrates the first etching mask layer 31 and the second etching mask layer 32 along the first direction D1. A plurality of the first trenches 40 are arranged at intervals along the second direction D2, as shown. Figure 4 As shown. An oxide material such as silicon dioxide is deposited to form a first cover layer 50 that continuously covers the inner walls of the plurality of first trenches 40 and the top surface of the second etching mask layer 32, as shown. Figure 5 As shown. Then, the first cover layer 50 covering the top surface of the second etch mask layer 32 and the first cover layer 50 located on the bottom wall of the first trench 40 are removed, leaving the first cover layer 50 remaining on the sidewall of the first trench 40 as the first sidewall 60. After removing the first etch mask layer 31 and the second etch mask layer 32, the following is obtained: Figure 6 The structure shown.
[0066] Subsequently, the first trench 40 is backfilled to form a first filler layer 70 covering the fourth capacitor mask layer 30 and the first sidewall 60, and a third etch mask layer 71 covering the surface of the first filler layer 70, a fourth etch mask layer 72 covering the surface of the third etch mask layer 71, and a fifth etch mask layer 73 covering the surface of the fourth etch mask layer 72 are formed, as follows. Figure 7 As shown. The first filling layer 70 can be made of spin-coated carbon, the third etching mask layer 71 is made of silicon oxynitride, the fourth etching mask layer 72 is made of spin-coated carbon, and the fifth etching mask layer 73 is made of silicon oxynitride. Next, the fifth etching mask layer 73 and the fourth etching mask layer 72 are etched to form a second trench 80 that continuously penetrates the fifth etching mask layer 73 and the fourth etching mask layer 72 along the first direction D1. Then, a second cover layer 81 is formed that continuously covers the inner walls of the plurality of second trenches 80 spaced apart along the second direction D2 and the top surface of the fifth etching mask layer 73, as shown. Figure 8 As shown. The second cover layer 81 covering the top surface of the fifth etch mask layer 73 and the bottom wall of the second trench 80 is removed. The remaining second cover layer 81 on the sidewall of the second trench 80 serves as the second sidewall 90. Figure 9 As shown. After removing the fifth etch mask layer 73 and the fourth etch mask layer 72, the result is as follows. Figure 10 The structure shown.
[0067] Using the first sidewall 60 and the second sidewall 90 as a mask pattern, the fourth capacitor mask layer 30 and the third capacitor mask layer 29 are etched downwards to form a third trench 110 that continuously penetrates the fourth capacitor mask layer 30 and the third capacitor mask layer 29 along the first direction D1. After removing the first sidewall 60, the second sidewall 90, the third etch mask 71, and the first filler layer 70, the following is obtained: Figure 11 The structure is shown. The second capacitor mask layer 28 is etched downwards along the third trench 110 to form a fourth trench 120 penetrating the second capacitor mask layer 28 along the first direction D1, as shown. Figure 12 As shown. Then, the first capacitor mask layer 27 is etched downwards along the fourth trench 120 to form a fifth trench 130 penetrating the first capacitor mask layer 27 along the first direction D1, as shown. Figure 13 As shown. Then, the stacked structure is etched downwards along the plurality of fifth trenches 130 to form a plurality of capacitor holes 140 penetrating the stacked structure along the first direction D1. The capacitor holes 140 expose the capacitor contact areas 21 in the substrate 20, and the plurality of capacitor holes 140 are spaced apart along the second direction D2, as shown. Figure 14 As shown.
[0068] In some embodiments, the specific steps for removing the sacrificial layer include:
[0069] An etched hole 170 is formed along the first direction D1 through the stacked structure, such as Figure 17 As shown;
[0070] The first sacrificial layer 25 and the second sacrificial layer 26 are removed along the etched hole 170, exposing the outer surface of the first electrode layer 150. The outer surface of the first electrode layer 150 refers to the surface of the first electrode layer 150 that faces away from the capacitor hole 140. Figure 18 As shown.
[0071] In some embodiments, the material of the sacrificial layer is polycrystalline silicon; the specific steps for removing the sacrificial layer along the etch hole 170 include: using a wet etching process to etch away the sacrificial layer along the etch hole.
[0072] In some embodiments, tetramethylammonium hydroxide is used as the etching agent in the wet etching process.
[0073] The following description continues to use the example of a stacked structure comprising a first support layer 22, a first sacrificial layer 25, a second support layer 23, a second sacrificial layer 26, and a third support layer 24 stacked sequentially along the first direction D1, wherein the materials of the first sacrificial layer 25 and the second sacrificial layer 26 are both crystalline polycrystalline silicon, and the materials of the first support layer 22, the second support layer 23, and the third support layer 24 are all silicon carbonitride. After forming the capacitor holes 140, a conductive material such as TiN is deposited on the stacked structure to form a lower electrode layer 150 that continuously covers the inner walls of the plurality of capacitor holes 140 spaced apart along the second direction D2 and covers the top surface of the third support layer 24. Figure 15 As shown. The lower electrode layer 150 is electrically connected to the capacitor contact region 21 inside the substrate 20. Next, a sixth etching mask layer 160 is formed above the stacked structure, and a second photoresist layer 161 is formed on the surface of the sixth etching mask layer 160. The second photoresist layer 161 has a second etching window 162, as shown. Figure 16 As shown. The first electrode layer 150 and the stacked structure are etched downwards along the second etching window 162, forming an etching hole 170 that penetrates the first electrode layer 150 and the stacked structure along the first direction D1, as shown. Figure 17As shown. Then, using tetramethylammonium hydroxide as an etchant, a wet etching process is employed to remove all of the first sacrificial layer 25 and the second sacrificial layer 26 along the etched hole 170, forming a gap 180 between adjacent support layers (e.g., between the first support layer 22 and the second support layer 23, and between the second support layer 23 and the third support layer 24), as shown. Figure 18 As shown, when tetramethylammonium hydroxide is used as the etchant, the etching selectivity ratio between the crystalline polycrystalline silicon and the silicon carbonitride can reach over 800:1. This allows for the thorough removal of the first sacrificial layer 25 and the second sacrificial layer 26 without damaging the first support layer 22, the second support layer 23, and the third support layer 24. Simultaneously, tetramethylammonium hydroxide does not damage the lower electrode layer 150 formed from conductive materials such as TiN, ensuring the integrity of the lower electrode layer 150 and avoiding short circuits between the upper and lower electrode layers due to damage to the lower electrode layer 150. Furthermore, since the substrate curvature generated during the formation of the first sacrificial layer 25 and the second sacrificial layer 26 is no greater than 30 μm, the substrate deformation caused during the process from the formation of the first sacrificial layer 25 and the second sacrificial layer 26 to the complete removal of the first sacrificial layer 25 and the second sacrificial layer 26 is very small. This ensures that after the removal of the first sacrificial layer 25 and the second sacrificial layer 26, the capacitor hole and the lower electrode layer 150 will hardly undergo bending or other deformation, reducing the deformation problem of the capacitor, improving the performance of the semiconductor structure, and increasing the manufacturing yield of the semiconductor structure.
[0074] After removing the first sacrificial layer 25 and the second sacrificial layer 26, a material with a high dielectric constant is deposited on the stacked structure to form the dielectric layer 190 covering the outer surface of the lower electrode layer 150 (i.e., the surface of the lower electrode layer 150 facing the etched hole 170) and the inner surface of the lower electrode layer 150 (i.e., the surface opposite to the outer surface of the lower electrode layer 150), such as... Figure 19 As shown. Subsequently, conductive materials such as TiN are deposited on the stacked structure to form an upper electrode layer 200 covering the dielectric layer 190, as shown. Figure 20 As shown.
[0075] In other specific embodiments, a filler layer covering a portion of the surface of the lower electrode layer 150 and filling the lower part of the capacitor hole 140 can be formed within the capacitor hole 140 after the lower electrode layer 150 is formed and before the etched hole 170 is formed. In this case, the dielectric layer 190 located within the capacitor hole 140 covers a portion of the surface of the lower electrode layer 150 and the top surface of the filler layer. In one example, the filler layer is made of an insulating dielectric material to support the lower electrode layer 150, further preventing the lower electrode layer 150 from tilting or collapsing during the subsequent removal of the first sacrificial layer 25 and the second sacrificial layer 26. It also avoids the problem that the lower electrode layer 150 located at the bottom of the capacitor hole 140 cannot be covered due to the high aspect ratio of the capacitor hole 140. In another example, the filling layer is made of a conductive material to support the lower electrode layer 150 and to avoid the problem that the lower electrode layer 150 located at the bottom of the capacitor hole 140 cannot be covered due to the high aspect ratio of the capacitor hole 140, while increasing the capacitance of the capacitor.
[0076] In other embodiments, the sacrificial layer is made of amorphous carbon; the specific steps for removing the sacrificial layer along the etched hole include: removing the sacrificial layer along the etched hole 170 using an ashing process.
[0077] In other embodiments, the sacrificial layer is made of silicon carbide; the step of removing the sacrificial layer along the etched hole includes removing the sacrificial layer along the etched hole using an ashing process or a wet etching process.
[0078] In some embodiments, the specific steps of forming a stacked structure on the top surface of the substrate 20 include:
[0079] A first support layer 22 is formed on the top surface of the substrate 20;
[0080] A first sacrificial layer 25 is formed on the surface of the first support layer;
[0081] A second support layer 23 is formed on the surface of the first sacrificial layer;
[0082] A second sacrificial layer 26 is formed on the surface of the second support layer;
[0083] A third support layer 24 is formed on the surface of the second sacrificial layer to form the stacked structure including the first support layer 22, the first sacrificial layer 25, the second support layer 23, the second sacrificial layer 26 and the third support layer 24.
[0084] In some embodiments, the materials of the first support layer 22, the second support layer 23, and the third support layer 24 are all the same, the materials of the first sacrificial layer 25 and the second sacrificial layer 26 are the same, and the etching selectivity ratio between the first support layer 22 and the first sacrificial layer 25 is greater than or equal to 800:1.
[0085] Specifically, by using the same materials for the first support layer 22, the second support layer 23, and the third support layer 24, and the same materials for the first sacrificial layer 25 and the second sacrificial layer 26, the manufacturing process of the stacked structure can be simplified, and the manufacturing cost of the stacked structure can be reduced. Having an etching selectivity ratio greater than or equal to 800:1 between the first support layer 22 and the first sacrificial layer 25 ensures that the first support layer 22, the second support layer 23, and the third support layer 24 are not damaged during the removal of the first sacrificial layer 25 and the second sacrificial layer 26, thus simplifying the processing of structures with high aspect ratios.
[0086] In other embodiments, the materials of the first support layer 22, the second support layer 23, and the third support layer 24 are all the same, the materials of the first sacrificial layer 25 and the second sacrificial layer 26 are different, and the substrate curvature generated when forming the first sacrificial layer 25 and the second sacrificial layer 26 is no greater than 30 μm.
[0087] The etching selectivity ratio between the first support layer 22 and the first sacrificial layer 25, and the etching selectivity ratio between the first support layer 22 and the second sacrificial layer 26 are both greater than or equal to 800:1.
[0088] By setting the materials of the first sacrificial layer 25 and the second sacrificial layer 26 to be different, the flexibility of material selection for the stacked structure can be improved, thereby helping to further increase the height of the capacitor hole and the capacitance of the capacitor.
[0089] In some embodiments, the ratio between the depth of the capacitor hole 140 along the first direction D1 and the width of the capacitor hole 140 along the second direction D2 is greater than or equal to 100:1, and the second direction D2 is parallel to the top surface of the substrate 20.
[0090] This specific embodiment also provides a semiconductor structure, formed using the semiconductor structure formation method described in any of the preceding embodiments. A schematic diagram of the semiconductor structure described in this specific embodiment can be found [link to schematic diagram]. Figure 20 The semiconductor structure described in this specific embodiment can be as follows: Figures 1-20 The semiconductor structure shown is formed using the method described.
[0091] The semiconductor structure and its formation method provided in some embodiments of this specific implementation reduce or even avoid the shrinkage and other deformations of the sacrificial layer during the capacitor manufacturing process by ensuring that the substrate curvature generated during the formation of the sacrificial layer in the stacked structure is no greater than 30 μm. This reduces or even avoids the probability of substrate curvature and other deformations caused by the sacrificial layer, thereby reducing stress generated during capacitor manufacturing and further reducing capacitor deformation problems, improving the performance of the semiconductor structure, and increasing the manufacturing yield of the semiconductor structure. Simultaneously, the reduced capacitor deformation also reduces the problem of short circuits between adjacent capacitors. Furthermore, some embodiments of this disclosure set the etching selectivity ratio between the sacrificial layer and the support layer inside the stacked structure to be greater than or equal to 800:1, thereby enabling the sacrificial layer in the stacked structure to be sufficiently removed without damaging the support layer and the lower electrode layer, reducing or even avoiding short circuits between the lower electrode layer and the upper electrode layer inside the capacitor, thereby further improving the manufacturing yield of the semiconductor structure.
[0092] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method of forming a semiconductor structure, characterized by, Includes the following steps: Provide substrate; A stacked structure is formed on the top surface of the substrate. The stacked structure includes a support layer, a sacrificial layer, and a support layer that are alternately stacked along a first direction. The substrate curvature generated when forming the sacrificial layer is no greater than 30 μm. The first direction is perpendicular to the top surface of the substrate. A capacitor hole is formed that penetrates the stacked structure along the first direction; A lower electrode layer is formed covering the inner wall of the capacitor hole; Remove the sacrificial layer; A dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer are formed to form a capacitor including the lower electrode layer, the dielectric layer and the upper electrode layer; The steps for removing the sacrificial layer include: Forming an etched hole that penetrates the stacked structure along the first direction; The sacrificial layer is removed along the etched hole to expose the outer surface of the lower electrode layer, wherein the outer surface of the lower electrode layer refers to the surface of the lower electrode layer that is away from the capacitor hole. The sacrificial layer is a crystalline polycrystalline silicon layer, and the method for forming the crystalline polycrystalline silicon layer includes: Polycrystalline silicon material is deposited on the surface of the support layer to form an initial sacrificial layer; The initial sacrificial layer is annealed at a preset temperature to form an annealed sacrificial layer. The annealed sacrificial layer is subjected to chemical mechanical polishing.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The etching selectivity ratio between the support layer and the sacrificial layer is greater than or equal to 800:
1.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the support layer includes at least one of silicon carbonitride, silicon nitride, and silicon boronitride.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, The grain size of the crystalline polycrystalline silicon layer is greater than or equal to 100 nm.
5. The method for forming a semiconductor structure according to any one of claims 1-4, characterized in that, The step of forming a capacitor hole through the stacked structure along the first direction includes: The stacked structure is etched using a multi-pattern etching process to form the capacitor holes.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The sacrificial layer is made of polycrystalline silicon; The step of removing the sacrificial layer along the etched hole includes: etching away the sacrificial layer along the etched hole using a wet etching process.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, The wet etching process uses tetramethylammonium hydroxide as the etching agent.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, The sacrificial layer is made of amorphous carbon. The step of removing the sacrificial layer along the etched hole includes: removing the sacrificial layer along the etched hole using an ashing process.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The sacrificial layer is made of silicon carbide; The step of removing the sacrificial layer along the etched hole includes: removing the sacrificial layer along the etched hole using an ashing process or a wet etching process.
10. The method for forming a semiconductor structure according to any one of claims 1-4, characterized in that, The step of forming a stacked structure on the top surface of the substrate includes: A first support layer is formed on the top surface of the substrate; A first sacrificial layer is formed on the surface of the first support layer; A second support layer is formed on the surface of the first sacrificial layer; A second sacrificial layer is formed on the surface of the second support layer; A third support layer is formed on the surface of the second sacrificial layer to form the stacked structure including the first support layer, the first sacrificial layer, the second support layer, the second sacrificial layer and the third support layer.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The materials of the first support layer, the second support layer, and the third support layer are all the same. The materials of the first sacrificial layer and the second sacrificial layer are the same. The etching selectivity ratio between the first support layer and the first sacrificial layer is greater than or equal to 800:
1.
12. The method for forming a semiconductor structure according to claim 10, characterized in that, The materials of the first support layer, the second support layer, and the third support layer are all the same. The materials of the first sacrificial layer and the second sacrificial layer are different. The substrate curvature generated when forming the first sacrificial layer and the second sacrificial layer is no greater than 30 μm. The etching selectivity ratio between the first support layer and the first sacrificial layer, and the etching selectivity ratio between the first support layer and the second sacrificial layer are both greater than or equal to 800:
1.
13. The method for forming a semiconductor structure according to any one of claims 1-4, characterized in that, The ratio between the depth of the capacitor aperture along the first direction and the width of the capacitor aperture along the second direction is greater than or equal to 100:1, and the second direction is parallel to the top surface of the substrate.
14. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method described in any one of claims 1-13.