Instruction dispatch routing

Abstract

A method of instruction dispatch routing includes receiving an instruction for dispatch to an issue queue of a plurality of issue queues, determining a priority state of the instruction, selecting a round-robin order based on the priority state, wherein a first round-robin order is associated with priority instructions and a second round-robin order different from the first round-robin order is associated with non-priority instructions, selecting an issue queue of the plurality of issue queues based on the selected round-robin order, and dispatching the instruction to the selected issue queue.

Description

Background Technology

[0001] Processor cores with multiple issue queues driving multiple execution units typically utilize a mechanism to distribute dispatched instructions into these issue queues. Traditional processor cores usually achieve this by distributing instructions sequentially in instruction order. That is, a traditional processor core dispatches instructions by starting at one issue queue and round-robining through the queues to sequentially assign an instruction to each issue queue in instruction order. However, this traditional technique can lead to performance degradation. For example, it's often known which issue queues are full, and those queues are skipped during the round-robin. However, reacting after an issue queue has become overfilled is detrimental to performance. For performance purposes, it's desirable to assign an equal workload to each issue queue, and this is not as simple as simply distributing the number of instructions equally to each issue queue because all instructions differ in terms of the resources they use. Summary of the Invention

[0002] This disclosure may include methods, processors, and systems for instruction dispatch routing. In one aspect, a method includes: receiving an instruction for dispatch to one of a plurality of release queues; determining a priority state of the instruction; selecting a round-robin order based on the priority state, wherein a first round-robin order is associated with a priority instruction and a second round-robin order different from the first round-robin order is associated with a non-priority instruction; selecting a release queue among the plurality of release queues based on the selected round-robin order; and dispatching the instruction to the selected release queue.

[0003] In another aspect, a method includes receiving a plurality of instructions during a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; dispatching each of the one or more instructions designated as resource-intensive to a corresponding release queue of a plurality of release queues according to a first rotation order; and dispatching each of the one or more instructions designated as non-resource-intensive to a corresponding release queue of the plurality of release queues according to a second rotation order opposite to the first rotation order.

[0004] In another aspect, a processor includes: an instruction fetch unit; a dispatch unit communicatively coupled to the instruction fetch unit; and a plurality of release queues communicatively coupled to the dispatch unit. The dispatch unit is configured to: receive a plurality of instructions from the instruction fetch unit; determine a corresponding priority state for each of the plurality of instructions; and select a round-robin order for each of the plurality of instructions based on the corresponding priority state. A first round-robin order is associated with priority instructions, and a second round-robin order, different from the first round-robin order, is associated with non-priority instructions. The dispatch unit is further configured to: select a corresponding release queue from the plurality of release queues for each of the plurality of instructions based on the corresponding selected round-robin order; and dispatch each of the plurality of instructions to the corresponding selected release queue.

[0005] In another aspect, a computer system includes: a memory configured to store program code; and a processor communicatively coupled to the memory and configured to execute the program code. The processor includes an instruction fetch unit; a dispatch unit communicatively coupled to the instruction fetch unit; and a plurality of dispatch queues communicatively coupled to the dispatch unit. The dispatch unit is configured to receive a plurality of instructions in a cycle. The plurality of instructions includes one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive. The dispatch unit is configured to dispatch each of the one or more instructions designated as resource-intensive to a corresponding dispatch queue of the plurality of dispatch queues according to a first round-robin order; and to dispatch each of the one or more instructions designated as non-resource-intensive to a corresponding dispatch queue of the plurality of dispatch queues according to a second round-robin order opposite to the first round-robin order.

[0006] The above overview is not intended to describe every illustrated embodiment or every implementation of this disclosure. Attached Figure Description

[0007] It should be understood that the accompanying drawings depict only exemplary embodiments and are therefore not intended to limit the scope. Exemplary embodiments will be described with additional features and details using the drawings, wherein: Figure 1 This is a high-level block diagram illustrating one embodiment of an example computer system. Figure 2 This is a high-level block diagram of one embodiment of the example processor core. Figure 3 yes Figure 2 A partial view of one embodiment of the processor core. Figure 4 yes Figure 2 A partial view of one embodiment of the processor core. Figure 5 This is a flowchart depicting an example method for dispatching instructions, representing one embodiment. Figure 6 This is a flowchart of another embodiment of an example method for dispatching instructions. Figure 7 This is a flowchart of another embodiment of an example method for dispatching instructions.

[0008] By convention, features described differently are not drawn to scale, but rather to emphasize specific features relevant to the exemplary embodiments. Detailed Implementation

[0009] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, and specific exemplary embodiments are illustrated in the drawings by way of example. However, it should be understood that other embodiments may be utilized, and logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the drawings and specification should not be construed as limiting the order in which the various steps can be performed. Therefore, the following detailed description should not be construed as restrictive.

[0010] The implementation method is described below…

[0011] Figure 1 This is a high-level block diagram illustrating one embodiment of an example computer system 10. The computer system 10 includes one or more processors 12 coupled to various additional components, such as system memory 14, input / output (I / O) 16, and memory 18, via one or more communication paths 20 implemented, for example, using one or more buses, networks, interconnects, etc. Each processor 12 may include one or more processor cores 22 and local memory 24, such as internal system memory and / or one or more levels of cache memory. In some embodiments, each processor 12 may be configured similarly, while in other embodiments, processors with different configurations may be used together. Further, in a multi-core processor implementation, each core 22 may be configured similarly or differently from other cores 22 within the same processor 12. It should be understood that the embodiments described herein can be used in a wide variety of system configurations, including single-processor and / or multi-processor configurations and single-core and / or multi-core configurations. Furthermore, the embodiments described herein can be used with different types of dedicated processors, such as graphics processors, network processors, coprocessors, service processors, embedded processors, etc.

[0012] In some embodiments, system memory 14 may include random access memory (RAM) representing the primary volatile memory of the system. Further, in some embodiments, a single system memory 14 may be supported, while in other embodiments, the memory may be distributed across multiple nodes, with one or more processors 12 implemented within each node and non-uniform memory access occurring between portions of the memory in the same or different nodes of the system. Nodes may also be arranged in various tiers, for example, within different cabinets, racks, cards, slots, etc., and interconnected via a high-speed network.

[0013] System 10 also includes various input / output (I / O) interfaces and devices 16, which may vary depending on the type of system. For example, in some systems, I / O 16 may include adapters and / or interfaces to one or more external networks, such as private networks, public networks, wired networks, wireless networks, etc. Furthermore, for single-user systems such as desktop computers, laptop computers, tablet computers, mobile devices, etc., I / O 16 may also include user input devices such as mice, keyboards, touchscreens, microphones, imaging devices, etc., for receiving user input, and graphic displays and / or audio playback devices for displaying information. System 10 may also include a storage subsystem 18, which may include non-removable mass storage drives such as solid-state drives and hard disk drives, and removable drives such as flash drives and optical disc drives, the latter of which can be used, for example, to read program code and / or data stored on computer-readable media such as optical discs.

[0014] For example, sample program code 28 is shown in memory 24, which may represent different types of instructions that can be executed by core 22 of processor 12, including, for example, user-level applications, operating systems, firmware, middleware, device drivers, virtualization program code, etc. It should be understood that program code 28 may also be stored from time to time in other computer-readable media, including various types of non-volatile and volatile memories, such as cache memory, system memory, external storage, removable media, etc.

[0015] Although Figure 1 The system described herein is intended to provide an illustration of a system in which the embodiments described herein can be implemented; however, it should be understood that the described architecture is not limiting and is intended to provide examples of suitable computer systems in which the various techniques disclosed herein can be applied.

[0016] Furthermore, it should be understood that the techniques described herein can be implemented within a circuit arrangement, which typically represents a physical device or system (e.g., one or more integrated circuit devices / chips, cards, boards, components, systems, etc.) incorporating hardware and (in some instances) software configured to implement the techniques described herein. Additionally, it should be understood that implementations utilizing the techniques described herein can be distributed, at least in part, in the form of a program product including logical definition code that defines the circuit arrangement and is stored on a computer-readable medium, and this disclosure applies equally regardless of the specific type of computer-readable medium used to actually perform the distribution. Logical definition program code may include, for example, general gate netlists, composite forms (e.g., described in a hardware description language such as Verilog or VHDL), low-level, physical descriptions (such as GDS11), or other types of program code capable of defining the functionality and / or layout of the manufactured circuit arrangement at different levels of detail. Examples of computer-readable media include, but are not limited to, non-transient, physical, recordable media such as volatile and non-volatile memory devices, floppy disks, hard disk drives, CD-ROMs, and DVDs (etc.).

[0017] about Figure 2 Further details of processor core 22 are shown and described. In one example, the processor is a superscalar processor, which draws from memory (e.g., ... Figure 1 The system memory 14 retrieves instructions and loads them into the processor's instruction ordering logic (ISL) 204. The instruction ordering logic 204 includes, for example, a Level 1 instruction cache (L11 cache) 206, a fetch / decode unit 208, an instruction queue 210, and a dispatch unit 212. In one example, instructions are loaded into the L11 cache 206 of the ISL 204 and are held in the L11 cache 206 until they are requested or replaced if they are not needed. Instructions are retrieved from the L11 cache 206, and in one embodiment, instructions are grouped into instruction sets and decoded by the fetch / decode unit 208 (also referred to herein as the instruction fetch unit 208). After decoding the current instruction, the current instruction is loaded into the instruction queue 210. The dispatch unit 212 dispatches the instruction from the instruction queue 210 to one of a plurality of release queues 222-1…222-N (collectively referred to herein as release queues 222), where N is the total number of release queues. In this example, processor core 22 includes four publish queues 222. However, it should be understood that in other embodiments, more or fewer than four publish queues 222 may be used.

[0018] Each of the issue queues 222 issues a current instruction to one of the execution units 224-1...224-M (collectively referred to herein as execution units 224), where M is the total number of execution units. Issue queue 222 may contain, for example, floating-point type, fixed-point type, and / or load / store instructions. However, it should be understood that any number and type of instructions can be used. For example, the types of instructions may include, but are not limited to, fixed-point arithmetic, matrix multiplication and accumulation (MMA), vector scalar unit (VSU), and load / store (LS) instructions. In this example, processor core 22 includes eight execution units 224 for executing instructions received from issue queue 222. However, it should be understood that in other embodiments, more or fewer than eight execution units 224 may be used. Each execution unit in the execution units 224 may be implemented or configured to execute one or more types of instructions. For example, execution units 224 may include, but are not limited to, matrix multiplication and accumulation (MMA), vector scalar unit (VSU), and load / store (LS) units.

[0019] For example, in one exemplary embodiment, each release queue 222 is bound to a separate vector scalar unit (e.g., execution units 224-1, 224-3, 224-4, and 224-6). Furthermore, in this example, two release queues 222 drive one load / store unit, with a total of two load / store units per core (e.g., execution units 224-2 and 224-5). Similarly, two release queues drive one matrix multiplication and accumulation unit, with a total of two MMA units per core (e.g., execution units 224-7 and 227-M). Additionally, in... Figure 2 In an example embodiment, when operating in a mode known as Simultaneous Multithreading (SMT) 4 mode, processor core 22 can be split into two. In SMT4 mode, core 22 is configured to process two threads per side, with each side having two publish queues, one load / store unit, and one MMA unit per side. In SMT4 mode, each side routes four instructions to at most two publish queues with even and odd half-slices, for a total of four half-slices per side. Figure 2 The segments are labeled as superslice 0 and superslice 1. When running in a mode known as SMT2 mode or single-threaded (ST) mode, core 22 is uniform (i.e., cannot be divided into superslices or edges) and 8 instructions are dispatched to one of 4 release queues in either an even or odd slice, for a total of 8 half-slices.

[0020] Each release queue 222 is also referred to herein as a slice. Furthermore, each release queue 222 has two time slots, referred to herein as even half-slices and odd half-slices, discussed in more detail below. In SMT2 mode, all instructions per cycle (e.g., 8 instructions) are assigned to one of the four release queues 222 in either an even or odd slice, for a total of eight half-slices. In SMT4 mode, each side or superslice routes half of its instructions (e.g., 4 instructions) per cycle to up to two release queues with both even and odd slices, for a total of four half-slices per side or superslice.

[0021] Processor cores with multiple release queues driving multiple execution units utilize a mechanism to distribute dispatched instructions into these release queues. Traditional processor cores typically achieve this by distributing instructions sequentially in instruction order. That is, a conventional processor core dispatches instructions by starting at one release queue and sequentially rounding down the queues one instruction at a time. However, this traditional technique can lead to performance degradation. For example, it's generally known which release queues are full, and those queues are skipped during the round-robin. However, reacting after overfilling release queues is detrimental to performance. For performance purposes, it's desirable to assign an equal workload to each release queue, which is not as simple as distributing the number of instructions equally among all release queues, because all instructions are not equal in terms of the resources they use.

[0022] If instructions are dispatched sequentially as in a traditional system, it's possible for all instructions of the same type (such as VSU or MMA instructions) to enter the same release queue, which provides only one VSU or MMA unit, thus failing to spread the work around for parallel execution. For example, if every fourth instruction is a VSU instruction and these instructions are simply dispatched sequentially, then all VSU instructions will eventually be dispatched to the same release queue, and therefore to the same VSU execution unit. This can create a local bottleneck as a VSU completes and delay the execution of the entire workload.

[0023] In the embodiments described herein, dispatch unit 212 is configured to overcome the performance problems of conventional processor cores by implementing novel dispatch techniques that can be executed efficiently and quickly. Specifically, the circuitry in the processor core executes at very high frequencies. Therefore, the dispatch techniques implemented in dispatch unit 212 are configured to be constructible in high-performance circuitry that enables dispatch unit 212 to quickly determine or select release queue 222 for a given instruction. This allows the dispatch unit to balance the weights or loads on each release queue 222 approximately equally, while still executing such routing fast enough relative to the high execution frequency of the circuitry in processor core 22 to avoid becoming a performance bottleneck.

[0024] At a higher level, dispatch unit 212 is configured to implement two distinct and separate round-robin commands. One round-robin order is associated with an instruction type designated as a priority / optimal instruction type, and the other round-robin order is associated with an instruction type designated as a non-priority / non-optimal instruction type. In some embodiments, the selection of the priority / optimal instruction type may be based on instruction types that may block the release queue (e.g., the instruction type may be determined based on its pipeline length, especially for data dependencies). In some embodiments, the instruction type designated as priority may be selected a priori. Furthermore, in some embodiments, only one instruction type (e.g., MMA, VSU, or L / S) is designated as a priority instruction. In other embodiments, more than one instruction type may be designated as a priority instruction.

[0025] As an example, in some embodiments, the instruction fetch unit 208 receives eight instructions per cycle. In some such embodiments, priority instructions are marked by an 8-bit vector sent from the instruction fetch unit 208, where, for example, 1 indicates a best or priority instruction and 0 indicates a non-best or non-priority instruction. As described in more detail below, the dispatch unit 212 is configured to remember or maintain a tracking queue number for the next round of dispatch for each type of instruction. For example, in some embodiments, a 2-bit latch for four types of instructions is used to maintain a tracking queue number for the next round of dispatch for that type of instruction. Furthermore, in some embodiments, a switch can be used to statically select which type of instruction is designated as best / priority.

[0026] Additionally, in some embodiments, the instruction type designated as a priority instruction can be dynamically changed from cycle to cycle, rather than being statically assigned a priori. In some such embodiments, the instruction fetching unit 208 sends the type of instruction to be prioritized to the dispatching unit 212. For example, in some such embodiments, a hierarchical structure for instruction type priorities is used to assign priority instruction types to a cycle based on the instruction types in a given cycle. For example, in one such embodiment, MMA instructions have the highest priority, followed by VSU instructions, then L / S instructions, and then fixed-point arithmetic. Thus, in this embodiment, if one or more MMA instructions exist in a given cycle, then the MMA instructions are assigned a priority instruction type, while VSU, L / S, and fixed-point arithmetic instructions are considered non-priority instructions. However, if the MMA instructions are not present in a given cycle, but one or more VSU instructions are present in the cycle, then the VSU instructions are assigned the priority instruction type for that cycle, and so on. In some embodiments, this dynamic selection of priority instruction types can be performed in the instruction fetching unit 208 and transmitted to the dispatching unit 212. In some embodiments, the switch can be used to enable / disable dynamic changing of priority instruction types and other functions, such as indicating the selected priority instruction type and forcing rotation, as discussed in more detail below.

[0027] Additionally, in some other embodiments involving dynamically assigning instruction types as priorities, dispatch unit 212, instruction fetch unit 208, or another unit in the processor core is configured to observe workload over a rolling window of previous cycles (e.g., 20 cycles). Based on the observed workload of the previous cycle, an instruction type is selected as the priority instruction type for the next cycle. For example, in some such embodiments, if an MMA instruction type is observed in any of the last 20 cycles, then that MMA instruction type can be selected as the priority instruction type for the next cycle. If no MMA instruction type is observed in the last 20 cycles, a different instruction type (e.g., VSU) can be selected as the priority instruction type for the next cycle. Thus, instead of switching every instruction cycle, the instruction type considered a priority instruction type is switched less periodically (e.g., less periodically) (e.g., after 10 or 20 cycles, depending on the size of the rolling window).

[0028] Given a specified priority instruction type for a given period, dispatch unit 212 is configured to dispatch any priority instruction according to a first rotation order associated with the priority instruction, and to dispatch any other instruction in the period according to a second rotation order associated with non-priority instructions, the second rotation order being different from the first rotation order. Each of the first and second rotation orders is defined for the corresponding direction of rotation through the release queue 222 and the amount of adjustment for rotation, as follows regarding... Figure 3 and 4 For more detailed description. In some embodiments, dispatch unit 212 may include different logic gates to determine where to dispatch instructions based on different received bits and switches, as described herein.

[0029] Figure 3 This is a partial view of one embodiment of processor core 22, depicting only the dispatch unit 212 and the issue queue 222. Specifically, Figure 3 One implementation of dispatching instructions to publish queue 222 within a single cycle is described. Figure 3 In the example shown, the cycle includes eight instructions (labeled i0 to i7) received at dispatch unit 212 from instruction fetch unit 208. In this example, instructions i0 and i1 have instruction types specifying the priority instruction type used for this cycle. In this example, instructions i2 to i7 have instruction types specified as non-priority instructions. In some embodiments, dispatch unit 212 is configured to determine the instruction type of each instruction in the cycle based on information sent from instruction fetch unit 208. For example, instruction fetch unit 208 may set one or more bits to be sent along with the decoded instruction. In other embodiments, dispatch unit 212 uses different techniques to determine the instruction type of each instruction.

[0030] In this embodiment, due to the architecture of processor core 22, instructions are sequentially dispatched from i0 to i7. That is, to dispatch instruction i1, instruction i0 must be dispatched first, and so on. Since instructions i0 and i1 are designated as priority instructions in this example, a first round-robin order is selected for dispatching instructions i0 and i1, while a second round-robin order is selected for dispatching instructions i2 to i7. The first and second round-robin orders can be described relative to the number of slices and the number of half-slices. For example, release queues 222-1, 222-2, 222-3, and 222-N are also referred to as slice 0 (S0), slice 1 (S1), slice 2 (S2), and slice 3 (S3), respectively. In addition, as discussed above, each release queue has 2 time slots or half-slices. The time slots or half-slices are sequentially labeled as 0, 1, 2, 3, 4, 5, 6, and 7. Each release queue has an even number of half-slices (0, 2, 4, or 6) and an odd number of half-slices (1, 3, 5, or 7).

[0031] In this embodiment, the first rotation order specifies a slice order of 0-2-1-3. Therefore, the first rotation order starts with slice 0 (release queue 222-1) for the first priority instruction, then rotates to slice 2 (release queue 222-3) for the next priority instruction, then to slice 1 (release queue 222-2) for the next priority instruction, and then to slice 3 (release queue 222-N) for the next priority instruction. If there are more than four priority instructions, the first rotation order starts at slice 0. In this example, the second rotation order for non-priority instructions specifies a slice order of 3-1-2-0. Therefore, the second rotation order starts with slice 3 (release queue 222-N) for the first non-priority instruction, then rotates to slice 1 (release queue 222-2) for the next non-priority instruction, then to slice 2 (release queue 222-3) for the next non-priority instruction, and then to slice 0 (release queue 222-1) for the next non-priority instruction. If there are more than 4 non-priority instructions, then the second rotation order starts at slice 3.

[0032] As can be seen, the first and second rotation sequences each define a starting point and the rotation direction and amount (e.g., rotation direction and amount) for each rotation. For example, rotating two slices to the right, rotating one slice to the left, etc. Specifically, the starting point, rotation direction, and rotation amount defined by the second rotation sequence are substantially opposite to those defined by the first rotation sequence. Additionally, in this example, the dispatch unit is configured to first select an even-numbered half-slice for each slice in a given period, and then select an odd-numbered half-slice for each slice. For example, the first instruction (whether priority or non-priority) dispatched to slice 0 (dispatch queue 222-1) is dispatched to half-slice or slot 0. Similarly, when the instruction (whether priority or non-priority) is first dispatched to other slices, it is dispatched to an even-numbered half-slice (i.e., 2, 4, or 6). The next time an instruction (whether priority or non-priority) is assigned to slice 0 (or one of the other slices), subsequent instructions will be assigned to odd-numbered half-slices (i.e., 1, 3, 5, or 7).

[0033] Thus, dispatch unit 212 is configured to track or remember which point in the first and second rotation order of each subsequent instruction dispatch unit 212 uses for that slice, and whether an even or odd half-slice is used for that slice. Additionally, in some embodiments, dispatch unit 212 remembers the point in both the first and second rotation order across each cycle. That is, instead of resetting the first and second rotation commands at the beginning of each cycle, dispatch unit 212 remembers where it is at the end and beginning of each cycle in each of the first and second rotation commands. For example, if at the end of a given cycle, dispatch unit dispatches a priority instruction to slice 2, then using the example rotation discussed above, the next priority instruction in a subsequent cycle will then be sent to slice 1. Additionally, in some embodiments, dispatch unit 212 tracks the last half-slice used for each slice across cycles, as described above. For example, dispatch unit 212 may track whether the last instruction sent to slice 1 is an odd or even half-slice, such that the next subsequent instruction sent to slice 1 (whether in the same cycle or a subsequent cycle) will be sent to the other half-slice on slice 1.

[0034] In addition to tracking the last release queues used for priority and non-priority rotation orders, in some embodiments, dispatch unit 212 is configured to track the last release queue for each instruction type. Thus, in embodiments with four different instruction types, dispatch unit 212 is configured to track the last release queue for each of the four different instruction types. In embodiments involving dynamically selecting priority instruction types, for example, at the beginning of each instruction cycle, dispatch unit 212 adjusts the start of the priority rotation order based on the last release queue of the instruction type selected as the priority instruction type for that instruction cycle. Specifically, dispatch unit 212 sets the first or starting release queue for the priority rotation order of that instruction cycle as the next release queue after the last release queue for the priority instruction type in the priority rotation order. The non-priority rotation order is then adjusted to be the reverse of the priority rotation order. In other words, the starting release queue in the non-priority release queue is the opposite of the starting release queue in the priority rotation order.

[0035] In some embodiments, dispatch unit 212 uses a 2-bit encoded or 4-bit decoded value to track which publish queue is next for each of the first and second round-robin sequences. For example, the next round number can be picked from a previous round-robin state latch, and this can be extended to a 4-bit quadrature signal that rounds one bit to the right after each priority instruction. A converse 4-bit quadrature signal is used for non-priority instructions and rounds one bit to the left after each non-priority instruction. Thus, each instruction is checked sequentially, and priority instructions receive the best round, while non-priority instructions round in the opposite direction, starting from the last selection of the priority instructions. In this way, dispatch unit 212 can track its current position in each of the first and second round-robin commands.

[0036] Therefore, by using two separate round-robin orders for priority and non-priority instructions and remembering the last half-slice used, dispatch unit 212 can ensure that the workload is distributed more evenly across the issue queue 222 than in conventional processor cores. For example, in a conventional processor, if instructions requiring more resources occur in every fourth instruction, those more resource-intensive instructions will be dispatched to the same queue, leading to an imbalance in workload distribution across execution loads and resulting in performance degradation. Conversely, in the same case using the implementation described herein, more resource-intensive instructions can be marked as priority instructions and dispatched in a different manner than non-priority instructions. Therefore, in embodiments using the round-robin order described herein, more resource-intensive instructions (and less resource-intensive instructions) will be more evenly distributed across the issue queue and thus across the execution units, resulting in performance improvements compared to conventional processors.

[0037] For example, in Figure 3In the illustrated embodiment, instructions i0 and i1 are designated as priority instructions based on, for example, instruction type (e.g., higher resource-intensive instructions). Thus, instructions i0 and i1 are assigned according to a first round-robin order. In this particular example, instruction i0 is assigned to slice 0 (release queue 222-1). Because this is the first instruction assigned to slice 0, instruction i0 is moved to half-slice 0. Then, instruction i1 is assigned to slice 2 (release queue 222-3). Again, because this is the first instruction assigned to slice 2, instruction i1 is moved to even half-slice 4. Instructions i2 through i7 are designated as non-priority instructions (e.g., lower resource-intensive compared to priority instructions) and are therefore assigned according to a second round-robin order. Specifically, instruction i2 is assigned to slice 3 (release queue 222-N). Since this is the first instruction assigned to slice 3, instruction i2 is moved to half-slice 6. Instruction i3 is even moved to half-slice 3 (release queue 222-1) within slice 1, because it is the first instruction assigned to slice 1. Instruction i4 is assigned to odd half-slice 5 in slice 2 (issue queue 222-3) because it is the second instruction assigned to slice 2. Instruction i5 is assigned to odd half-slice 1 in slice 0 because it is the second instruction assigned to slice 0. The second round of rotation then begins at slice 3, and dispatch unit 212 assigns instruction i6 to odd half-slice 7 in slice 3, and then assigns instruction i7 to odd half-slice 3 in slice 1.

[0038] In the next cycle, if instructions i0 and i1 are also priority instructions, then instruction i0 is assigned to slice 1 and instruction i1 is assigned to slice 3. Therefore, it can be seen that priority instructions are assigned to different issue queues and evenly distributed across issue queue 222 for more parallel execution. Furthermore, the example round-robin order enables both 4-way and 2-way round-robin execution. For example, in the example processor core 22, there are 2 MMA execution units. Thus, the round-robin execution of MMA instructions is 2-way round-robin. However, in... Figure 2 In the example, there are 4 VSU execution units, so the VSU instruction rotation is a 4-way rotation. However, as described above, the first and second rotation sequences are each configured to switch between superslice 0 (SS0) and superslice 1 (SS1) on each shift or rotation. Therefore, the 4-way rotation supports 2-way rotation because the instructions alternate between the two superslices. Furthermore, the embodiments described herein support SMT4, SMT2, and ST modes, as discussed above. Specifically, by ensuring that each rotation or switch causes the superslice to alternate, the first and second rotation sequences can support embodiments with 1 or 2 superslices. In this way, the embodiments described herein can support SMT4, SMT2, and ST modes.

[0039] Furthermore, in SMT4 mode, processor core 22 is divided into two, thus there are only two possible choices for each side of the release queue. That is, multiple release queues are divided into two groups that operate independently of each other. Each of the two groups can have a corresponding first round order for priority / resource-intensive instructions and a corresponding second round order for non-priority / non-resource-intensive instructions. Additionally, in some embodiments, instructions are divided between the two sides. For example, instructions i0-i3 can be assigned to superslice 0, and instructions i4-i7 can be assigned to superslice 1. This can be indicated by 1 bit, although information on the possible instruction types (e.g., up to 4 instruction types) for each group can be tracked on both half-cores. Thus, in some such embodiments, a total of 8 instruction types are tracked: 4 types of instructions on superslice 0 and 4 types of instructions on superslice 1. For each superslice or half-core, 1 bit is passed for the round of the optimal / priority instruction type, and a separate 1 bit is passed for the round of the non-optimal / non-priority instructions. The non-optimal round starts in the opposite manner to the starting value of the optimal round. Each of the four instructions on one side is rotated sequentially using either optimal or non-optimal rotation signals, and the appropriate signal is toggled for each case of that type of instruction on each superslice. Thus, in some embodiments, each superslice may have a different priority instruction type (e.g., MMA on superslice 0 and VSU on superslice 1).

[0040] Furthermore, in some embodiments, the dispatch unit 212 is configured to take into account busy publish queues. For example, in Figure 3In this implementation, there are 8 instructions and 4 release queues, each with 2 half-slices. Some release queues may be busy. If no busy release queues exist, instruction dispatch is a simple choice between each of the two round-robin sequences. In some embodiments, if some busy release queues exist, dispatch unit 212 implements sequential dependencies on the earliest instruction within the 8-instruction group. For example, in some embodiments, to obtain cycle time, dispatch unit 212 chooses to dispatch only 4 instructions when some busy release queues 222 exist; otherwise, an 8-instruction dependency chain exists. Furthermore, in some embodiments, if the release queue pointed to by the round-robin vector / round-robin sequence is busy, the next one in the round is checked, then the next one after that, and so on. In some embodiments, if all the remaining release queues are busy, the instruction and all newer instructions in the group are not dispatched. The processing of busy release queues / slices 222 can depend on the operating mode. For example, in some embodiments operating in SMT2 or ST mode, when one or more slices are busy, dispatch unit 212 may be configured to dispatch instructions in pairs rather than individually, and to dispatch all instructions in fewer cycles (e.g., 4 instead of 8). In some embodiments operating in SMT4 mode, when one or more slices are busy, dispatch unit 212 may be configured to dispatch any instruction to any half-slice for each superslice, even prioritizing even-numbered half-slices.

[0041] Furthermore, in some other embodiments, dispatch unit 212 is configured to force a rotation order instead of checking the next publication queue in the rotation if the publication queue pointed to by the rotation vector / rotation command is busy. In some such embodiments, a switch is used to force rotation based on the instruction type. For example, when the force rotation switch is set high, only the selected rotation publication queue pointed to by the rotation vector / rotation order is checked to see if it is not busy. If the indicated publication queue is unavailable, dispatch unit 212 stops until the indicated publication queue becomes available. In some implementations, the selection of forced rotation depends on the instruction type, as described above. For example, in some embodiments, MMA instructions are selected to always enable the forced rotation signal, while other instruction types are not selected to enable the forced rotation signal. Because some instruction types, such as MMA instructions, can run for relatively long periods, performance can sometimes be improved by waiting for the indicated publication queue rather than publishing long-running instructions to different publication queues earlier. Furthermore, in some embodiments, a runnable time limit is used to limit the amount of time dispatch unit 212 waits for a busy publication queue to become available. In some embodiments, the runtime availability can be measured, for example, in terms of periods or actual elapsed time. In such embodiments using runtime availability, if the timeout is reached and the indicated publishing queue is still busy, the dispatch unit 212 moves to the next publishing queue in rotation order.

[0042] It should be understood that the above regarding Figure 3 The example first and second rotation orders discussed are provided by way of example only, and other rotation orders may be used in other embodiments. For example, in another embodiment, the first rotation order specifies a slice order of 1-3-0-2, and the second rotation order specifies a slice order of 2-0-3-1. Furthermore, in some embodiments, dispatch unit 212 is configured to first dispatch instructions to the odd-numbered half-segments of each release queue 222, and then to the even-numbered half-segments. Additionally, in other embodiments, dispatch unit 212 may be configured to reset one or both of the first and second rotation orders for each cycle. It should also be understood that the number and order of priority and non-priority instructions discussed herein are presented by way of example only, and the number and order of priority and non-priority instructions may differ for each cycle and embodiment. Specifically, it should be understood that all priority instructions are not necessarily consecutive or the first instruction in a cycle.

[0043] Furthermore, in some embodiments, the dispatch unit 212 is configured to dispatch paired instructions, such as those concerning... Figure 4 The subject of discussion. Specifically, in Figure 4 In the example shown, instructions i0 and i1 are a pair of instructions. As used herein, a pair of instructions refers to instructions to be executed by the same execution unit. Accordingly, dispatch unit 212 is configured to dispatch the paired instructions to the same release queue 222. Furthermore, in this example, instructions i0, i1, and i2 are designated as non-priority instructions, and instructions i3 through i7 are designated as priority instructions. None of instructions i2 through i7 are a pair of instructions. However, in this example, dispatch unit 212 is configured to adapt the dispatch of instructions i0 through i7 to consider the paired instructions i0 and i1. Specifically, dispatch unit 212 is configured to dispatch all instructions i0 through i7 in pairs, even if only instructions i0 and i1 are considered a pair of instructions.

[0044] For example, in this embodiment, instructions i0 and i1 are a pair of non-priority instructions. Therefore, instructions i0 and i1 are assigned according to a second routing order associated with the non-priority instructions. Figure 4In the example, the second routing instruction begins at slice 3. Thus, instruction i0 is assigned to the even-numbered half-slice 6 of slice 3, and instruction i1 is assigned to the odd-numbered half-slice 7 of slice 3. Instructions i2 and i3 are also assigned together as a pair. In this example, instruction i2 is a non-priority instruction and instruction i3 is a priority instruction. Therefore, in this example, the first routing order associated with the priority instructions is used to assign instructions i2 and i3. Thus, instruction i2 is assigned to the even-numbered half-slice 0 of slice 0, and instruction i3 is assigned to the odd-numbered half-slice 1 of slice 0. However, in other embodiments, when one of the two instructions assigned as a pair is a non-priority instruction, the instruction pair can be assigned according to the second routing order associated with the non-priority instruction. In such an embodiment, for example, instruction i2 is assigned to the even-numbered half-slice 2 of slice 1, and instruction i3 is assigned to the odd-numbered half-slice 3 of slice 1.

[0045] Instructions i4 and i5 are priority instructions and are dispatched according to the first routing order. Therefore, in this example, instruction i4 is dispatched to the even-numbered half-slice 4 of slice 2, and instruction i5 is dispatched to the odd-numbered half-slice 5 of slice 2. Finally, instructions i6 and i7 are priority instructions and are dispatched as a pair according to the first routing order. In this example, instruction i6 is dispatched to the even-numbered half-slice 2 of slice 1, and instruction i7 is dispatched to the odd-numbered half-slice 3 of slice 1. Therefore, Figure 4 The pairwise patterns shown are used for dispatching instructions. Figure 3 Similar to the standalone mode, because it uses two separate dispatch orders for priority instructions and non-priority instructions. However, with Figure 3 In contrast, as mentioned above, when alternating even and odd half-slices, instructions are assigned in pairs to the even and odd half-slices of the same slice, rather than to one slice individually.

[0046] Figure 5 This is a flowchart depicting one embodiment of an example method 500 for dispatching instructions. Method 500 can be implemented by a dispatch unit of the processor core (e.g., dispatch unit 212 discussed above). It should be understood that, for illustrative purposes, the order of actions in example method 500 is provided, and in other embodiments, the method may be executed in a different order. Similarly, it should be understood that some actions may be omitted or additional actions may be included in other embodiments.

[0047] At 502, instructions for dispatching to one of multiple release queues are received. For example, in each cycle, multiple instructions can be received from the instruction fetching unit, as described above. One or more instructions in each cycle can be designated as priority or optimal instructions. As described above, priority or optimal instructions are designated as resource-intensive instructions. Therefore, instruction types not designated as resource-intensive for a given instruction cycle are designated as non-priority or non-resource-intensive instructions.

[0048] At 504, the priority state of the instruction is determined. As described above, this designation or priority state can be based on the instruction type. Additionally, in some embodiments, as discussed above, the priority state of each instruction can be indicated by bits in a vector received from the instruction fetch unit. Furthermore, as discussed above, the instruction type designated as priority or resource-intensive can be determined, for example, dynamically from cycle to cycle by the instruction fetch unit. Furthermore, the instruction type designated as priority or resource-intensive can be determined based on historical data of instruction types assigned in previous cycles, as discussed above. It should be understood that designation as resource-intensive or non-resource-intensive is relative to the relative resource requirements of the instruction type in a given instruction cycle. For example, in one instruction cycle, a VSU instruction type can be designated as a priority or resource-intensive instruction type compared to a fixed arithmetic instruction in the same instruction cycle. However, in another instruction cycle, a VSU instruction can be designated as non-resource-intensive compared to an MMA instruction designated as resource-intensive for that instruction cycle. Therefore, the designation as resource-intensive or non-resource-intensive is not an absolute designation of the specific amount of resources required, but a relative designation relative to the expected resource requirements of other instructions in the instruction cycle based on the corresponding instruction type.

[0049] At point 506, a rotation order based on priority status is selected. Specifically, as discussed above, the first rotation order is associated with priority instructions, and a second rotation order, different from the first, is associated with non-priority instructions. The second rotation order can be the reverse of the first. For example, as described above, the dispatch unit can track the last rotation or issue queue for each instruction type. For example, the last rotation or issue queue for VSU instructions could be... Figure 3 The release queue 222-2 (slice S1) is selected, and the VSU instruction is chosen as the priority instruction type for the current instruction cycle. Thus, at the beginning of the current instruction cycle, the first round order associated with the priority instruction is advanced to begin in the next round or release queue after the last round for the VSU instruction according to the first round order. For example, if the last round for the current priority instruction type is slice S1 (release queue 222-2), then according to the above... Figure 3In the example rotation order discussed, the first rotation order of the current instruction cycle is advanced to begin with slice S3 (issue queue 222-N). Thus, the first rotation order of this instruction cycle will follow a slice order of 3-0-2-1. At the beginning of the current instruction cycle, a second rotation order for non-priority instruction types is then selected, in reverse to the first rotation order. Thus, in the example described here, the second rotation order will follow a slice order of 1-2-0-3. During the instruction cycle, each instruction is dispatched according to one of the two rotation orders, as discussed above. After each corresponding instruction, only the rotation order corresponding to that instruction is updated. For example, if a given instruction is dispatched according to the first rotation order during the instruction cycle, then only the first rotation order is updated. Similarly, if a given instruction is dispatched according to the second rotation order during the instruction cycle, then only the second rotation order is updated.

[0050] At 508, a release queue is selected from multiple release queues based on the selected rotation order, as discussed above. Additionally, as mentioned above, in some embodiments, each release queue has two time slots. In such embodiments, selecting a release queue includes selecting both the release queue and the time slot based on the selected rotation order. At 510, an instruction is dispatched to the selected release queue. Method 500 then returns to 502 for the next instruction in the instruction cycle. In some embodiments, dispatching an instruction to the selected release queue includes: determining that the selected release queue is busy, and waiting for the selected release queue to become available in response to determining that the selected release queue is busy, as shown, for example, regarding... Figure 7 The illustrative embodiments described herein. In other embodiments, dispatching instructions to a selected release queue includes: in response to determining that the selected release queue is busy, selecting a next release queue based on a selected round-robin order, and dispatching instructions to the next release queue, as exemplified by [example description of the next release queue]. Figure 6 The illustrative embodiments described herein.

[0051] Figure 6 This is a flowchart depicting another embodiment of an exemplary method 600 for dispatching instructions. Method 600 may be implemented by a dispatch unit of a processor core (e.g., dispatch unit 612 discussed above). It should be understood that, for illustrative purposes, the order of actions in example method 600 is provided, and in other embodiments, the method may be performed in a different order. Similarly, it should be understood that some actions may be omitted or additional actions may be included in other embodiments.

[0052] At 602, an instruction for assignment to one of multiple release queues is received. For example, multiple instructions may be received from the instruction fetching unit in each cycle, as described above. One or more instructions in each cycle may be designated as priority or optimal instructions. As described above, priority or optimal instructions are those designated as resource-intensive. At 604, the priority state of the instruction is determined. As described above, this designation or priority state may be based on the instruction type. Additionally, in some embodiments, as discussed above, the priority state of each instruction may be indicated by bits in a vector received from the instruction fetching unit. Furthermore, as discussed above, the instruction type designated as priority or resource-intensive may be determined, for example, dynamically by the instruction fetching unit from cycle to cycle. Furthermore, the instruction type designated as priority or resource-intensive may be determined based on historical data of instruction types assigned in previous cycles, as discussed above.

[0053] At point 606, a rotation order based on priority status is selected. Specifically, as discussed above, the first rotation order is associated with priority instructions, and a second rotation order, different from the first, is associated with non-priority instructions. The second rotation order can be the reverse of the first. For example, as mentioned above, the dispatch unit can track the last rotation or issue queue for each instruction type. For example, the last rotation or issue queue for MMA instructions could be... Figure 3 In the example, the release queue is 222-3 (slice S2), and the MMA instruction is selected as the priority instruction type for the current instruction cycle. Therefore, at the beginning of the current instruction cycle, the first round order associated with the priority instruction is advanced to begin in the next round or release queue after the last round used for the MMA instruction according to the first round order. For example, if the last round used for the current priority instruction type is slice S2 (release queue 222-3), then according to the above... Figure 3 In the example rotation order discussed, the first rotation order of the current instruction cycle is advanced to begin with slice S1 (issue queue 222-2). Thus, the first rotation order of this instruction cycle will follow a slice order of 1-3-0-2. At the beginning of the current instruction cycle, a second rotation order for non-priority instruction types is then selected, in reverse to the first rotation order. Thus, in the example described here, the second rotation order will follow a slice order of 2-0-3-1. During the instruction cycle, each instruction is dispatched according to one of the two rotation orders, as discussed above. After each corresponding instruction, only the rotation order corresponding to that instruction is updated. For example, if a given instruction is dispatched according to the first rotation order during the instruction cycle, then only the first rotation order is updated. Similarly, if a given instruction is dispatched according to the second rotation order during the instruction cycle, then only the second rotation order is updated.

[0054] At 608, a release queue is selected from multiple release queues based on the selected rotation order, as discussed above. Additionally, as mentioned above, in some embodiments, each release queue has two time slots. In such embodiments, selecting a release queue involves selecting both the release queue and the time slot based on the selected rotation order. At 610, it is determined whether the selected release queue is busy or otherwise unavailable. If the selected release queue is not busy, instructions are dispatched to the selected release queue at 612.

[0055] In some embodiments, if the selected release queue is busy, it is determined at block 614 that there are additional release queues to be checked. In other words, at block 614, it is determined whether all release queues have been checked to determine if there are any available release queues. In some embodiments, if there are no more release queues to be checked, method 600 stops dispatching instructions for that instruction cycle at block 616. If there are one or more release queues to be checked, method 600 returns to block 608, where the next release queue in the selected rotation order is selected. If the next release queue in the rotation selected at block 610 is not busy, the instruction is dispatched to the next release queue at block 612, and method 600 returns to 602 for the next instruction in the cycle.

[0056] Figure 7 This is a flowchart depicting another embodiment of an exemplary method 700 for dispatching instructions. Method 700 may be implemented by a dispatch unit of a processor core (e.g., dispatch unit 712 discussed above). It should be understood that, for illustrative purposes, the order of actions in example method 700 is provided, and in other embodiments, the method may be performed in a different order. Similarly, it should be understood that some actions may be omitted or additional actions may be included in other embodiments.

[0057] At 702, an instruction for assignment to one of multiple release queues is received. For example, multiple instructions may be received from the instruction fetching unit in each cycle, as described above. One or more instructions in each cycle may be designated as priority or optimal instructions. As described above, priority or optimal instructions are those designated as resource-intensive. At 704, the priority state of the instruction is determined. As described above, this designation or priority state may be based on the instruction type. Additionally, in some embodiments, as discussed above, the priority state of each instruction may be indicated by bits in a vector received from the instruction fetching unit. Furthermore, as discussed above, the instruction type designated as priority or resource-intensive may be determined, for example, dynamically by the instruction fetching unit from cycle to cycle. Furthermore, the instruction type designated as priority or resource-intensive may be determined based on historical data of instruction types assigned in previous cycles, as discussed above.

[0058] At point 706, a rotation order based on priority status is selected. Specifically, as discussed above, the first rotation order is associated with priority instructions, and the second rotation order, different from the first, is associated with non-priority instructions. The second rotation order can be the reverse of the first. For example, as mentioned above, the dispatch unit can track the last rotation or issue queue for each instruction type. For example, the last rotation or issue queue for L / S instructions could be... Figure 3 The release queue 222-1 (slice S0) is selected, and the L / S instruction is chosen as the priority instruction type for the current instruction cycle. Thus, at the beginning of the current instruction cycle, the first round order associated with the priority instruction is advanced to begin in the next round or release queue after the last round for the L / S instruction according to the first round order. For example, if the last round for the current priority instruction type is slice S0 (release queue 222-1), then according to the above... Figure 3 In the example rotation order discussed, the first rotation order of the current instruction cycle is advanced to begin with slice S2 (issue queue 222-3). Thus, the first rotation order of this instruction cycle will follow a slice order of 2-1-3-0. At the beginning of the current instruction cycle, a second rotation order for non-priority instruction types is then selected, in reverse to the first rotation order. Thus, in the example described here, the second rotation order will follow a slice order of 0-3-1-2. During the instruction cycle, each instruction is dispatched according to one of the two rotation orders, as discussed above. After each corresponding instruction, only the rotation order corresponding to that instruction is updated. For example, if a given instruction is dispatched according to the first rotation order during the instruction cycle, then only the first rotation order is updated. Similarly, if a given instruction is dispatched according to the second rotation order during the instruction cycle, then only the second rotation order is updated.

[0059] At 708, a release queue is selected from multiple release queues based on the selected rotation order, as discussed above. Additionally, as mentioned above, in some embodiments, each release queue has two time slots. In such embodiments, selecting a release queue involves selecting both the release queue and the time slot based on the selected rotation order. At 710, it is determined whether the selected release queue is busy or otherwise unavailable. If the selected release queue is not busy, instructions are dispatched to the selected release queue at 712.

[0060] If the selected release queue is busy, it is determined at block 714 whether forced rotation for a given instruction type is enabled. For example, a bit can be set to indicate that forced rotation should be enabled for a given instruction type, as discussed above. If forced rotation is enabled at block 714, the dispatch unit waits at block 716 until the selected release queue becomes available. As described above, in some embodiments, a timeout can be applied to limit the amount of time the dispatch unit waits for the selected release queue. Once the selected release queue becomes available, the instruction is dispatched to the selected release queue at block 712. If forced rotation is disabled for a given instruction type at block 714, method 700 returns to block 708, where the next release queue in the selected rotation order is selected, and method 700 continues to block 710 to determine if the next release queue in the rotation order is busy. If the next release queue is not busy, the instruction is dispatched to the next release queue at block 714. Method 700 then returns to 702 for the next instruction in the instruction cycle.

[0061] Therefore, using the techniques described herein, each of a plurality of instructions in a cycle is dispatched using one of two different round-robin orders based on the priority state of the respective instruction. Specifically, according to a first round-robin order, each of one or more instructions designated as resource-intensive or priority is dispatched to a corresponding one of a plurality of release queues, and according to a second round-robin order, each of one or more instructions designated as non-resource-intensive or non-priority is dispatched to a corresponding one of a plurality of release queues. As discussed herein, dispatching instructions using two different round-robin orders of priority and non-priority instructions improves the processor core's ability to distribute workload evenly among release queues and execution units, resulting in improved performance compared to conventional processors and systems. Example Implementation

[0062] Example 1 includes a method comprising: receiving instructions for dispatching to a plurality of publication queues; determining a priority state of the instructions; selecting a rotation order based on the priority state, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting a publication queue from the plurality of publication queues based on the selected rotation order; and dispatching the instructions to the selected publication queue.

[0063] Example 2 includes the method of Example 1, wherein determining the priority state of an instruction includes checking the bits corresponding to the instruction in a vector received from the instruction fetching unit.

[0064] Example 3 includes a method from any of Examples 1-2, wherein determining the priority state of an instruction is based on the instruction type of the instruction, wherein one instruction type is designated as priority and at least one instruction type is designated as non-priority; wherein the first rotation order is adjusted to begin at the next release queue after the last used release queue of the instruction type designated as priority in the first rotation order; and wherein the second rotation order is adjusted to be the reverse of the first rotation order.

[0065] Example 4 includes the method of Example 3, wherein the instruction type assigned as priority is dynamically determined from period to period.

[0066] Example 5 includes any of the methods in Examples 3-4, which determines the instruction type to be assigned priority based on historical data of instruction types dispatched in previous cycles.

[0067] Example 6 includes a method from any of Examples 1-5, wherein each release queue has 2 time slots; and wherein selecting a release queue includes selecting the release queue and time slot based on the selected rotation order.

[0068] Example 7 includes a method from any of Examples 1-6, wherein dispatching instructions to a selected release queue further includes: determining that the selected release queue is busy; and, in response to determining that the selected release queue is busy, waiting for the selected release queue to become available.

[0069] Example 8 includes a method of any of Examples 1-7, wherein dispatching an instruction to a selected release queue further includes: determining that the selected release queue is busy; in response to determining that the selected release queue is busy, selecting a next release queue based on the selected rotation order; and dispatching the instruction to the next release queue.

[0070] Example 9 includes a method comprising: receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; assigning each of the one or more instructions designated as resource-intensive to a corresponding one of a plurality of release queues according to a first rotation order; and assigning each of the one or more instructions designated as non-resource-intensive to a corresponding release queue of the plurality of release queues according to a second rotation order opposite to the first rotation order.

[0071] Example 10 includes the method of Example 9, and also includes tracking the position in the first rotation sequence and the position in the second rotation sequence for use in subsequent cycles.

[0072] Example 11 includes any of the methods in Examples 9-10, wherein a plurality of release queues are divided into a first group and a second group that operates independently of the first group; and wherein each of the first group and the second group is associated with a corresponding first round-robin order for resource-intensive instructions and a corresponding second round-robin order for non-resource-intensive instructions.

[0073] Example 12 includes a method of any one of Examples 9-11, wherein at least two of the plurality of instructions are paired instructions; wherein the method further includes pairing each of the unpaired instructions with another unpaired instruction; and wherein dispatching each of the one or more instructions designated as resource-intensive includes dispatching each of the one or more instructions designated as resource-intensive together with another of the plurality of instructions according to a first rounding order; and wherein dispatching each of the one or more instructions designated as non-resource-intensive includes dispatching each of the one or more instructions designated as paired with another non-resource-intensive instruction according to a second rounding order.

[0074] Example 13 includes a processor comprising an instruction fetch unit; a dispatch unit communicatively coupled to the instruction fetch unit; and a plurality of release queues communicatively coupled to the dispatch unit. The dispatch unit is configured to: receive a plurality of instructions from the instruction fetch unit; determine a corresponding priority state for each of the plurality of instructions; select a round-robin order for each of the plurality of instructions based on the corresponding priority state, wherein a first round-robin order is associated with priority instructions, and a second round-robin order different from the first round-robin order is associated with non-priority instructions; select a corresponding release queue from the plurality of release queues for each of the plurality of instructions based on the corresponding selected round-robin order; and dispatch each of the plurality of instructions to the corresponding selected release queue.

[0075] Example 14 includes the processor of Example 13, wherein the dispatch unit is configured to determine the priority state of each of a plurality of instructions by examining the bits corresponding to each instruction in a vector received from the instruction fetch unit.

[0076] Example 15 includes a processor of any of Examples 13-14, wherein the instruction fetch unit is configured to determine the appropriate priority state of each instruction based on the appropriate instruction type of each instruction.

[0077] Example 16 includes a processor of any of the examples 13-15, wherein the instruction fetch unit is configured to dynamically determine the instruction type assigned as priority from cycle to cycle.

[0078] Example 17 includes any of the processors in Examples 13-16, wherein the instruction fetch unit is configured to determine the instruction type assigned a priority based on historical data of instruction types dispatched in previous cycles.

[0079] Example 18 includes a processor of any of Examples 13-17, wherein each of a plurality of release queues has 2 time slots; and wherein selecting the appropriate release queue among the plurality of release queues for each of a plurality of instructions includes selecting the appropriate release queue and time slot based on the rotation order of the appropriate selection.

[0080] Example 19 includes a processor of any of Examples 13-18, wherein the dispatch unit is further configured to determine that the appropriate selection of the release queue for a given instruction among a plurality of instructions is busy, and to wait to dispatch the given instruction among the plurality of instructions until the appropriate selection of the release queue becomes available.

[0081] Example 20 includes a processor of any of Examples 13-19, wherein the dispatch unit is further configured to: determine that the corresponding selection of the release queue for a given instruction among a plurality of instructions is busy; in response to determining that the corresponding selection of the release queue is busy, select the next release queue based on the round-robin order of the corresponding selection; and dispatch the given instruction among the plurality of instructions to the next release queue.

[0082] Example 21 includes a computer system comprising a memory configured to store program code; and a processor communicatively coupled to the memory and configured to execute the program code. The processor includes an instruction fetch unit; a dispatch unit communicatively coupled to the instruction fetch unit; and a plurality of dispatch queues communicatively coupled to the dispatch unit. The dispatch unit is configured to receive, in a cycle, a plurality of instructions, including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; dispatch each of the one or more resource-intensive instructions to a corresponding one of the plurality of dispatch queues according to a first round-robin order; and dispatch each of the one or more non-resource-intensive instructions to a corresponding one of the plurality of dispatch queues according to a second round-robin order opposite to the first round-robin order.

[0083] Example 22 includes the computer system of Example 21, wherein the dispatching unit is further configured to track positions in a first rotation sequence and positions in a second rotation sequence for use in subsequent cycles.

[0084] Example 23 includes any of the computer systems in Examples 21-22, wherein a plurality of release queues are divided into a first group and a second group that operates independently of the first group; and wherein each of the first group and the second group is associated with a corresponding first round order for resource-intensive instructions and a corresponding second round order for non-resource-intensive instructions.

[0085] Example 24 includes a computer system of any one of Examples 21-23, wherein at least two of the plurality of instructions are paired instructions; wherein the dispatch unit is further configured to dispatch the plurality of instructions in pairs, such that each of the one or more instructions designated as resource-intensive is dispatched together with another instruction of the plurality of instructions according to a first rotation order, and each of the one or more instructions designated as non-resource-intensive is dispatched in pairs with another instruction designated as non-resource-intensive according to a second rotation order.

[0086] Example 25 includes any of the computer systems in Examples 21-24, wherein the instruction fetching unit is configured to dynamically determine the instruction type designated as resource-intensive for each cycle.

[0087] While specific embodiments have been shown and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. Therefore, this disclosure is clearly intended to be limited only by the claims and their equivalents.

Claims

1. A method for instruction dispatch, comprising: Receive instructions for dispatching to one of multiple publish queues; Determine the resource intensity of the instruction; The rotation order is selected based on the resource intensity, wherein the first rotation order is associated with instructions designated as resource intensive, and the second rotation order, which is different from the first rotation order, is associated with instructions designated as non-resource intensive. One of the multiple publishing queues is selected based on the chosen rotation order; and The instruction is dispatched to the selected release queue.

2. The method according to claim 1, wherein, The instruction type designated as resource-intensive is dynamically determined from periodic to periodic.

3. The method according to claim 1, wherein, Each release queue has 2 time slots; and Selecting the release queue includes selecting the release queue and time slot based on the selected rotation order.

4. The method according to claim 1, wherein, Dispatching the instruction to the selected release queue further includes: Determine if the selected publish queue is busy; and In response to determining that the selected release queue is busy, wait for the selected release queue to become available.

5. The method according to claim 1, wherein, Dispatching the instruction to the selected release queue further includes: Determine if the selected publish queue is busy; In response to determining that the selected release queue is busy, the next release queue is selected based on the selected rotation order; and The instruction is dispatched to the next release queue.

6. The method according to claim 1, comprising: During the cycle, multiple instructions are received, including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; According to the first rotation order, each of the one or more instructions designated as resource-intensive is assigned to a corresponding one of the multiple release queues; as well as Each of the one or more instructions designated as non-resource-intensive is assigned to a corresponding one of the plurality of release queues according to the second rotation order, wherein the second rotation order is the reverse of the first rotation order.

7. The method of claim 6, further comprising tracking a position in the first rotation sequence and a position in the second rotation sequence for use in subsequent cycles.

8. The method according to claim 6, wherein, The multiple publish queues are divided into a first group and a second group that operates independently of the first group; and Each of the first group and the second group is associated with a corresponding first rotation order for instructions designated as resource-intensive and a corresponding second rotation order for instructions designated as non-resource-intensive.

9. The method according to claim 6, wherein, At least two of the plurality of instructions are paired instructions; The method further includes pairing each of the unpaired instructions with another unpaired instruction; and The assignment of each of the one or more instructions designated as resource-intensive includes assigning each of the one or more instructions designated as resource-intensive, together with another of the plurality of instructions, according to the first round-robin order; and The dispatching of each of the one or more designated non-resource-intensive instructions includes dispatching each of the one or more designated non-resource-intensive instructions in pairs with another designated non-resource-intensive instruction according to the second round order.

10. A method for instruction dispatch, comprising: During the cycle, multiple instructions are received, including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; According to the first round of rotation, each of the one or more instructions designated as resource-intensive is assigned to a corresponding one of the multiple release queues; as well as According to a second rotation order that is the reverse of the first rotation order, each of the one or more instructions designated as non-resource intensive is assigned to a corresponding one of the plurality of release queues.

11. The method of claim 10, further comprising tracking the position in the first rotation sequence and the position in the second rotation sequence for use in subsequent cycles.

12. The method according to claim 10, wherein, The multiple publish queues are divided into a first group and a second group that operates independently of the first group; and Each of the first group and the second group is associated with a corresponding first rotation order for instructions designated as resource-intensive and a corresponding second rotation order for instructions designated as non-resource-intensive.

13. The method according to claim 10, wherein, At least two of the plurality of instructions are paired instructions; The method further includes pairing each of the unpaired instructions with another unpaired instruction; and The assignment of each of the one or more instructions designated as resource-intensive includes assigning each of the one or more instructions designated as resource-intensive, together with another of the plurality of instructions, according to the first round-robin order; and The dispatching of each of the one or more designated non-resource-intensive instructions includes dispatching each of the one or more designated non-resource-intensive instructions in pairs with another designated non-resource-intensive instruction according to the second round order.

14. A processor, comprising: Instruction fetching unit; The dispatch unit is communicatively coupled to the instruction acquisition unit; as well as Multiple publish queues are communicatively coupled to the dispatch unit; The dispatch unit is configured as follows: Receive multiple instructions from the instruction acquisition unit; Determine the corresponding resource intensity for each of the plurality of instructions; The rotation order of each of the plurality of instructions is selected based on the corresponding resource intensity, wherein the first rotation order is associated with instructions designated as resource intensive, and the second rotation order, which is different from the first rotation order, is associated with instructions designated as non-resource intensive. Based on the selected rotation order, a corresponding release queue from multiple release queues is selected for each of the plurality of instructions; and Each of the plurality of instructions is assigned to the corresponding selected release queue.

15. The processor of claim 14, wherein, The instruction acquisition unit is configured to dynamically determine, from period to period, the instruction type designated as resource-intensive.

16. The processor of claim 14, wherein, Each of the plurality of publishing queues has 2 time slots; and Selecting the appropriate release queue from the plurality of release queues for each of the plurality of instructions includes selecting the appropriate release queue and time slot based on the corresponding selected rotation order.

17. The processor of claim 14, wherein, The dispatch unit is further configured to: determine that the corresponding selected publish queue for a given instruction among the plurality of instructions is busy, and wait to dispatch the given instruction among the plurality of instructions until the corresponding selected publish queue becomes available.

18. The processor of claim 14, wherein, The dispatch unit is further configured to: determine that a corresponding selected release queue for a given instruction among the plurality of instructions is busy; in response to determining that the corresponding selected release queue is busy, select a next release queue based on the corresponding selected round-robin order; and dispatch the given instruction among the plurality of instructions to the next release queue.

19. The processor of claim 14, wherein, The dispatch unit is configured as follows: During the cycle, multiple instructions are received, including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; According to the first rotation order, each of the one or more instructions designated as resource-intensive is assigned to a corresponding one of the plurality of release queues; as well as According to the second rotation order, each of the one or more instructions designated as non-resource intensive is assigned to a corresponding one of the plurality of release queues, wherein the second rotation order is the reverse of the first rotation order.

20. The processor of claim 19, wherein, The dispatch unit is further configured to track the position in the first rotation sequence and the position in the second rotation sequence for use in subsequent cycles.

21. The processor according to claim 19, wherein, The multiple publish queues are divided into a first group and a second group that operates independently of the first group; and Each of the first group and the second group is associated with a corresponding first rotation order for instructions designated as resource-intensive and a corresponding second rotation order for instructions designated as non-resource-intensive.

22. The processor according to claim 19, wherein, At least two of the plurality of instructions are paired instructions; The dispatch unit is further configured to dispatch the plurality of instructions in pairs, such that each of the one or more instructions designated as resource-intensive is dispatched together with another of the plurality of instructions according to the first rounding order, and each of the one or more instructions designated as non-resource-intensive is dispatched in pairs with another instruction designated as non-resource-intensive according to the second rounding order.

23. The processor according to claim 19, wherein, The instruction acquisition unit is configured to dynamically determine the instruction type designated as resource-intensive for each cycle.

24. A computer system, comprising: The memory is configured to store program code; as well as A processor, communicatively coupled to the memory and configured to execute the program code, wherein the processor includes: Instruction fetching unit; The dispatch unit is communicatively coupled to the instruction acquisition unit; and Multiple publish queues are communicatively coupled to the dispatch unit; The dispatch unit is configured as follows: During the cycle, multiple instructions are received, including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; According to the first round-robin order, each of the one or more instructions designated as resource-intensive is assigned to a corresponding one of the plurality of release queues; and According to a second rotation order that is the reverse of the first rotation order, each of the one or more instructions designated as non-resource intensive is assigned to a corresponding one of the plurality of release queues.

25. The computer system according to claim 24, wherein, The dispatch unit is further configured to track the position in the first rotation sequence and the position in the second rotation sequence for use in subsequent cycles.

26. The computer system according to claim 24, wherein, The multiple publish queues are divided into a first group and a second group that operates independently of the first group; and Each of the first group and the second group is associated with a corresponding first rotation order for instructions designated as resource-intensive and a corresponding second rotation order for instructions designated as non-resource-intensive.

27. The computer system according to claim 24, wherein, At least two of the plurality of instructions are paired instructions; The dispatch unit is further configured to dispatch the plurality of instructions in pairs, such that each of the one or more instructions designated as resource-intensive is dispatched together with another instruction of the plurality of instructions according to the first rounding order, and each of the one or more instructions designated as non-resource-intensive is dispatched in pairs with another instruction designated as non-resource-intensive according to the second rounding order.

28. The computer system according to claim 24, wherein, The instruction acquisition unit is configured to dynamically determine the instruction type designated as resource-intensive for each cycle.

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