Light emitting element and display device including the same

Abstract

A light emitting element and a display device including the same are provided. The light emitting diode includes a first semiconductor layer; a second semiconductor layer; an active layer disposed between the first semiconductor layer and the second semiconductor layer; a protective layer disposed to surround an outer surface of at least one of the first semiconductor layer, the second semiconductor layer, and the active layer; and an insulating layer disposed to surround an outer surface of the protective layer, wherein the protective layer includes a two-dimensional material.

Description

Technical Field

[0001] The present invention relates to a light-emitting element and a display device including the light-emitting element. Background Technology

[0002] Recently, with the increasing interest in information display, research and development of display devices have been ongoing. Summary of the Invention

[0003] Technical issues

[0004] The present invention has been dedicated to providing a light-emitting element with improved element life and efficiency by controlling surface defects of a semiconductor core, and a display device including the light-emitting element.

[0005] The purpose of this invention is not limited to the purposes mentioned above, and other technical purposes not mentioned can be clearly understood by those skilled in the art through the following description.

[0006] An embodiment provides a light-emitting element comprising: a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a protective layer disposed around the outer surface of at least one of the first semiconductor layer, the second semiconductor layer, and the active layer; and an insulating layer disposed around the outer surface of the protective layer, wherein the protective layer comprises a two-dimensional (2D) material.

[0007] 2D materials can include CaF2, Ti 0.9 At least one of O2, mica, SiO2, WS2, MoS2, Ni(OH)2, Cu(OH)2, Mg(OH)2, GaS, talc, and hexagonal boron nitride (hBN).

[0008] The band gap of 2D materials can be 3.5 eV or greater.

[0009] The protective layer may be partially disposed on the outer surface of the first semiconductor layer, the second semiconductor layer, or the active layer, and the outer surface of the first semiconductor layer, the second semiconductor layer, or the active layer exposed by the protective layer may be in contact with the insulating layer.

[0010] The protective layer can be completely disposed on the outer surface of the first semiconductor layer, the second semiconductor layer and / or the active layer.

[0011] The protective layer can be directly disposed on the outer surface of the first semiconductor layer, the second semiconductor layer, and the active layer.

[0012] The insulating layer can be made of inorganic materials.

[0013] Inorganic materials may include SiO x SiN x SiOx N y AlO x AlN x ZrO x HfO x and TiO x At least one of them.

[0014] The insulating layer may include the same material as the first semiconductor layer, the second semiconductor layer, or the active layer.

[0015] The insulating layer can be directly applied to the protective layer.

[0016] Another embodiment provides a display device comprising: a plurality of pixels, each of the plurality of pixels including a first electrode and a second electrode spaced apart from each other and a light-emitting element disposed between the first electrode and the second electrode, and each of the light-emitting elements including a semiconductor core, a protective layer disposed around an outer surface of the semiconductor core, and an insulating layer disposed around an outer surface of the protective layer, wherein the protective layer comprises a two-dimensional (2D) material.

[0017] The protective layer can be partially disposed on the outer surface of the semiconductor core, and the semiconductor core exposed by the protective layer can contact the insulating layer.

[0018] The protective layer can be completely placed on the outer surface of the semiconductor core.

[0019] 2D materials include CaF2 and Ti 0.9 At least one of O2, mica, SiO2, WS2, MoS2, Ni(OH)2, Cu(OH)2, Mg(OH)2, GaS, talc, and hexagonal boron nitride (hBN).

[0020] The band gap of 2D materials can be 3.5 eV or greater.

[0021] The semiconductor core may include a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0022] The protective layer can be directly disposed on the outer surface of the first semiconductor layer, the second semiconductor layer, and the active layer.

[0023] The insulating layer can be made of inorganic materials.

[0024] The insulating layer may include the same material as the semiconductor core.

[0025] The insulating layer can be directly applied to the protective layer.

[0026] Details of other embodiments are included in the detailed description and accompanying drawings.

[0027] Beneficial effects

[0028] According to embodiments of the present invention, since surface defects of the semiconductor core can be effectively controlled by forming a protective layer of two-dimensional material on the semiconductor core of the light-emitting element, the lifespan and efficiency of the light-emitting element can be improved.

[0029] The effects of the embodiments of the present invention are not limited to those shown above, and many more effects are included in this specification. Attached Figure Description

[0030] Figure 1 This is a perspective view of the light-emitting element according to an embodiment.

[0031] Figure 2 and Figure 3 This is a cross-sectional view of the light-emitting element according to an embodiment.

[0032] Figure 4 It shows Figure 2 A magnified view of area "A".

[0033] Figure 5 and Figure 6 A perspective view and a cross-sectional view of a light-emitting element according to another embodiment are shown.

[0034] Figure 7 A top plan view of a display device according to an embodiment is shown.

[0035] Figures 8 to 10 A circuit diagram of a pixel according to an embodiment is shown.

[0036] Figure 11 and Figure 12 A cross-sectional view of a pixel according to an embodiment is shown. Detailed Implementation

[0037] The advantages and features of the invention, as well as the methods of carrying out the invention, can be more readily understood by referring to the following detailed description and accompanying drawings of preferred embodiments. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. This disclosure is provided so that it will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art; furthermore, the invention is defined only by the scope of the claims.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this disclosure, they indicate the presence of the stated elements, steps, operations, and / or means, but do not exclude the presence or addition of one or more other elements, steps, operations, and / or means.

[0039] Additionally, the terms "connection" or "combination" can broadly refer to physical connection and / or electrical connection or physical combination and / or electrical combination. Furthermore, this can broadly refer to direct connection or indirect connection or direct combination or indirect combination, as well as integrated connection or non-integrated connection or integrated combination or non-integrated combination.

[0040] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or there may be intermediate elements or layers present. Throughout the specification, the same reference numerals denote the same constituent elements.

[0041] Although the terms "first," "second," etc., are used to describe various component elements, these component elements are not limited by these terms. These terms are only used to distinguish one component element from another. Therefore, the first component element described below can be a second component element within the technical spirit of the present invention.

[0042] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a perspective view of the light-emitting element according to an embodiment. Figure 2 and Figure 3 This is a cross-sectional view of the light-emitting element according to an embodiment.

[0044] Figures 1 to 3 A cylindrical light-emitting element (LD) is shown, but the type and / or shape of the light-emitting element (LD) are not limited to this.

[0045] Reference Figures 1 to 3 The light-emitting element (LD) may include a semiconductor core NR, a protective layer PVL surrounding the semiconductor core NR, and an insulating layer INF surrounding the protective layer PVL.

[0046] The semiconductor core NR may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, when the extension direction of the light-emitting element LD is referred to as the direction of length L, the semiconductor core NR may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 stacked sequentially along the direction of length L.

[0047] In some embodiments, the light-emitting element (LD) may be configured to have a cylindrical shape extending in one direction. The light-emitting element (LD) may have a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the first end EP1 of the light-emitting element (LD). The remaining one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the second end EP2 of the light-emitting element (LD).

[0048] In some embodiments, the light-emitting element (LD) may be a light-emitting element manufactured in a cylindrical shape by means of etching or the like. In this specification, "cylindrical shape" includes rod-like or bar-like shapes that are long in the length L direction, such as cylinders or polygonal cylinders (i.e., having an aspect ratio greater than 1), but the shape of its cross-section is not specifically limited. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its transverse side cross-section).

[0049] Light-emitting elements (LDs) can have dimensions ranging from nanometers to micrometers. For example, LDs can have diameters (or widths) and / or lengths (L) ranging from nanometers to micrometers. However, the dimensions of LDs are not limited to these and can vary depending on the design conditions of various devices (e.g., display devices) that use LDs as light sources.

[0050] The first semiconductor layer 11 may be a first conductive semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an N-type semiconductor layer doped with a first conductive dopant such as Si, Ge, Sn, etc. However, the materials included in the first semiconductor layer 11 are not limited to these, and the first semiconductor layer 11 may be made of various materials.

[0051] The active layer 12 is disposed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be varied depending on the type of light-emitting element (LD).

[0052] A capping layer (not shown) doped with a conductive dopant may be formed on the upper and / or lower portion of the active layer 12. For example, the capping layer may be formed as an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN and InAlGaN may be used to form the active layer 12; otherwise, various materials may be used to form the active layer 12.

[0053] The second semiconductor layer 13 is disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a P-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a second conductive dopant (such as Mg). However, the materials included in the second semiconductor layer 13 are not limited to these, and the second semiconductor layer 13 may be formed from various materials.

[0054] When a threshold voltage or a higher voltage is applied to the corresponding end of the light-emitting element (LD), the LD emits light while electron-hole pairs recombine in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source not only for pixels in display devices but also for various other light-emitting devices.

[0055] In some embodiments, the light-emitting element LD may further include a protective layer PVL disposed on the surface of the semiconductor core NR. The protective layer PVL may be directly disposed on the surface of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0056] The protective layer PVL can be configured to surround the outer peripheral surface of the semiconductor core NR, i.e., the outer peripheral surface of at least one of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. In an embodiment, the protective layer PVL can be partially disposed around the semiconductor core NR (i.e., as shown in the example). Figure 2 The outer surface of the first semiconductor layer 11, active layer 12, or second semiconductor layer 13 shown. When the protective layer PVL is partially disposed on the outer surface of the semiconductor core NR, the outer surface of the first semiconductor layer 11, active layer 12, or second semiconductor layer 13 exposed by the protective layer PVL can contact the insulating layer INF, which will be described later. In this case, the protective layer PVL can be formed first in areas where the concentration of surface defects of the semiconductor core NR is high to effectively control surface defects. (Referring later...) Figure 4 Describe it in detail.

[0057] In another embodiment, the protective layer PVL can be completely disposed on the outer surface of the semiconductor core NR, that is, as... Figure 3The outer surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 shown in the figure.

[0058] In some embodiments, the protective layer PVL may expose the respective ends of the semiconductor core NR with different polarities. For example, the protective layer PVL may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 respectively disposed at the first end EP1 and the second end EP2 of the semiconductor core NR. In another embodiment, the protective layer PVL may expose the sides of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the semiconductor core NR.

[0059] In embodiments, the protective layer PVL may comprise a two-dimensional (2D) material. A two-dimensional material may refer to a nanoscale crystalline material, for example, a material having a crystalline structure in a plane with a thickness of one to three atoms. For example, a 2D material may have a planar crystalline structure with a thickness of 1 nm or less. In this case, the 2D material can form a planar crystalline structure through sp2 hybridization bonding (e.g., the 2D material may comprise atoms bonded together by bonds formed by sp2 hybridized atomic orbitals (resulting in a planar structure)). However, the 2D material is not limited to this; a 2D material may be a multilayer composed of multiple layers made of nanoscale crystalline material, and may be referred to as a material having a structure in which multiple layers are bonded by van der Waals bonds. In this case, the multiple layers comprising the 2D material can be formed by van der Waals bonds, allowing the individual layers to be separated relatively easily.

[0060] When the protective PVL layer includes the aforementioned 2D material, the lifespan and efficiency of the light-emitting element (LD) can be improved because surface defects in the semiconductor core NR can be controlled. This will be referred to... Figure 4 Detailed description.

[0061] Figure 4 It shows Figure 2 A magnified view of area "A".

[0062] Reference Figure 4 The protective PVL layer can be formed as a two-dimensional thin film structure to form out-of-plane van der Waals bonds with the surface of the semiconductor core NR. In this case, even if there are defects such as vacancies on the surface of the semiconductor core NR, the surface defect concentration can be reduced or the defective parts can be protected by the protective PVL layer, thus minimizing the surface defects of the semiconductor core NR.

[0063] Typically, when dry etching is used to manufacture the semiconductor core NR, vacancies or dangling bonds are created due to the partial absence of atoms on the surface of the NR. Even with dry etching to control these surface defects, the defective parts of the NR cannot be eliminated. Furthermore, even if the insulating layer is formed directly on the NR, lattice defects exist at the interface with the insulating layer INF due to the vacancies in the NR, preventing the insulating layer from growing and leaving the NR surface inadequately protected. In other words, the lifetime, efficiency, and crystallinity of the light-emitting diode (LD) are degraded due to these surface defects in the NR.

[0064] Therefore, the light-emitting element (LD) according to the embodiment can effectively control surface defects by first forming a protective layer (PVL) in a region where the surface defect concentration of the semiconductor core (NR) is high using a two-dimensional material. Furthermore, when the protective layer (PVL) contains a two-dimensional material, the concentration of surface defects at the interface between the protective layer (PVL) and the adjacent insulating layer (INF) can be minimized due to the formation of sp2 hybrid bonds in the in-plane direction. Therefore, the lifetime and efficiency of the light-emitting element (LD) can be improved.

[0065] In this embodiment, the protective PVL layer may include CaF2, Ti 0.9 O2, mica, SiO2, WS2, MoS2, Ni(OH)2, Cu(OH)2, Mg(OH)2, GaS, talc (Talc), and hexagonal boron nitride (hBN) can be used as two-dimensional materials, but are not limited thereto. For example, the material of the protective layer PVL can be selected from various two-dimensional materials in the range of having a band gap of 3.5 eV or greater.

[0066] Return to reference Figure 3 The light-emitting element (LD) may further include an insulating layer (INF) disposed on the surface of the protective layer (PVL). The insulating layer (INF) may be configured to surround the outer peripheral surface of the protective layer (PVL). The insulating layer (INF) may be formed directly on the surface of the protective layer (PVL). The thickness of the insulating layer (INF) may be thicker than the thickness of the protective layer (PVL), but the invention is not limited thereto.

[0067] In some embodiments, the insulating layer INF may expose the respective ends of the semiconductor core NR with different polarities. For example, the insulating layer INF may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 disposed at the first end EP1 and the second end EP2 of the semiconductor core NR. In another embodiment, the insulating layer INF may expose the sides of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the semiconductor core NR.

[0068] The insulating layer INF may include inorganic insulating materials. Furthermore, the insulating layer INF may be formed as a single layer or a multilayer comprising two layers. When the insulating layer INF is formed as a double layer, each layer can be formed using different materials through separate processes. However, the invention is not limited to this; the various layers forming the insulating layer INF may be formed using the same material through a continuous process. For example, the insulating layer INF may include silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) and titanium dioxide (TiO) x At least one insulating material from the group consisting of aluminum oxide (Al₂O₃). For example, the insulating layer INF can be formed from aluminum oxide (Al₂O₃). x ) and silicon dioxide (SiO) x It is made of double layers, but not limited to this.

[0069] In some embodiments, the insulating layer INF may comprise the same material as the semiconductor core NR (i.e., the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13). For example, the insulating layer INF may comprise at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto. Thus, when the insulating layer INF comprises the same material as the semiconductor core NR, epitaxial growth is possible, and therefore a high-quality insulating layer INF can be formed to more effectively control surface defects.

[0070] When the insulating layer INF is disposed on the semiconductor core NR and the protective layer PVL, short circuits between the active layer 12 and the electrodes (e.g., at least one of the contact electrodes connected to the respective ends of the semiconductor core NR), which will be described later, can be prevented. Therefore, the electrical stability of the light-emitting element LD can be ensured. Furthermore, when the insulating layer INF is disposed on the surface of the light-emitting element LD, its lifetime and efficiency can be improved by minimizing surface defects. Additionally, even when multiple light-emitting elements LD are disposed in close contact with each other, undesirable short circuits between the light-emitting elements LD can be prevented.

[0071] In some embodiments, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the protective layer PVL, and / or the insulating layer INF, the light-emitting element LD may also include other constituent elements. For example, the light-emitting element LD may additionally include one or more of a phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer disposed on one end side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0072] Figure 5 and Figure 6 A perspective view and a cross-sectional view of a light-emitting element according to another embodiment are shown.

[0073] Reference Figure 5 and Figure 6 The light-emitting element LD may also include at least one electrode layer 14 disposed at one end of the second semiconductor layer 13.

[0074] Electrode layer 14 may comprise a metal or a conductive metal oxide. For example, electrode layer 14 may be formed by using alone or in combination of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, and transparent electrode materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)). Electrode layer 14 may be substantially transparent or translucent. Therefore, light generated by the light-emitting element LD can pass through electrode layer 14 to be emitted to the outside of the light-emitting element LD.

[0075] In some embodiments, the protective layer PVL and / or the insulating layer INF may at least partially cover the outer peripheral surface of the electrode layer 14. That is, the protective layer PVL and / or the insulating layer INF may be selectively formed on the surface of the electrode layer 14. Additionally, the protective layer PVL and / or the insulating layer INF may be formed to expose the respective ends of the light-emitting element LD with different polarities; for example, they may expose at least one region of the electrode layer 14. However, the invention is not limited thereto.

[0076] at the same time, Figure 5 and Figure 6 Only the electrode layer 14 disposed on the second semiconductor layer 13 is shown, but the present invention is not limited thereto. The light-emitting element LD may also include an electrode layer disposed on the first semiconductor layer 11.

[0077] Light-emitting devices including the aforementioned light-emitting elements (LDs) can be used not only in display devices but also in various types of devices that require a light source. For example, multiple light-emitting elements (LDs) can be arranged in each pixel of a display panel, and the LDs can serve as the light source for each pixel. However, the application areas of light-emitting elements (LDs) are not limited to the examples described above. For instance, LDs can be used in other types of devices that require a light source, such as lighting devices. Referring below... Figures 7 to 12 The detailed description includes a display device with a light-emitting element LD according to the above embodiments.

[0078] Figure 7 A top plan view of a display device according to an embodiment is shown.

[0079] Figure 7 A display device (specifically, a display panel PNL disposed in the display device) is shown as a device that can be used. Figures 1 to 6 The embodiments described herein are examples of electronic devices using a light-emitting element (LD) as a light source.

[0080] Each pixel unit PXU of the display panel PNL and each pixel constituting each pixel unit PXU of the display panel PNL may include at least one light-emitting element (LD). For convenience, Figure 7 The structure of the display panel PNL is briefly illustrated based on the display area DA. However, in some embodiments, at least one driving circuit portion (e.g., at least one of a scan driver and a data driver), wiring, and / or pads (also referred to as "solder pads") not shown may also be provided in the display panel PNL.

[0081] Reference Figure 7 The display panel PNL may include a substrate SUB and pixel units PXU disposed on the substrate SUB. Pixel units PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. In the following text, when referring to any one or more of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, or when referring to two or more types of pixels in general, they will be referred to as "pixel PXL" or "multiple pixel PXL".

[0082] The substrate SUB constitutes the base component of the display panel PNL and can be a rigid substrate or rigid film, or a flexible substrate or flexible film. For example, the substrate SUB can be a hard substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal material, or at least one layered insulating layer. There are no specific limitations on the material and / or physical properties of the substrate SUB.

[0083] In one embodiment, the substrate SUB may be substantially transparent. Here, "substantially transparent" can mean that light can be transmitted at a predetermined transmittance or higher. In another embodiment, the substrate SUB may be translucent or opaque. Additionally, according to an embodiment, the substrate SUB may include a reflective material.

[0084] The display panel PNL and the substrate SUB used to form the display panel include a display area DA for displaying images and a non-display area NDA other than the display area DA.

[0085] Pixel PXL can be set in the display area DA. In the non-display area NDA, various wiring, pads, and / or internal circuit components of the pixel PXL connected to the display area DA can be set. Pixel PXL can be configured according to stripe or... The arrangement structure is regular. However, the arrangement structure of pixels PXL is not limited to this; pixels PXL can be arranged in the display area DA in various structures and / or methods.

[0086] In some embodiments, two or more types of pixels PXL emitting different colors of light can be disposed in the display area DA. For example, in the display area DA, a first pixel PXL1 emitting a first color of light, a second pixel PXL2 emitting a second color of light, and a third pixel PXL3 emitting a third color of light can be arranged in the X-axis and Y-axis directions. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 arranged adjacent to each other can form a pixel unit PXU capable of emitting various colors of light. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be a sub-pixel emitting a predetermined color of light. In some embodiments, the first pixel PXL1 can be a red pixel emitting red light, the second pixel PXL2 can be a green pixel emitting green light, and the third pixel PXL3 can be a blue pixel emitting blue light, but the invention is not limited thereto.

[0087] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are each provided with a first-color light-emitting element, a second-color light-emitting element, and a third-color light-emitting element as light sources, respectively, so that they emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are provided with light-emitting elements of the same color, and include color conversion layers and / or color filters of different colors disposed on each light-emitting element, so that they can emit light of the first color, the second color, and the third color, respectively. However, there is no specific limitation on the color, type, and / or number of pixels PXL constituting each pixel unit PXU. That is, the color of the light emitted by each pixel PXL can be changed in various ways.

[0088] Pixel PXL may include at least one light source driven by predetermined control signals (e.g., scan signals and data signals) and / or predetermined power supplies (e.g., a first power supply and a second power supply). In embodiments, the light source may include at least one according to... Figures 1 to 6 One embodiment uses a light-emitting element (LD), for example, an ultra-small cylindrical light-emitting element LD with a size ranging from nanometers to micrometers. However, the invention is not limited to this, and various types of light-emitting elements (LDs) can be used as the light source for the pixel PXL.

[0089] In this embodiment, each pixel PXL can be configured as an active pixel. However, there are no specific limitations on the type, structure, and / or driving method of the pixel PXL that can be applied to the display device. For example, each pixel PXL can be configured as a pixel of a passive or active light-emitting display device with various structures and / or driving methods.

[0090] Figures 8 to 10 A circuit diagram of a pixel according to an embodiment is shown. For example, Figures 8 to 10 An embodiment of a pixel PXL applicable to an active display device is shown. However, the types of pixel PXL and display devices are not limited to this.

[0091] In some embodiments, Figures 8 to 10 The pixel PXL shown can be set in... Figure 7 One of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 in the display panel PNL. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures.

[0092] Reference Figure 8 The pixel PXL may include a light source unit LSU for generating light with a brightness corresponding to the data signal and a pixel circuit PXC for driving the light source unit LSU.

[0093] A light source unit (LSU) may include at least one light-emitting element connected between a first power supply VDD and a second power supply VSS. For example, the LSU may include a first electrode ELT1 (also referred to as a "first pixel electrode" or "first alignment electrode") connected to the first power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode ELT2 (also referred to as a "second pixel electrode" or "second alignment electrode") connected to the second power supply VSS via a second power line PL2, and a plurality of light-emitting elements LD connected in the same direction between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0094] Each of the light-emitting elements (LDs) may include a first end (e.g., a P-type end) connected to a first power supply VDD via a first electrode ELT1 and / or pixel circuit PXC, and a second end (e.g., an N-type end) connected to a second power supply VSS via a second electrode ELT2. That is, the light-emitting elements (LDs) may be connected in parallel in the forward direction between the first electrode ELT1 and the second electrode ELT2. The respective light-emitting elements (LDs) connected in the forward direction between the first power supply VDD and the second power supply VSS constitute respective effective light sources, and these effective light sources may be combined to constitute the light source unit (LSU) of pixel PXL.

[0095] The first power supply VDD and the second power supply VSS can have different potentials, allowing the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential, and the second power supply VSS can be set to a low potential. In this case, at least during the light-emitting period of pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS can be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0096] One end (e.g., the P-type end) of the light-emitting element LD constituting each light source unit LSU can be connected to the pixel circuit PXC via an electrode of the light source unit LSU (e.g., the first pixel electrode ELT1 of each pixel PXL), and can be connected to the first power supply VDD via the pixel circuit PXC and the first power line PL1. The other end (e.g., the N-type end) of the light-emitting element LD can be connected to the second power supply VSS via another electrode of the light source unit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power line PL2.

[0097] The light-emitting element (LD) can emit light with a brightness corresponding to the driving current supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current to the light source unit (LSU) corresponding to the grayscale value to be displayed in the corresponding frame. The driving current supplied to the light source unit (LSU) can be shunt to flow in the light-emitting element (LD) connected in the forward direction. Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing therein, the light source unit (LSU) can emit light with a brightness corresponding to the driving current.

[0098] The pixel circuit PXC can be connected between the first power supply VDD and the first electrode ELT1. The pixel circuit PXC can be connected to the scan line Si and data line Dj of the pixel PXL. For example, when the pixel PXL is set in the i-th horizontal line (row) (i is a positive integer) and the j-th vertical line (column) (j is a positive integer) of the display area DA, the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0099] In some embodiments, a pixel circuit (PXC) may include a plurality of transistors and at least one capacitor. For example, a pixel circuit (PXC) may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0100] The first transistor T1 is connected between the first power supply VDD and the light source unit LSU. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to the first electrode ELT1. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the drive current supplied to the light source unit LSU in response to the voltage of the first node N1. That is, the first transistor T1 can be a drive transistor that controls the drive current of the pixel PXL.

[0101] A second transistor T2 is connected between the data line Dj and the first node N1. For example, the first electrode (e.g., the source electrode) of the second transistor T2 can be connected to the data line Dj, and the second electrode (e.g., the drain electrode) of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal SSi with a gate turn-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj and the first node N1.

[0102] For each frame period, the corresponding frame's data signal DSj is supplied to the data line Dj, and during the period in which the scan signal SSi with the gate on voltage is supplied, the data signal DSj is transmitted to the first node N1 through the on second transistor T2. That is, the second transistor T2 can be a switching transistor used to transmit each data signal DSj to the inside of pixel PXL.

[0103] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode is connected to the first node N1. During each frame period, the storage capacitor Cst is charged with a voltage corresponding to the data signal DSj supplied to the first node N1.

[0104] At the same time, Figure 8 In the diagram, the transistors included in the pixel circuit PXC (e.g., the first transistor T1 and the second transistor T2) are shown as P-type transistors, but are not limited thereto; at least one of the first transistor T1 and the second transistor T2 can be changed to an N-type transistor. Furthermore, the pixel circuit PXC can be constructed as a pixel circuit with various structures and / or driving methods.

[0105] Reference Figure 9 The pixel circuit PXC can also be connected to the sensing control line SCLi and the sensing line SLj. For example, the pixel circuit PXC of pixel PXL, located at the i-th horizontal line and the j-th vertical line of display area DA, can be connected to the i-th sensing control line SCLi and the j-th sensing line SLj of display area DA. The pixel circuit PXC can also include a third transistor T3. Optionally, in another embodiment, the sensing line SLj can be omitted, and the characteristics of pixel PXL can also be detected by detecting the sensing signal SENj via the data line Dj of the corresponding pixel PXL (or adjacent pixels).

[0106] The third transistor T3 is connected between the first transistor T1 and the sensing line SLj. For example, one electrode of the third transistor T3 can be connected to one electrode of the first transistor T1 that is connected to the first electrode ELT1 (e.g., the source electrode), and the other electrode of the third transistor T3 can be connected to the sensing line SLj. Alternatively, when the sensing line SLj is omitted, the other electrode of the third transistor T3 can be connected to the data line Dj.

[0107] The gate electrode of the third transistor T3 is connected to the sensing control line SCLi. When the sensing control line SCLi is omitted, the gate electrode of the third transistor T3 can be connected to the scan line Si. The third transistor T3 is turned on by a sensing control signal SCSi supplied to the sensing control line SCLi with a gate on-state voltage (e.g., a high-level voltage) during a predetermined sensing period, thereby electrically connecting the sensing line SLj and the first transistor T1.

[0108] In some embodiments, the sensing period may be a period for extracting characteristics (e.g., the threshold voltage of the first transistor T1) of each of the pixels PXL disposed in the display area DA. During the sensing period, the first transistor T1 can be turned on by supplying a predetermined reference voltage that enables the first transistor T1 to conduct via data line Dj and the second transistor T2, and by connecting each pixel PXL to a current source, etc. Additionally, the first transistor T1 can be connected to the sensing line SLj to turn on the third transistor T3 by supplying a sensing control signal SCSi with a gate turn-on voltage to the third transistor T3. Thereafter, a sensing signal SENj is obtained via the sensing line SLj, and characteristics of each pixel PXL other than the threshold voltage of the first transistor T1 can be detected using the sensing signal SENj. Image data can be transformed using information about the characteristics of each pixel PXL, making it possible to compensate for characteristic differences between pixels PXL disposed in the display area DA.

[0109] at the same time, Figure 8 and Figure 9 An embodiment in which all effective light sources (i.e., light-emitting elements LD) forming each light source unit LSU are connected in parallel is shown, but the invention is not limited thereto. For example, as Figure 10 As shown, the light source unit (LSU) of each pixel PXL can be constructed to include at least two stages in series. In the description... Figure 10 In the implementation of the example, the terms will be omitted. Figure 8 and Figure 9 A detailed description of similar or identical constructions (e.g., pixel circuits PXC) in the embodiments.

[0110] Reference Figure 10 A light source unit (LSU) may include at least two light-emitting elements connected in series with each other. For example, a light source unit (LSU) may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 connected in series in the forward direction between a first power supply VDD and a second power supply VSS. Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can constitute an effective light source.

[0111] In the following text, when referring to a specific light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element is referred to as "first light-emitting element LD1", "second light-emitting element LD2", or "third light-emitting element LD3". Furthermore, when referring to at least one of the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or when referring to the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3 in general, it will be referred to as "light-emitting element LD" or "multiple light-emitting elements LD".

[0112] The first end (e.g., the P-type end) of the first light-emitting element LD1 is connected to the first power supply VDD via the first electrode ELT1 (that is, the first pixel electrode) of the light source unit LSU. In addition, the second end (e.g., the N-type end) of the first light-emitting element LD1 is connected to the first end (e.g., the P-type end) of the second light-emitting element LD2 via the first intermediate electrode IET1.

[0113] The first end of the second light-emitting element LD2 is connected to the second end of the first light-emitting element LD1. In addition, the second end of the second light-emitting element LD2 (e.g., the N-type end) is connected to the first end of the third light-emitting element LD3 (e.g., the P-type end) through the second intermediate electrode IET2.

[0114] The first end of the third light-emitting element LD3 is connected to the second end of the second light-emitting element LD2. Additionally, the second end of the third light-emitting element LD3 (e.g., an N-type end) can be connected to the second power supply VSS via the second electrode of the light source unit LSU (i.e., the second pixel electrode ELT2). In this manner, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be sequentially connected in series between the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU.

[0115] at the same time, Figure 10 An embodiment of a three-stage series connection of light-emitting elements (LDs) is shown, but the invention is not limited thereto. Two light-emitting elements (LDs) can be connected in a two-stage series connection, or four or more light-emitting elements (LDs) can be connected in a four-stage or more series connection.

[0116] Assuming the same brightness is achieved using light-emitting elements (LDs) under identical conditions (e.g., the same size and / or number), compared to a light source unit (LSU) with LDs connected in parallel, the voltage applied between the first electrode ELT1 and the second electrode ELT2 increases, and the drive current flowing through the LSU decreases. Therefore, when constructing the LSU for each pixel PXL using a series structure, the panel current flowing through the display panel PNL can be reduced.

[0117] As in the above embodiments, each light source unit LSU is connected in the forward direction to a first power supply VDD and a second power supply VSS, enabling it to include multiple light-emitting elements LD that constitute each effective light source. Furthermore, the connection structure between the light-emitting elements LD can be varied according to the embodiments. For example, the light-emitting elements LD can be connected to each other only in series or in parallel, or they can be connected in a hybrid series / parallel structure.

[0118] Figure 11 and Figure 12 A cross-sectional view of a pixel according to an embodiment is shown.

[0119] Figure 11 and Figure 12 The structure of each pixel PXL based on a light-emitting element LD is schematically shown, and the storage capacitor Cst and the transistor T connected to the first electrode ELT1 are shown respectively to illustrate the various circuit elements for constructing the pixel circuit PXC. Figure 8 The first transistor T1 in the process. In the following text, the first transistor T1 will also be referred to as "transistor T" unless otherwise specified.

[0120] Meanwhile, the structure of transistor T and storage capacitor Cst and / or the location of each layer thereof are not limited to Figure 11 and Figure 12 The embodiments shown are general embodiments, and various modifications can be made to them. Furthermore, in the embodiments, the transistors T included in each pixel circuit PXC may have substantially the same or similar structures to each other, but are not limited thereto. For example, in another embodiment, at least one of the transistors T included in the pixel circuit PXC may have a different cross-sectional structure than the other transistors T and / or may be disposed on different layers.

[0121] Reference Figure 11 and Figure 12 The pixel PXL and the display device including the pixel PXL may include a substrate SUB, a circuit layer PCL disposed on one surface of the substrate SUB, and a display layer DPL disposed on the circuit layer.

[0122] The circuit layer PCL may include circuit elements for constructing the pixel circuit PXC for each pixel PXL and various wiring connected to the circuit elements. The display layer DPL may include electrodes (e.g., first electrode ELT1 and second electrode ELT2 and / or first contact electrode CNE1 and second contact electrode CNE2) and light-emitting elements LD for constructing the light source unit LSU for each pixel PXL.

[0123] The circuit layer PCL may include at least one circuit element electrically connected to the light-emitting element LD of each pixel PXL. For example, the circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst disposed in each pixel region to form the pixel circuit PXC of the corresponding pixel PXL. In addition, the circuit layer PCL may also include at least one power line and / or signal line connected to each pixel circuit PXC and / or light source unit LSU. For example, the circuit layer PCL may include a first power line PL1, a second power line PL2, and a scan line Si and a data line Dj for each pixel PXL. On the other hand, when the pixel circuit PXC is omitted and the light source unit LSU of each pixel PXL is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the circuit layer PCL may be omitted.

[0124] Additionally, the circuit layer PCL may include multiple insulating layers. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and / or a passivation layer PSV, sequentially stacked on one side of the substrate SUB. Furthermore, the circuit layer PCL may selectively include at least one light-blocking pattern (not shown) disposed beneath at least some of the transistors T.

[0125] The buffer layer (BFL) prevents impurities from diffusing into each circuit element. The buffer layer (BFL) can be formed as a single layer, or as a multilayer with at least two or more layers. When the buffer layer (BFL) is multilayered, the individual layers can be made of the same material or different materials. Various circuit elements, such as transistors (T) and storage capacitors (Cst), as well as various wirings connected to the circuit elements, can be disposed on the buffer layer (BFL). Meanwhile, in some embodiments, the buffer layer (BFL) can be omitted. In this case, at least one circuit element and / or wiring can be directly disposed on one surface of the substrate (SUB).

[0126] Each transistor T may include a semiconductor pattern SCP (also known as a "semiconductor layer" or "active layer"), a gate electrode GE, a first transistor electrode TE1, and a second transistor electrode TE2. Meanwhile, Figure 11 and Figure 12An embodiment is shown in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor pattern SCP, but the invention is not limited thereto. For example, in another embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 disposed in at least one transistor T may be integrated with each semiconductor pattern SCP.

[0127] A semiconductor pattern SCP can be disposed on a buffer layer BFL. For example, the semiconductor pattern SCP can be disposed between a substrate SUB on which the buffer layer BFL is formed and a gate insulating layer GI. The semiconductor pattern SCP may include a first region contacting each first transistor electrode TE1, a second region contacting each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In some embodiments, one of the first region and the second region may be a source region, and the other of the first region and the second region may be a drain region.

[0128] In some embodiments, the semiconductor pattern SCP can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. Additionally, the channel region of the semiconductor pattern SCP can be an intrinsic semiconductor as an undoped semiconductor pattern, and each of the first and second regions of the semiconductor pattern SCP can be a semiconductor pattern doped with predetermined impurities.

[0129] In this embodiment, the semiconductor pattern SCP of the transistor T included in each pixel circuit PXC can be made of substantially the same or similar materials. For example, the semiconductor pattern SCP of the transistor T can be one of polycrystalline silicon, amorphous silicon, and oxide semiconductor.

[0130] In another embodiment, some of the transistors T and the remainder may include semiconductor patterns SCPs made of different materials. For example, the semiconductor patterns SCPs of some of the transistors T may be made of polycrystalline silicon or amorphous silicon, and the semiconductor patterns SCPs of the remainder of the transistors T may be made of oxide semiconductors.

[0131] A gate insulating layer GI can be disposed on a semiconductor pattern SCP. For example, the gate insulating layer GI can be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI can be formed as a single layer or multiple layers, and can include silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y Various types of organic / inorganic insulating materials.

[0132] The gate electrode GE can be disposed on the gate insulating layer GI. For example, the gate electrode GE can be stacked with the semiconductor pattern SCP, with the gate insulating layer GI disposed between the gate electrode GE and the semiconductor pattern SCP. Meanwhile, Figure 11 and Figure 12 The diagram shows a top-gate structure for transistor T, but in another embodiment, transistor T may have a bottom-gate structure. In this case, the gate electrode GE may be configured to be stacked below the semiconductor pattern SCP.

[0133] The first interlayer insulating layer ILD1 can be disposed on the gate electrode GE. For example, the first interlayer insulating layer ILD1 can be disposed between the gate electrode GE and the first transistor electrode TE1 and between the gate electrode GE and the second transistor electrode TE2. The first interlayer insulating layer ILD1 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the first interlayer insulating layer ILD1 may include silicon nitride (SiN) as a component. x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y Various types of organic / inorganic insulating materials, and the materials included in the first interlayer insulation layer ILD1 are not specifically limited.

[0134] A first transistor electrode TE1 and a second transistor electrode TE2 may be disposed on each semiconductor pattern SCP, and at least one first interlayer insulating layer ILD1 is disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and the semiconductor pattern SCP. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed at different ends of the semiconductor pattern SCP, and a gate insulating layer GI and a first interlayer insulating layer ILD1 are disposed between the first transistor electrode TE1 and the second transistor electrode TE2. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor pattern SCP. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to a first region and a second region of the semiconductor pattern SCP through corresponding contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1. In some embodiments, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other of them may be a drain electrode.

[0135] At least one transistor T disposed in the pixel circuit PXC can be connected to at least one pixel electrode. For example, the transistor T can be electrically connected to the first electrode ELT1 of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) through the passivation layer PSV and / or the bridging pattern BRP.

[0136] The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2 stacked on top of each other. Each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be composed of a single layer or multiple layers. In addition, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be disposed on the same layer as at least one electrode or semiconductor pattern SCP constituting the first transistor T1.

[0137] For example, the first capacitor electrode CE1 can be configured as a multilayer electrode, comprising a lower electrode LE disposed on the same layer as the semiconductor pattern SCP of the first transistor T1, and an upper electrode UE disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. The second capacitor electrode CE2 can be configured as a single-layer electrode, disposed on the same layer as the gate electrode of the first transistor T1, and disposed between the lower electrode LE and the upper electrode UE of the first capacitor electrode CE1. However, the structure and / or position of each of the first capacitor electrode CE1 and the second capacitor electrode CE2 can be varied. For example, one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may include a conductive pattern disposed on a layer different from the electrodes (e.g., the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2) and the semiconductor pattern SCP that constitute the first transistor T1. For example, the first capacitor electrode CE1 or the second capacitor electrode CE2 may have a single-layer structure or a multilayer structure including a conductive pattern disposed on the second interlayer insulating layer ILD2.

[0138] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be disposed on the same layer as an electrode of a circuit element included in the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be disposed on the same layer as the gate electrode GE of the transistor T, and the data line Dj of each pixel PXL may be disposed on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T.

[0139] The first power line PL1 and / or the second power line PL2 can be disposed on the same layer or different layers as the gate electrode GE of transistor T or the first transistor electrode TE1 and the second transistor electrode TE2. For example, the second power line PL2, used to supply power to the second power supply VSS, can be disposed on the second interlayer insulating layer ILD2 and at least partially covered by the passivation layer PSV. The second power line PL2 can be electrically connected to the second electrode ELT2 of the light source unit LSU disposed on the passivation layer PSV through the second contact hole CH2 passing through the passivation layer PSV. However, the position and / or structure of the first power line PL1 and / or the second power line PL2 can be varied. For example, the second power line PL2 can be disposed on the same layer as the gate electrode GE of transistor T or the first transistor electrode TE1 and the second transistor electrode TE2 and electrically connected to the second electrode ELT2 through at least one bridging pattern (not shown) and / or the second contact hole CH2.

[0140] The second interlayer insulating layer ILD2 can be disposed above the first interlayer insulating layer ILD1, and can cover the first transistor electrode TE1 and the second transistor electrode TE2 and / or the storage capacitor Cst disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the second interlayer insulating layer ILD2 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y Various types of organic / inorganic insulating materials, but not specifically limited to them.

[0141] A bridging pattern BRP, a first electric field line PL1, and / or a second electric field line PL2 for connecting at least one circuit element (e.g., a first transistor T1) disposed in the pixel circuit PXC to the first electrode ELT1 may be disposed on the second interlayer insulating layer ILD2. However, in some embodiments, the second interlayer insulating layer ILD2 may be omitted. In this case, it may be omitted. Figure 11 and Figure 12 The bridging pattern BRP, and the second power line PL2 can be disposed on a layer on which a transistor T is disposed.

[0142] The passivation layer PSV can be disposed on circuit elements including transistor T and storage capacitor Cst, and / or on wiring including first power line PL1 and second power line PL2. The passivation layer PSV can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the passivation layer PSV may include at least one organic insulating layer and can be used to substantially planarize the surface of the circuit layer PCL.

[0143] The display layer DPL can be disposed on the passivation layer PSV of the circuit layer PCL. The display layer DPL may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in the light-emitting region of each pixel PXL and constituting each light source unit LSU, and at least one light-emitting element LD connected between the first electrodes ELT1 and the second electrodes ELT2. On the other hand, Figure 11 and Figure 12 Both show a light-emitting element LD set in each pixel PXL, but each pixel PXL can be as follows: Figure 8 As in the embodiments described above, multiple light-emitting elements (LDs) are connected between the first electrode ELT1 and the second electrode ELT2. Therefore, in the following description, each embodiment will be assumed to include multiple light-emitting elements (LDs).

[0144] Additionally, the display layer DPL may also include a first contact electrode CNE1 and a second contact electrode CNE2 for more stably connecting the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2, and a dam BNK1 for causing a region of each of the first electrode ELT1 and the second electrode ELT2 and / or the first contact electrode CNE1 and the second contact electrode CNE2 to protrude upwards. Furthermore, the display layer DPL may also include at least one conductive layer and / or an insulating layer.

[0145] The dam BNK1 can be disposed on the circuit layer PCL. The dam BNK1 can be formed as a separate or integral pattern. The dam BNK1 can protrude in the height direction of the substrate SUB (that is, in the third direction (Z-axis direction)).

[0146] According to embodiments, the embankment BNK1 can have various shapes. In one embodiment, the embankment BNK1 can be a embankment structure with a positive conical structure. For example, the embankment BNK1 can be formed with an inclined surface that is tilted at a predetermined angle relative to the base SUB. However, the invention is not limited to this; the embankment BNK1 can include sidewalls with curved surfaces or stepped shapes. For example, the embankment BNK1 can have a semi-circular or semi-elliptical cross-section.

[0147] The electrodes and insulating layers disposed on the upper part of the dam BNK1 can have a shape corresponding to the dam BNK1. For example, the first electrode ELT1 and the second electrode ELT2, as well as the first contact electrode CNE1 and the second contact electrode CNE2, can be disposed on a region of the dam BNK1 and can include inclined or curved surfaces having a shape corresponding to the shape of the dam BNK1. Similarly, the first insulating layer INS1, the third insulating layer INS3, and / or the fourth insulating layer INS4 can be disposed on the dam BNK1 to include inclined or curved surfaces having a shape corresponding to the shape of the dam BNK1.

[0148] The dam BNK1 may include an insulating material comprising at least one inorganic and / or organic material. For example, the dam BNK1 may include at least one inorganic film, said at least one inorganic film comprising silicon nitride (SiN). x ) or silicon dioxide (SiO) x Various inorganic insulating materials. Optionally, the dam BNK1 may include at least one organic film comprising various organic insulating materials and / or at least one photoresist film, or may include a single or multiple layer insulator comprising organic / inorganic materials. That is, the material and / or pattern shape of the dam BNK1 can be varied.

[0149] In an embodiment, the dam BNK1 can be used as a reflective member. For example, the dam BNK1, together with the first electrode ELT1 and the second electrode ELT2 disposed thereon, can be used as a reflective member that guides the light emitted from each light-emitting element LD in a desired direction (e.g., the upward direction of pixel PXL) to improve the light efficiency of pixel PXL.

[0150] The first electrode ELT1 and the second electrode ELT2, included in the pixel electrodes of each pixel PXL, can be disposed at the upper part of the embankment BNK1. The first electrode ELT1 and the second electrode ELT2 can be disposed in each pixel region where each pixel PXL is disposed and / or formed. For example, the first electrode ELT1 and the second electrode ELT2 can be disposed in the light-emitting region of each pixel PXL. The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 can be spaced side-by-side at a predetermined interval in each light-emitting region.

[0151] In some embodiments, the first electrode ELT1 and / or the second electrode ELT2 may have separate patterns for each pixel PXL or have patterns that are commonly connected to multiple pixels PXL. Alternatively, prior to the formation of the pixel PXL, specifically before the alignment of the light-emitting element LD is completed, the first electrodes ELT1 of the pixel PXL disposed in the display area DA are connected to each other, and the second electrodes ELT2 of the pixel PXL may be connected to each other. For example, before the alignment of the light-emitting element LD is completed, the first electrodes ELT1 of the pixel PXL may be integrally or non-integrally formed and electrically connected to each other, and the second electrodes ELT2 of the pixel PXL may be integrally or non-integrally formed and electrically connected to each other. When the first electrodes ELT1 or the second electrodes ELT2 of the pixel PXL are non-integrally connected, the first electrodes ELT1 or the second electrodes ELT2 may be electrically connected to each other through at least one contact hole and / or bridging pattern.

[0152] The first electrode ELT1 and the second electrode ELT2 can respectively receive a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage) during the alignment step of the light-emitting element LD. For example, one of the first electrode ELT1 and the second electrode ELT2 can be supplied with an AC-type alignment signal, and the other of the first electrode ELT1 and the second electrode ELT2 can be supplied with an alignment voltage with a constant voltage level (e.g., ground voltage). That is, during the alignment step of the light-emitting element LD, a predetermined alignment signal can be applied to the first electrode ELT1 and the second electrode ELT2. Therefore, an electric field can be formed between the first electrode ELT1 and the second electrode ELT2. The light-emitting element LD disposed in the light-emitting area of ​​each pixel PXL can self-align between the first electrode ELT1 and the second electrode ELT2 through the electric field. After the alignment of the light-emitting element LD is completed, by disconnecting at least the first electrode ELT1 between pixels PXL, pixels PXL can be formed in a form that can be driven individually.

[0153] The first electrode ELT1 can be electrically connected via the first contact hole CH1 to a predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). In an embodiment, the first electrode ELT1 can be electrically connected to the bridging pattern BRP via the first contact hole CH1, and therefore, the first electrode ELT1 can be electrically connected to the transistor T. However, the invention is not limited to this; the first electrode ELT1 can be directly connected to the predetermined power line or signal line.

[0154] The second electrode ELT2 can be electrically connected via the second contact hole CH2 to a predetermined circuit element (e.g., at least one transistor constituting a pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). In an embodiment, the second electrode ELT2 can be electrically connected to the second power line PL2 via the second contact hole CH2. However, the invention is not limited to this; the second electrode ELT2 can be directly connected to a predetermined power line or signal line.

[0155] Each of the first electrode ELT1 and the second electrode ELT2 may contain at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include: at least one metal or alloy thereof selected from various metallic materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu); conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or fluorine tin oxide (FTO); or at least one conductive material selected from conductive polymers such as PEDOT, but not limited thereto. For example, each of the first electrode ELT1 and the second electrode ELT2 may contain other conductive materials such as carbon nanotubes or graphene. Furthermore, each of the first electrode ELT1 and the second electrode ELT2 may be composed of a single layer or multiple layers. For example, each of the first electrode ELT1 and the second electrode ELT2 may include a reflective electrode layer comprising a reflective conductive material. Additionally, each of the first electrode ELT1 and the second electrode ELT2 may selectively include at least one of at least a transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper part of the reflective electrode layer and / or the transparent electrode layer.

[0156] A first insulating layer INS1 may be disposed on a region of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of each of the first electrode ELT1 and the second electrode ELT2, and may include an opening exposing another region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may include an opening formed on the upper surface of the embankment BNK1. In the region of the opening in the first insulating layer INS1, the first electrode ELT1 and the second electrode ELT2 may be electrically connected to the first contact electrode CNE1 and the second contact electrode CNE2, respectively. Meanwhile, in some embodiments, the first insulating layer INS1 may be omitted. In this case, the light-emitting element LD may be directly disposed on the passivation layer PSV and / or one end of each of the first electrode ELT1 and the second electrode ELT2.

[0157] In one embodiment, a first insulating layer INS1 may be formed first to completely cover the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is supplied and arranged on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose an area of ​​the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 has an opening exposing an area of ​​the first electrode ELT1 and the second electrode ELT2 on the upper surface of the embankment BNK1, and may at least partially cover the inclined or curved surfaces of the first electrode ELT1 and the second electrode ELT2. Alternatively, in another embodiment, the first insulating layer INS1 may be patterned as a separate pattern that is only partially disposed under the light-emitting element LD after the light-emitting element LD has been fully supplied and arranged. After the first electrode ELT1 and the second electrode ELT2 are formed, the first insulating layer INS1 may be formed to cover the first electrode ELT1 and the second electrode ELT2. Therefore, it is possible to prevent the first electrode ELT1 and the second electrode ELT2 from being damaged in subsequent processes.

[0158] The first insulating layer INS1 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating layer INS1 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Various types of organic / inorganic insulating materials.

[0159] Light-emitting elements (LDs) can be disposed and arranged on a first electrode ELT1, a second electrode ELT2, and a first insulating layer INS1. LDs can be supplied to each pixel region in which a dam BNK1, the first electrode ELT1, the second electrode ELT2, and the first insulating layer are formed, to be disposed between the first electrode ELT1 and the second electrode ELT2. For example, multiple LDs can be supplied to the light-emitting area of ​​each pixel PXL by inkjet printing, slot coating, or various other methods, and the LDs can be oriented and aligned between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment signal (or alignment voltage) applied to each of the first electrode ELT1 and the second electrode ELT2.

[0160] In one embodiment, at least some of the light-emitting elements (LDs) can be disposed between a pair of first electrodes ELT1 and second electrodes ELT2, such that the two ends of the light-emitting element LD (i.e., the first end EP1 and the second end EP2) are superimposed on the adjacent pair of first electrodes ELT1 and second electrodes ELT2. In another embodiment, at least some of the light-emitting elements (LDs) can be disposed between a pair of adjacent first electrodes ELT1 and second electrodes ELT2 without superimposing on the first electrodes ELT1 and / or the second electrodes ELT2, and can be electrically connected to the pair of first electrodes ELT1 and second electrodes ELT2 respectively via first contact electrodes CNE1 and second contact electrodes CNE2. Each light-emitting element LD electrically connected between the first electrodes ELT1 and the second electrodes ELT2 can form an effective light source for the corresponding pixel PXL. The effective light source can constitute the light source unit LSU for the corresponding pixel PXL.

[0161] The second insulating layer INS2 can be disposed on a region of the light-emitting element LD. For example, the second insulating layer INS2 can be disposed on a region of each of the light-emitting elements LD to expose the first end EP1 and the second end EP2 of each of the light-emitting elements LD. For example, the second insulating layer INS2 can be partially disposed on the upper part of a region including the central region of each of the light-emitting elements LD. When the second insulating layer INS2 is formed on the light-emitting element LD after the alignment of the light-emitting element LD is completed, it is possible to prevent the light-emitting element LD from deviating from the alignment position.

[0162] The second insulating layer INS2 can be formed in an independent pattern in the light-emitting area of ​​each pixel PXL, but is not limited thereto. In some embodiments, the second insulating layer INS2 can be omitted, and in this case, one end of each of the first contact electrode CNE1 and the second contact electrode CNE2 can be directly disposed on the upper surface of the light-emitting element LD.

[0163] The second insulating layer INS2 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating layer INS2 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Various types of organic / inorganic insulating materials, including photoresist.

[0164] The two ends of the light-emitting element LD that are not covered by the second insulating layer INS2 (i.e., the first end EP1 and the second end EP2) can be covered by the first contact electrode CNE1 and the second contact electrode CNE2, respectively. The first contact electrode CNE1 and the second contact electrode CNE2 are formed to be spaced apart from each other. For example, adjacent first contact electrodes CNE1 and second contact electrodes CNE2 can be spaced apart from each other on at least one adjacent first end EP1 and second end EP2 of the light-emitting element LD, and the third insulating layer INS3 is between the first contact electrode CNE1 and the second contact electrode CNE2.

[0165] Furthermore, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed at the upper position of the first electrode ELT1 and the second electrode ELT2 to cover the exposed area of ​​each of the first electrode ELT1 and the second electrode ELT2. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on at least one area of ​​each of the first electrode ELT1 and the second electrode ELT2 so as to directly / indirectly contact each of the first electrode ELT1 and the second electrode ELT2 at the upper part of the embankment BNK1 or around the embankment BNK1. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 can be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. That is, the first electrode ELT1 and the second electrode ELT2 can be electrically connected to the first end EP1 and the second end EP2 of at least one adjacent light-emitting element LD through the first contact electrode CNE1 and the second contact electrode CNE2, respectively.

[0166] In an embodiment, such as Figure 11As shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be sequentially formed in different layers on one surface of the substrate SUB. In this case, a third insulating layer INS3 can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2. Meanwhile, the order in which the first contact electrode CNE1 and the second contact electrode CNE2 are formed can vary depending on the embodiment. For example, in another embodiment, the second contact electrode CNE2 is formed first before the first contact electrode CNE1 is formed, and the third insulating layer INS3 is formed to cover the second contact electrode CNE2 and the second insulating layer INS2, and then the first contact electrode CNE1 can be formed on the third insulating layer INS3. However, the invention is not limited to this; the first contact electrode CNE1 and the second contact electrode CNE2 can be formed as follows: Figure 12 The electrodes shown are disposed on the same layer. That is, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed from the same conductive layer on one surface of the substrate SUB. In this case, since the first contact electrode CNE1 and the second contact electrode CNE2 can be formed simultaneously in the same process, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified. However, the present invention is not limited to this, and the first contact electrode CNE1 and the second contact electrode CNE2 can be formed sequentially.

[0167] The first contact electrode CNE1 and the second contact electrode CNE2 can be made of various transparent conductive materials. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various transparent materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine tin oxide (FTO), and they can be made substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the light-emitting element LD through each of the first end EP1 and the second end EP2 can pass through the first contact electrode CNE1 and the second contact electrode CNE2 to be emitted to the outside of the display panel PNL.

[0168] A third insulating layer INS3 can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2. Thus, when the third insulating layer INS3 is formed between the first contact electrode CNE1 and the second contact electrode CNE2, electrical stability between the first end EP1 and the second end EP2 of the light-emitting element LD can be ensured. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be stably separated by the third insulating layer INS3. Therefore, short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD can be effectively prevented.

[0169] The third insulating layer INS3 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the third insulating layer INS3 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Various types of organic / inorganic insulating materials.

[0170] A fourth insulating layer INS4 may be disposed on the first contact electrode CNE1, the second contact electrode CNE2, and / or the third insulating layer INS3. For example, the fourth insulating layer INS4 may cover the dam BNK1, the first electrode ELT1, the second electrode ELT2, the first insulating layer INS1, the second insulating layer INS2, and / or the third insulating layer INS3, the light-emitting element LD, and the first contact electrode CNE1 and the second contact electrode CNE2. The fourth insulating layer INS4 may include at least one inorganic layer and / or at least one organic layer.

[0171] The fourth insulating layer INS4 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, the fourth insulating layer INS4 may include silicon nitride (SiN) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Various types of organic / inorganic insulating materials.

[0172] In an embodiment, the fourth insulating layer INS4 may comprise a multilayer thin-film encapsulation layer. For example, the fourth insulating layer INS4 may comprise a multilayer thin-film encapsulation layer comprising at least two inorganic insulating layers and at least one organic insulating layer disposed between the at least two inorganic insulating layers. However, the invention is not limited thereto, and the material and / or structure of the fourth insulating layer INS4 may be varied.

[0173] Those skilled in the art related to this embodiment will readily understand that many modifications can be made without substantially departing from the novel teachings and advantages. The embodiments should be considered in a descriptive sense only and not for limiting purposes. The scope of the invention is defined by the appended claims rather than by the specific embodiments, and all differences within the equivalent scope will be construed as included in the invention.

Claims

1. A light-emitting element, the light-emitting element comprising: The system comprises a first semiconductor layer, a second semiconductor layer, and an active layer, wherein the active layer is disposed between the first semiconductor layer and the second semiconductor layer. A protective layer is configured to surround the outer surface of at least one of the first semiconductor layer, the second semiconductor layer, and the active layer; as well as An insulating layer is configured to surround the outer surface of the protective layer. The protective layer comprises a two-dimensional material to form out-of-plane van der Waals bonds with the outer surfaces of at least one of the first semiconductor layer, the second semiconductor layer, and the active layer.

2. The light-emitting element according to claim 1, wherein, The two-dimensional material includes CaF2 and Ti. 0.9 At least one of O2, mica, SiO2, WS2, MoS2, Ni(OH)2, Cu(OH)2, Mg(OH)2, GaS, talc and hBN.

3. The light-emitting element according to claim 1, wherein, The band gap of the two-dimensional material is 3.5 eV or greater.

4. The light-emitting element according to claim 1, wherein, The protective layer is partially disposed on the outer surface of the first semiconductor layer, the second semiconductor layer, or the active layer, and The outer surface of the first semiconductor layer, the second semiconductor layer, or the active layer exposed by the protective layer is in contact with the insulating layer.

5. The light-emitting element according to claim 1, wherein, The protective layer is completely disposed on the outer surfaces of the first semiconductor layer, the second semiconductor layer, and the active layer.

6. The light-emitting element according to claim 1, wherein, The protective layer is directly disposed on the outer surfaces of the first semiconductor layer, the second semiconductor layer, and the active layer.

7. The light-emitting element according to claim 1, wherein, The insulating layer is made of inorganic materials.

8. The light-emitting element according to claim 7, wherein, The inorganic material includes SiO₂ x SiN x SiO x N y AlO x AlN x ZrO x HfO x and TiO x At least one of them.

9. The light-emitting element according to claim 1, wherein, The insulating layer comprises the same material as the first semiconductor layer, the second semiconductor layer, or the active layer.

10. The light-emitting element according to claim 1, wherein, The insulating layer is directly disposed on the protective layer.

11. A display device, the display device comprising: The system comprises multiple pixels, each including: a first electrode and a second electrode spaced apart from each other; and a light-emitting element disposed between the first electrode and the second electrode. Each of the light-emitting elements includes: a semiconductor core; a protective layer configured to surround the outer surface of the semiconductor core; and an insulating layer configured to surround the outer surface of the protective layer. The protective layer comprises a two-dimensional material to form out-of-plane van der Waals bonds with the outer surface of the semiconductor core.

12. The display device according to claim 11, wherein, The protective layer is partially disposed on the outer surface of the semiconductor core, and The semiconductor core exposed by the protective layer is in contact with the insulating layer.

13. The display device according to claim 11, wherein, The protective layer is completely disposed on the outer surface of the semiconductor core.

14. The display device according to claim 11, wherein, The two-dimensional material includes CaF2 and Ti. 0.9 At least one of O2, mica, SiO2, WS2, MoS2, Ni(OH)2, Cu(OH)2, Mg(OH)2, GaS, talc and hBN.

15. The display device according to claim 11, wherein, The band gap of the two-dimensional material is 3.5 eV or greater.

16. The display device according to claim 11, wherein, The semiconductor core includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

17. The display device according to claim 16, wherein, The protective layer is directly disposed on the outer surface of the first semiconductor layer, the second semiconductor layer, and / or the active layer.

18. The display device according to claim 11, wherein, The insulating layer is made of inorganic materials.

19. The display device according to claim 11, wherein, The insulating layer comprises the same material as the semiconductor core.

20. The display device according to claim 11, wherein, The insulating layer is directly disposed on the protective layer.

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