Method for self-testing a phase of a three-level anpc inverter with lc filter

Abstract

A method for testing an inverter with a bridge is disclosed, the bridge comprising a first switch (T1) arranged between a positive connection (DC+) of a split intermediate circuit with a midpoint (M) and a positive internal connection (PI), a second switch (T2) arranged between the positive internal connection (PI) and a bridge output (BR), a third switch (T3) arranged between the bridge output (BR) and a negative internal connection (NI), a fourth switch (T4) arranged between the negative internal connection (NI) and a negative connection (DC-) of the split intermediate circuit, a fifth switch (T5) arranged between the midpoint (M) and the positive internal connection (PI), and a sixth switch (T6) arranged between the midpoint (M) and the negative internal connection (NI). A network filter with a filter choke (LF) and a filter capacitor (CF) is connected on the bridge output (BR). The method comprises applying an intermediate circuit voltage to the split intermediate circuit while the bridge output (BR) with the connected network filter is separated from the connected network, completely discharging the filter capacitor (CF), closing the first switch (T1) and the sixth switch (T6) while the fourth switch (T4) and the fifth switch (T5) are open, subsequently clocking the second switch (T2) with a plurality of short pulses, wherein the duty cycle of the short pulses is predefined between 1% and 5%, determining a falling voltage on the filter capacitor (CF) after the clocking, determining a fault state of the bridge if the falling voltage lies outside a voltage window with an upper window limit and a lower window limit. Furthermore an inverter is disclosed, the inverter having a control device designed and arranged for carrying out the method according to any one of the preceding claims and connecting the inverter to a connected network only if no fault state is determined.

Description

Technical Field

[0001] This invention relates to a method for testing an inverter. Furthermore, this application relates to an inverter configured to implement the testing method. Background Technology

[0002] Furthermore, the inverter is used to convert the direct current power generated by the solar generator into alternating current power so that it can be fed into the alternating current network. For this purpose, an inverter has one or more bridges, which in turn comprise multiple semiconductor switches. By clocking the switches, the potential applied to the DC connection terminals is alternately applied to the bridge output terminals. The bridge output terminals are connected to a phase of the AC voltage network via a network filter. Different topologies exist for the bridge, distinguished by single-level and multi-level topologies. The single-level topology alternately applies only positive or negative potentials to the bridge output terminals, while the multi-level topology applies additional intermediate potentials, typically generated by separate intermediate circuits, to the bridge output terminals. One implementation of this multilevel topology is called the ANPC (Active Neutral Point Clamped) topology, and it includes six switches that, depending on the switch configuration, can apply positive potentials, negative potentials, and the midpoint potential of separate intermediate circuits to the bridge output. Here, the ANPC topology is a particularly efficient bridge topology.

[0003] For efficiency and cost reasons, semiconductor switches are used in this topology, with a maximum permissible blocking voltage less than the input voltage applied to the DC current connection. Therefore, this topology only operates with a switching configuration in which the entire input voltage does not drop across any of the switches. A known drawback is that, in the event of a failure of one of the bridge switches, especially if one of the bridge switches remains continuously on, there is a practically permissible switching configuration in which, due to the failure of one switch, the entire input voltage is still applied to a still-functional switch. This results in indirect damage within the bridge. The indirect damage resulted in the destruction of other bridge switches and other components of the inverter.

[0004] Therefore, the object of the present invention is to provide a method that can check for bridge switch failures before an inverter is put into operation without jeopardizing other bridge switches or other inverter components. Summary of the Invention

[0005] This task is accomplished by the method having the features of claim 1 and by the inverter having the features of claim 11. Preferred embodiments of the invention are described in the dependent claims.

[0006] The method according to the invention is based on an inverter in which the bridge has: a first switch arranged between a positive connection terminal and a positive internal connection terminal of a separated intermediate circuit having a midpoint; a second switch arranged between the positive internal connection terminal and the bridge output terminal; a third switch arranged between the bridge output terminal and a negative internal connection terminal; and a fourth switch arranged between the negative internal connection terminal and the negative connection terminal of the separated intermediate circuit. Furthermore, the bridge has a fifth switch arranged between the midpoint and the positive internal connection terminal, and a sixth switch arranged between the midpoint and the negative internal connection terminal, wherein a network filter with a filter choke and a filter capacitor is connected to the bridge output terminal. The filter capacitor can be connected to the midpoint of the intermediate circuit with one connection terminal. To test an inverter with this bridge, the method according to the invention includes the following steps:

[0007] - Apply intermediate circuit voltage to the separate intermediate circuit, while the bridge output is disconnected from the connected network filter;

[0008] - Discharge the filter capacitor completely;

[0009] - Close the first switch and the sixth switch, while the fourth switch and the fifth switch are open;

[0010] -Then the second switch is clock-controlled with a series of short pulses, wherein the duty cycle of the short pulses is preset between 1% and 5%;

[0011] - After the clock control, determine the voltage drop across the filter capacitor;

[0012] - If the dropped voltage is outside a voltage window with upper and lower limits, the bridge is considered faulty. In a fully functional bridge switch, the filter capacitor is charged to a voltage determined by the duty cycle of the short pulses through multiple short pulses. Simultaneously, this type of clock control ensures that even in the event of a switch failure, the entire intermediate circuit voltage will not be applied to any of the remaining switches for at least such a long duration that this would cause damage to the associated switches. Thus, the test can be performed without causing indirect damage to the bridge. Even if the sixth switch is permanently blocked due to a fault, and thus the entire intermediate circuit voltage drops to the second switch when the second switch is open, this duration is so short due to the low duty cycle that the second switch remains protected. If one of the bridge switches is faulty, causing the charging of the filter capacitor to not occur or to occur in a modified form due to the fault, this can then be determined based on the voltage reached on the filter capacitor. In this situation, a fault condition is identified, and the inverter reacts accordingly, for example, by preventing operation or selecting the bridge switch in a manner that is permissible and will not jeopardize other components despite the fault being identified. Inverters typically already have a device for determining the voltage across the filter capacitors as part of their regulation.

[0013] Preferably, the method is supplemented by the following steps:

[0014] - Fully discharge the filter capacitor;

[0015] - Close the fourth and fifth switches, while the first and sixth switches are open;

[0016] - The third switch is clock-controlled by multiple short pulses, wherein the duty cycle of the short pulses is between 1% and 5%;

[0017] - After the clock control, determine another voltage drop across the filter capacitor;

[0018] - If the other voltage drop is outside the voltage window, then the fault condition of the bridge is determined.

[0019] These supplementary steps correspond to repeating the aforementioned method steps by applying a negative intermediate circuit voltage instead of a positive intermediate circuit voltage under clock control. These steps help identify other potential switching faults.

[0020] In an advantageous variation, the clock control of the second switch is performed using the complementary clock control of the third switch, or vice versa. However, alternatively, the third switch may also remain open during the clock control of the second switch, or the second switch may remain open during the clock control of the third switch. In this case, the clock control of either the second or third switch may be performed with a predetermined number of short pulses.

[0021] In a preferred variant of the test method according to the invention, before clocking the second switch, it is checked whether the potential at the negative internal connection terminal and the potential at the midpoint are consistent; or, before clocking the third switch, it is checked whether the potential at the positive internal connection terminal and the potential at the midpoint are consistent, wherein, if they are inconsistent, the fault state of the bridge is determined respectively.

[0022] If the inverter has multiple bridges, it is preferable to implement the method according to the invention sequentially on each of the bridges to eliminate fault conditions. The inverter is only enabled to operate as intended when all the bridges and their switches are functioning fault-free.

[0023] A filter capacitor connected to the midpoint of the intermediate circuit with one terminal can be discharged by simultaneously closing the fifth and second switches, or by closing the sixth and third switches. Alternatively, a filter capacitor connected to the midpoint of the intermediate circuit with one terminal can also be discharged by simultaneously closing the fifth and sixth switches.

[0024] In another aspect, the present invention relates to an inverter having a bridge circuit, the bridge comprising: a first switch disposed between a positive connection terminal and a positive internal connection terminal of a separate intermediate circuit with a midpoint; a second switch disposed between the positive internal connection terminal and the bridge output terminal; a third switch disposed between the bridge output terminal and a negative internal connection terminal; a fourth switch disposed between the negative internal connection terminal and the negative connection terminal of the separate intermediate circuit; a fifth switch disposed between the midpoint and the positive internal connection terminal; and a sixth switch disposed between the midpoint and the negative internal connection terminal, wherein a network filter with a filter choke and a filter capacitor is connected to the bridge output terminal. The inverter has a control device designed and configured to implement the aforementioned method and to connect the inverter to the connected network only when a fault condition is determined to be absent.

[0025] Here, the inverter may have multiple bridges. In this case, the control device is designed and configured to implement the method sequentially for each of the multiple bridges, and to connect the inverter to the network only when it is determined that there is no fault condition. Attached Figure Description

[0026] The invention will now be illustrated with reference to the accompanying drawings. Herein lies:

[0027] Figure 1 The first switching configuration of the bridge used to discharge the filter capacitor.

[0028] Figure 2 A second switching configuration for the bridge used to charge the filter capacitors in a complementary clock-controlled manner.

[0029] Figure 3 A diagram illustrating a clock control scheme for complementary clock-controlled charging of filter capacitors.

[0030] Figure 4 A third switch configuration for a bridge used to charge filter capacitors in a simple clock-controlled manner.

[0031] Figure 5 The fourth switch configuration of the bridge for complementary clock-controlled charging of the filter capacitors, and

[0032] Figure 6 A flowchart of the method according to the present invention. Detailed Implementation

[0033] Figure 1This diagram illustrates a switching configuration of an ANPC bridge, used to discharge a filter capacitor CF at the bridge's output. The ANPC bridge is connected at its input side to a separate intermediate circuit having a first intermediate circuit capacitor C1 connected to the positive connection DC+ and a second intermediate circuit capacitor C2 connected to the negative connection DC-, the first and second intermediate circuit capacitors being connected in series via a midpoint M. Between the positive connection DC+ and the negative connection DC- is a series circuit consisting of a first switch T1 with an anti-parallel freewheeling diode D1, a second switch T2 with an anti-parallel freewheeling diode D2, a third switch T3 with an anti-parallel freewheeling diode D3, and a fourth switch T4 with an anti-parallel freewheeling diode D4. The first and fourth switches T1 and T4 are implemented as IGBT transistors, while the second and third switches T2 are implemented as MOSFET transistors. The midpoint M is connected via a fifth switch T5 to the positive internal connection PI between the first and second switches T1 and T2. Furthermore, the midpoint M is connected via the negative internal connection terminal NI between the sixth switch T6 and the third switch T3 and the fourth switch T4. The fifth switch T5 and the sixth switch T6 are also implemented as IGBT transistors. An output filter with a filter choke LF and a filter capacitor CF is connected to the bridge output terminal BR located between the second switch T2 and the third switch T3 to provide a filtered output voltage at the AC voltage output terminal.

[0034] To discharge the filter capacitor CF, the third transistor T3 and the sixth transistor T6 are switched on, while all the remaining transistors in the bridge are switched off. This short-circuits the filter capacitor CF through the filter choke LF. Alternatively, the filter capacitor CF can also be discharged via the second switch T2 and the fifth switch T5, or via the fifth switch T5 and the sixth switch T6. Complete discharge, i.e., discharge to zero voltage, also includes discharging to any negligible residual voltage that may still exist.

[0035] Figure 2The second switch configuration of the bridge is shown, which is used to charge the filter capacitor CF to the check voltage in a complementary clock-controlled manner. Here, the first switch T1 and the sixth switch T6 are switched on, while the fifth switch T5 and the fourth switch T4 are switched off. The second switch T2 is now clocked at a high frequency with short pulses, its duty cycle being between 1% and 5%. The third switch T3 is clocked in a complementary manner to the second switch T2. In this way, during the on-phase of the second switch T2, the filter capacitor CF is charged through the first intermediate circuit capacitor C1 and the filter choke LF, and partially discharged again during the on-phase of the third switch T3. As a result of this clock control, a DC voltage is applied to the filter capacitor CF in time averaging, which is equivalent to the product of the voltage on the first intermediate circuit capacitor C1 and the duty cycle. After the clock control of the second switch T2 and the third switch T3 ends, it is checked whether the voltage of the filter capacitor CF is within the voltage window determined by the above relationship. If this is not the case, it can be concluded that one of the switches of the bridge is faulty and the fault condition of the bridge can be determined.

[0036] exist Figure 3 The clock control scheme of the complementary clock control of the bridge is described in more detail below. Here, in the topmost sub-figure, the switching states of the first switch T1, the second switch T2 below it, the third switch T3 below it, and the sixth switch T6 below it are shown as a function of time t on the horizontal axis. For the blocking switching state, the value on the vertical axis is 0, and for the conducting switching state, the value on the vertical axis is 1.

[0037] exist Figure 3 The bottom subplot illustrates the time-varying voltage U across the filter capacitor CF. After the discharge phase EP, where the voltage across the filter capacitor CF is zero, the charging phase LP begins, which features a second switch T2 clocked with short pulses and a third switch T3 clocked in a complementary manner. During this phase, the voltage U gradually approaches its final value, which is then compared to an allowable voltage window with upper and lower limits in the subsequent check phase PP to verify the fault-free function of the switches.

[0038] exist Figure 4 The alternative switch configuration shown is the same as in Figure 2The difference in the switch configuration shown for charging the filter capacitor CF is that the third switch T3 now switches in a blocking manner instead of being switched in a complementary clock-controlled manner. This prevents the filter capacitor CF from discharging between the short pulses of the second switch T2, so that the current through the filter choke LF is consumed only through the freewheeling path formed by the third switch T3, the sixth switch T6, and the filter capacitor CF during this time. Therefore, the voltage across the filter capacitor is gradually formed in each short pulse, so that in the test method for the bridge switch with this switch configuration, the charging phase for the filter capacitor CF ends after a predetermined number of short pulses or after a predetermined charging time before determining the voltage of the filter capacitor CF for testing the bridge switch state.

[0039] exist Figure 5 The alternative switch configuration shown is the same as in Figure 2 The difference in the switching configuration shown for charging the filter capacitor CF is that, here, the filter capacitor CF is charged with opposite polarity through the second intermediate circuit capacitor C2. This switching configuration can be used as... Figure 2 Alternatives or preferred methods of the switch configuration shown are used within the framework of the test method as a supplement, since other switches in this bridge can be checked in terms of their functionality. Here, the fourth switch T4 and the fifth switch T5 are switched to conduction, while the sixth switch T6 and the first switch T1 are switched to blocking. The third switch T3 is now clocked at a high frequency with short pulses, with a duty cycle between 1% and 5%. The second switch T2 is clocked in a complementary manner to the third switch T3. Of course, it is also conceivable that the switch configuration could be modified as described above, with the second switch T2 not clocked in a complementary manner, but switched in a blocking manner.

[0040] Finally, Figure 6 The diagram shows a flowchart of a method for testing an inverter with a bridge according to the present invention. In the first step S1, an intermediate circuit voltage is applied to the separate intermediate circuits of the inverter, for example, by connecting a DC source to the DC voltage terminals DC+ and DC- of the inverter. Here, the output terminal of the bridge with the connected network filter remains separate from the AC voltage network. In the second step S2, the filter capacitor of the network filter is fully discharged. Discharging is achieved by operating the bridge in a switching configuration in which a conduction path is formed from the midpoint of the separate intermediate circuits to the bridge output terminal BR. The order of execution of the first step S1 and the second step S2 is arbitrary.

[0041] In the subsequent third step S3, the first switch T1 and the sixth switch T6 are closed, while the fourth switch T4 and the fifth switch T5 are open. This applies a positive intermediate circuit potential to the positive internal connection terminal PI of the bridge and a midpoint potential to the negative internal connection terminal NI. In the fourth step S4, the second switch T2 is then clocked with a series of short pulses, wherein the duty cycle of the short pulses is preset between 1% and 5%.

[0042] In the final fifth step S5, after clock control, the voltage drop across the filter capacitor is determined, wherein if the dropped voltage is outside a voltage window with an upper and lower limit, the fault state of the bridge is determined.

[0043] If the inverter has multiple bridges, such as one bridge for each phase of the connected AC voltage network, or multiple bridges connected to a phase of the AC voltage network via individual network filters or also via a common network filter, the method can be performed sequentially for each bridge. This method can be supplemented by additional test routines for other fault profiles (Fehlerbilders) of the inverter's bridges or other components. The method can also be performed multiple times to verify the identified fault conditions.

[0044] If a fault condition in the bridge is determined using this method, it can be responded to in different ways. For example, the connection between the inverter and the AC voltage network can be blocked, the inverter can be operated while the relevant bridge is disabled, or the relevant bridge can be operated with restrictions. The fault condition can also be communicated to a higher-level control mechanism.

[0045] List of reference numerals

[0046] DC+ and DC- connectors

[0047] C1, C2 intermediate circuit capacitors

[0048] M midpoint

[0049] T1-T6 switches

[0050] Diodes D1-D6

[0051] BR bridge output

[0052] PI and NI internal connection terminals

[0053] LF filter choke

[0054] CF filter capacitor

[0055] AC voltage output terminal

[0056] Steps S1-S5

[0057] LP charging stage

[0058] EP discharge stage

[0059] PP inspection phase

Claims

1. A method for testing an inverter with a bridge circuit, the bridge comprising: - A first switch (T1) is arranged between the positive connection terminal (DC+) and the positive internal connection terminal (PI) of a separate intermediate circuit having a midpoint (M). - Second switch (T2), the second switch is arranged between the positive internal connection terminal (PI) and the bridge output terminal (BR); - A third switch (T3) is arranged between the bridge output (BR) and the negative internal connection (NI); - Fourth switch (T4), the fourth switch being arranged between the negative internal connection terminal (NI) and the negative connection terminal (DC-) of the separate intermediate circuit; - Fifth switch (T5), which is arranged between the midpoint (M) and the positive internal connection terminal (PI); as well as - The sixth switch (T6) is arranged between the midpoint (M) and the negative internal connection terminal (NI); A network filter is connected to the output terminal (BR) of the bridge circuit. The network filter has a filter choke (LF) and a filter capacitor (CF). The method includes the following steps: - Apply intermediate circuit voltage to the separate intermediate circuit, while the bridge output (BR) is disconnected from the connected network filter; - Discharge the filter capacitor (CF) completely; - Close the first switch (T1) and the sixth switch (T6), while the fourth switch (T4) and the fifth switch (T5) are open; - Next, the second switch (T2) is clocked with multiple short pulses, wherein the duty cycle of the short pulses is preset between 1% and 5%; - After the clock control, determine the voltage drop across the filter capacitor (CF); - If the dropped voltage is outside a voltage window with an upper and lower limit, then the fault condition of the bridge is determined.

2. The method according to claim 1, further comprising the following steps: - Fully discharge the filter capacitor (CF); - Close the fourth switch (T4) and the fifth switch (T5), while the first switch (T1) and the sixth switch (T6) are open; - The third switch (T3) is clock-controlled by multiple short pulses, wherein the duty cycle of the short pulses is between 1% and 5%; - After the clock control, determine another voltage drop across the filter capacitor (CF); - If the other voltage drop is outside the voltage window, then the fault condition of the bridge is determined.

3. The method according to claim 1 or 2, wherein, During the clock control of the second switch (T2), the third switch (T3) remains open, wherein the clock control of the second switch (T2) is performed with a predetermined number of short pulses.

4. The method according to claim 2 or 3, wherein, During the clock control of the third switch (T3), the second switch (T2) remains open, wherein the clock control of the third switch (T3) is performed with a predetermined number of short pulses.

5. The method according to any one of the preceding claims, wherein, Before clocking the second switch (T2), check whether the potential on the negative internal connection terminal (NI) and the potential on the midpoint (M) are consistent, wherein if they are inconsistent, the fault state of the bridge is determined.

6. The method according to any one of claims 2 to 5, wherein, Before clocking the third switch (T3), check whether the potential on the positive internal connection terminal (PI) and the potential on the midpoint (M) are consistent, wherein if they are inconsistent, the fault state of the bridge is determined.

7. The method according to any one of claims 1, 2, 4 to 6, wherein, The clock control of the second switch (T2) is executed by the complementary clock control of the third switch (T3).

8. The method according to any one of claims 2, 3, 5 to 7, wherein, The clock control of the third switch (T3) is executed by the complementary clock control of the second switch (T2).

9. The method according to any one of the preceding claims, wherein, The inverter has multiple bridges, wherein the method is implemented sequentially on each of the bridges.

10. The method according to any one of the preceding claims, wherein, The filter capacitor (CF) is discharged by simultaneously closing the fifth switch (T5) and the second switch (T2), or by closing the sixth switch (T6) and the third switch (T3), or by closing the fifth switch (T5) and the sixth switch (T6).

11. An inverter having a bridge circuit, the bridge comprising: - A first switch (T1) is arranged between the positive connection terminal (DC+) and the positive internal connection terminal (PI) of a separate intermediate circuit having a midpoint (M). - Second switch (T2), the second switch is arranged between the positive internal connection terminal (PI) and the bridge output terminal (BR); - A third switch (T3) is arranged between the bridge output (BR) and the negative internal connection (NI); - Fourth switch (T4), the fourth switch being arranged between the negative internal connection terminal (NI) and the negative connection terminal (DC-) of the separate intermediate circuit; - Fifth switch (T5), which is arranged between the midpoint (M) and the positive internal connection terminal (PI); as well as - The sixth switch (T6) is arranged between the midpoint (M) and the negative internal connection terminal (NI); A network filter is connected to the output terminal (BR) of the bridge circuit. The network filter has a filter choke (LF) and a filter capacitor (CF). Its features are, The inverter has a control device designed and configured to implement the method according to any one of the preceding claims, and to connect the inverter to the connected network only when it is determined that there is no fault condition.

12. The inverter according to claim 11, wherein, The inverter has multiple bridges, wherein the control device is designed and configured to implement the method sequentially for each of the multiple bridges, and to connect the inverter to the network only when it is determined that there is no fault condition.

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