Integrated circuitry and methods for forming a memory array including strings of memory cells

Abstract

A method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. A lowermost first tier of the first tiers includes a conductive first sacrificial material. A conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that differ from each other by at least 0.5 V.

Description

Technical Field

[0001] The embodiments disclosed herein relate to integrated circuit systems and methods for forming memory arrays comprising strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used to store data in computer systems. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least approximately 10 years. Volatile memory dissipates data and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two distinct selectable states. In binary systems, states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. Removing the voltage from the gate essentially prevents current from flowing through the channel region. FETs may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers may store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives (SSDs) instead of conventional hard drives. As yet another example, flash memory is prevalent in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized, and enables manufacturers to provide remote upgrades for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell device includes at least one selection device series-coupled with a series combination of memory cells (wherein the series combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each of which individually includes a reversibly programmable vertical transistor. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells, each individually including a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described, for example, in any one of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in so-called “step structures” at the ends or edges of the array of vertically stacked memory cells. A step structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) that define contact areas for individual word lines, with vertically extending conductive vias contacting these contact areas to provide electrical access to the word lines. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of a portion of the substrate during processing according to an embodiment of the present invention, and is through... Figure 2 It was cut from line 1-1 in the middle.

[0009] Figure 2 Is it through Figure 1 The diagram shows a cross-sectional view taken from line 2-2.

[0010] Figure 3-23 This is a process according to some embodiments of the present invention. Figure 1 and 2 The diagrams of the structure or its parts or alternative embodiments are sequentially cross-sectional, unfolded, enlarged and / or partial views. Detailed Implementation

[0011] Embodiments of the present invention cover methods for forming memory arrays comprising strings of memory cells, such as NAND arrays or arrays of other memory cells that may have at least one array-level peripheral control circuitry system (e.g., array-level CMOS). Embodiments of the present invention cover so-called "back-gate" or "replacement gate" processes, so-called "front-gate" processes, and other processes, whether existing or future developments, that are independent of the formation timing of transistor gates. Embodiments of the present invention also cover existing or future developments of integrated circuit systems comprising memory arrays including strings of memory cells independent of the manufacturing method, such as NAND architectures. Reference Figure 1-23 The first example method embodiment is described, which can be considered as a "post-gate" or "replacement gate," and from... Figure 1 and 2 start.

[0012] Figure 1 and 2 The illustration shows a configuration 10 having an array or array region 12 in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having one or more of the following materials: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / isolated (i.e., electrically) materials. Various materials have been vertically formed on the substrate 11. The materials may be... Figure 1 and 2 The material depicted may be located beside, vertically inside, or vertically outside. For example, components fabricated or fully fabricated in other parts of the integrated circuit system may be disposed above, around, or inside the substrate 11. Control circuitry systems and / or other peripheral circuitry systems for operating components within an array (e.g., array 12) of vertically extending strings of memory cells may also be fabricated, and these circuitry systems may or may not be fully or partially within the array or subarrays. Furthermore, multiple subarrays may be fabricated and operated relatively independently of each other, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0013] In some embodiments, and as shown, a conductor layer 16 comprising conductor material 17 has been formed over the substrate 11. As an example, conductor material 17 comprises an upper conductor material 43 (e.g., n-type or p-type conductive doped polysilicon) having a lower conductor material 44 (e.g., WSi) having a different composition from the upper conductor material 43. x Directly above (e.g., directly against the lower conductor material). Conductor layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuitry and / or common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within array 12.

[0014] The lower portion 18L of the stack 18* is formed over the substrate 11 and the conductor layer 16 (* is a suffix used to encompass all such components that may or may not have other suffixes and are specified with the same numerical value). The stack 18* will include vertically alternating conductive layers 22* and insulating layers 20*, wherein the material of layer 22* has a different composition than that of layer 20*. The stack 18* includes laterally spaced memory block regions 58, which will comprise laterally spaced memory blocks 58 in the finished circuit system construction. In this document, "block" generally includes "sub-block". The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered as longitudinally elongated and oriented, for example, along direction 55. The memory block regions 58 may be indistinguishable at this processing point.

[0015] The conductive layer 22* (alternately referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternately referred to as the second layer) may not include insulating material or may be insulating when combined with the “back gate” or “alternate gate” example method embodiments described herein. In one embodiment, the lower portion 18L includes the lowermost second layer 20z of the second layer 20* directly above (e.g., directly abutting) the conductive material 17. The lowermost second layer 20z is insulating (e.g., includes a material 24 comprising silicon dioxide) and may be sacrificed.

[0016] The bottommost layer 22z of the first layer 22* is directly above (e.g., directly abutting) the bottommost second layer 20z. The bottommost first layer 22z includes a conductive first sacrificial material 78 and a conductive second material 79, the conductive second material being directly electrically coupled to the conductive first sacrificial material 78 and, in one embodiment, directly abutting the conductive first sacrificial material. The conductive first sacrificial material 78 and the conductive second material 79 have different reduction potentials that differ from each other by at least 0.5V. In one embodiment, the different reduction potentials (differences) differ from each other by at least 1.0V, and in one embodiment, they differ from each other by no more than 4.0V. For example, and by way of example only, two materials having reduction potentials of -1.0V and -2.0V have a difference of 1.0V, and two materials having reduction potentials of +1.0V and -2.0V have a difference of 3.0V. In one embodiment, the conductive first sacrificial material 78 and the conductive second material 79 have relatively different thicknesses, and in one such embodiment, the conductive second material 79 is directly above and thinner than the conductive first sacrificial material 78. Alternatively, this can be reversed (not shown). In one embodiment, one of the conductive first sacrificial material 78 and the conductive second material 79 comprises conductive doped silicon (e.g., 78), and the other of the conductive first sacrificial material 78 and the conductive second material 79 (e.g., 79) comprises a metallic material. Alternatively, this can be reversed. In this document, “conductive doped silicon” is at least 1 × 10⁻⁶ silicon with impurities that increase conductivity. 18 atoms / cm 3 Silicon atoms (e.g., polycrystalline silicon).

[0017] In one embodiment, the lower portion 18L is formed to include a conductive third material 80 directly above and electrically coupled to the conductive first sacrificial material 78 and the conductive second material 79. In one embodiment, the conductive first sacrificial material 78 and the conductive third material 80 have a composition that is relatively identical to each other (e.g., conductive doped silicon). In one embodiment, the conductive first sacrificial material 78 and the conductive third material 80 have a greater thickness than the conductive second material 79, and in one such embodiment, they have relatively identical thicknesses. Alternatively, and by way of example only, material 79 may be a location where materials 78 and 80 are shown and have the same thickness, wherein one of materials 78 or 80 is vertically sandwiched therebetween (not shown).

[0018] In one embodiment, the second-lowest second layer 20x of the second layer 20* is directly above the lowest first layer 22z (e.g., including material 24). In another embodiment, a conductive layer 21 including conductive material 47 (e.g., conductive doped polysilicon) is directly above the second-lowest second layer 20x.

[0019] refer to Figure 3-7 Vertically alternating first layers 22 and second layers 20 of the upper portion 18U of the stack 18* are formed above the lower portion 18L. The first layers 22 and second layers 20 comprise different compositional materials 26 and 24 (e.g., silicon nitride and silicon dioxide). The upper portion 18U is shown as beginning with the second layer 20 above the lower portion 18L, but this could alternatively begin with the first layer 22 (not shown). Furthermore, and by way of example, the lower portion 18L may be formed to have one or more first and / or second layers as its top. In any case, only a small number of layers 20 and 22 are shown, while the upper portion 18U (and thus the stack 18*) is more likely to include dozens, a hundred, or more layers 20 and 22. Additionally, other circuitry, which may or may not be part of the peripheral and / or control circuitry system, may be present between the conductor layer 16 and the stack 18*. By way of example only, multiple vertically alternating layers of conductive and insulating materials in such circuit systems may be below the lowermost conductive layer and / or above the uppermost conductive layer in conductive layer 22*. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowermost conductive layer 22*, and one or more select gate layers may be above the uppermost conductive layer in conductive layer 22*. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive layers 22* may be a select gate layer.

[0020] A channel opening 25 is formed (e.g., by etching) through the second layer 20 and the first layer 22 in the upper portion 18U to the conductor layer 16 (e.g., at least to the bottommost first layer 22z). The channel opening 25 may gradually narrow radially inward as it moves deeper within the stack 18 (not shown). In some embodiments, the channel opening 25 may extend into the conductor material 17 of the conductor layer 16 as shown, or it may terminate at the top (not shown). Alternatively, as an example, the channel opening 25 may terminate at the top or inside the bottommost second layer 20z. The reason for extending the channel opening 25 at least to the conductor material 17 of the conductor layer 16 is to provide an anchoring effect to the material within the channel opening 25.

[0021] Horizontally elongated trenches 40 have been formed (e.g., by anisotropic etching) into the stack 18* and are individually located between laterally adjacent memory block regions 58. By way of example and for simplicity, the channel openings 25 are shown as groups or columns arranged in staggered rows of four and five channel openings 25 per row. The trenches 40 will typically be wider than the channel openings 25 (e.g., 10 to 20 times wider, but such wider extents are not shown for simplicity). Any alternative existing or future-developed arrangements and configurations can be used. The trenches 40 and channel openings 25 can be formed relative to each other in any order.

[0022] The trench 40 shown has been formed as a conductive first sacrificial material 78 and a conductive second material 79 extending into the lowermost first layer 22z. As an example, the trench 40 may be initially formed by etching materials 24, 26, and 47 (possibly using different anisotropic etching chemicals) and terminates on or within the material 24 of the second-lowest second layer 20x (if present). A thin sacrificial liner 78 (e.g., hafnium dioxide, alumina, etc.) may then be formed, followed by stamping etching through the thin sacrificial liner to expose the material 24, and subsequently stamping etching through the material 24 to expose the sacrificial material 77. Alternatively, and by way of example only, sacrificial etch stop lines (not shown) having the same overall horizontal profile as the trench 40 may be individually formed in the conductive layer 21 (if present), directly above and in contact with the material 24 of the second-lowest second layer 20x, after which the upper portion 18U is formed. The groove 40 can then be formed by etching materials 24 and 26 to stop on or within the material of the individual sacrificial lines, and then 78 removing the remaining material of such lines before forming the thin sacrificial liner.

[0023] Transistor channel material can be formed vertically along the insulating and conductive layers in individual channel openings, thus including individual channel material strings directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally positioned between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) is formed vertically along the individual charge-blocking region within the charge-blocking region. The insulating charge-transfer material (e.g., a bandgap-engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally positioned between the channel material and the storage material.

[0024] Figure 3-6 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transport material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing their respective thin layers on the stack 18* and within the individual channel openings 25 and subsequently planarizing such transistor materials back at least to the top surface of the stack 18*.

[0025] Channel material 36, serving as channel material string 53, has also been vertically formed in the channel opening 25 along the insulating layer 20 and the conductive layer 22. Due to proportions, materials 30, 32, 34, and 36... Figure 1and 2 The material 37 is shown and designated only in the examples. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). The thickness of each of materials 30, 32, 34, and 36 is typically between 25 angstroms and 100 angstroms. Stamping etching can be performed to remove materials 30, 32, and 34 from the substrate at channel opening 25 (not shown) to expose conductor layer 16, such that channel material 36 directly abuts conductor material 17 of conductor layer 16. Such stamping etching can occur individually with respect to each of materials 30, 32, and 34 (as shown), or it can occur with respect to only some of the materials (not shown). Alternatively, and by way of example only, stamping etching may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 (not yet shown) via only individual conductive interconnects. Regardless, a sacrificial etch-stop plug (not shown) may be formed horizontally in the lower portion 18L, wherein the channel opening 25 will be formed prior to the upper portion 18U and used in a manner similar to the sacrificial etch-stop line described above when forming the channel opening 25. A radially centered solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride) is displayed in the channel opening 25. Alternatively, and by way of example only, the radially centered portion within the channel opening 25 may contain void spaces (not shown) and / or be devoid of solid material (not shown).

[0026] In some embodiments, construction 10 may be considered to include a first region (e.g., as defined by...). Figure 3 and 4 (as shown) and the second zone 70 next to the first zone (e.g., as shown) Figure 7 (As shown in the diagram). The second region 70 may laterally contact the first region (not shown), or may be laterally spaced from the first region (e.g., laterally adjacent to the first region but not touching it, or laterally away from the first region and not touching it). The second region 70 may be located within one or more memory block regions (not shown). In some embodiments, the configuration 10 may be considered to include a first vertical stack (e.g., Figure 4 The stack 18* in the middle and the second vertical stack (e.g., stack 18* in the second zone 70), wherein the second stack includes an upper portion 18U and a lower portion 18L.

[0027] refer to Figure 8-10The conductive first sacrificial material 78 (not shown) has been electrically etched through trench 40 (e.g., by what some call "galvanic corrosion"). In one embodiment and as shown, such electrical etching has also been electrically etched through trench 40 to the conductive third material 80 (not shown and in presence). Alternatively, electrical etching does not preferentially etch through trench 40 to the conductive third material 80 (in presence and not shown) relative to the second material. For example, this may not occur if the conductive third material 80 and the conductive second material 79 have the same composition or have different compositions having different reduction potentials that are too close to each other (e.g., differing from each other by 0.3V or less). In one embodiment and as shown, electrical etching has occurred in the first region (e.g., Figure 8 And it has not yet occurred in Zone 70 ( Figure 10 For example, in the case where trench 40 is not formed in the second region 70 or the conductive first sacrificial material 78 is not etched in the second region 70.

[0028] Any suitable electrolyte and current etching conditions can be used, and a person skilled in the art can select such solutions and conditions depending on the composition of materials 79 and 78 (and 80, if present and where current etching is required). Ideally, the electrolyte is heated above room temperature to increase the rate of current etching, and in one such embodiment, the electrolyte is within 10°C of and below the boiling point of the electrolyte (whereby the electrolyte does not boil). In any case, the example electrolyte contains sulfuric acid, phosphoric acid, and ethylene glycol (e.g., a mixture of ethylene glycol and water). The electrolyte will preferentially current-etch conductive doped polysilicon (e.g., material 78) relative to, for example, tungsten silicide (e.g., material 79).

[0029] refer to Figure 11 and 12 And in one embodiment, it has passed through trench 40 ( Figure 11 The conductive second material 79 (not shown) is etched isotropically and non-currently in the unseen trench 40. Alternatively, the conductive second material 79 may not be etched in this way and / or at least some of the conductive second material may remain (not shown). In one embodiment and as shown, isotropic and non-current etching has occurred in the first region (e.g., Figure 11 And it has not yet occurred in Zone 70 ( Figure 12 For example, in the case where trench 40 is not formed in the second region 70 or the conductive second material 79 is not etched in the second region 70.

[0030] The bottom second layer is removed after current etching, and a conductive material is formed in the bottom first layer, which directly electrically couples the channel material in the individual channel material strings and the conductor material of the conductor layer together. In one embodiment, such conductive material is formed directly against the bottom of the conductive material of the conductive layer and directly against the top of the conductor material of the conductor layer. For example, and first referring to... Figure 13-15 The illustration shows a subsequent processing step in which, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in layer 20z to expose the sidewalls 41 of the channel material 36 of the channel material string 53 in the bottommost first layer 22z. Any of materials 30, 32, and 34 in layer 22z can be considered as a sacrificial material therein. As an example, consider an embodiment where the liner 78 is one or more insulating oxides (other than silicon dioxide), and memory cell materials 30, 32, and 34 are one or more of silicon dioxide and silicon nitride layers, respectively. In such examples, the depicted structure can be produced by selectively etching silicon dioxide and silicon nitride sequentially relative to another chemical substance using modified or different chemical substances. As an example, a 100:1 (by volume) water to HF solution will selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 (by volume) water to HF solution will selectively etch silicon nitride relative to silicon dioxide. Therefore, and in such examples, these etching chemicals can be used alternately, where the desired effect is achieved by… Figure 13-15 The example structure shown. Technicians can select other chemicals to etch different materials, where conditions require... Figure 13-15 The structure is shown in the diagram. Furthermore, if the second-lowest second layer 20x (if present and not shown) and the second-lowest second layer 20z (not shown) comprise one or more of silicon dioxide or silicon nitride, such layers can be removed as shown by the sequential etching described above. In one embodiment, and as shown, the removal of the second-lowest second layer 20z and the second-lowest second layer 20x has already occurred in the first region (e.g., Figure 13 And it has not yet occurred in Zone 70 ( Figure 15 ).

[0031] refer to Figure 16 and 17Conductive material 42 (e.g., conductive doped polysilicon) has been formed in the bottommost first layer 22z, and in one embodiment, it is formed directly against the sidewalls 41 of the channel material 36. In one embodiment, and as shown, such material has been formed directly against the bottom of the conductive material 47 of the conductive layer 21 and directly against the top of the conductive material 43 of the conductor layer 16, thereby directly electrically coupling the channel material 36 of the individual channel material strings 53 to the conductor material 43 of the conductor layer 16 and the conductive material 47 of the conductive layer 21. Subsequently, and by way of example, as with the removal of the sacrificial liner 78 (not shown), the conductive material 42 has been removed from the trench 40. The sacrificial liner 78 may be removed before the formation of the conductive material 42 (not shown).

[0032] refer to Figure 18-22 The material 26 (not shown) of the conductive layer 22* has been removed, for example, by isotropically etching it away through the trench 40, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, wherein material 26 is silicon nitride and other materials include one or more oxides or polysilicon). In an exemplary embodiment, the material 26 (not shown) in the conductive layer 22* is sacrificed and replaced by the conductive material 48, and subsequently removed from the trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0033] A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate locations of the transistors and / or memory cells 56 are... Figure 21 Parentheses are used to indicate this, and some are in Figure 18-20 The transistors and / or memory cells 56 are indicated by dashed outlines, where they are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in the individual conductive layer, and not shown). The conductive material 48 can be considered as having ends 50 corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Figure 21In the depicted embodiment, the control gate region 52 includes individual portions of the individual conductive lines 29. Materials 30, 32, and 34 can be considered as a memory structure 65 laterally located between the control gate region 52 and the channel material 36. In one embodiment, and as shown relative to the example “back gate” processing, the conductive material 48 of the conductive layer 22* is formed after the formation of the channel opening 25 and / or the trench 40. Alternatively, for example, relative to the “front gate” processing, the conductive material of the conductive layer may be formed before the formation of the channel opening 25 and / or the trench 40 (not shown).

[0034] A charge-blocking region (e.g., charge-blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge-blocking member in the memory cell may function to prevent charge carriers from flowing from the storage material (e.g., a floating gate material, a charge trapping material, etc.) to the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge-blocking member can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown in the example, the charge-blocking region includes an insulating material 30. By another example, the charge-blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein such storage material is insulating (e.g., in the absence of any different compositional materials between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the junction between the storage material and the conductive material of the control gate may be sufficient to act as a charge-blocking region in the absence of any separate compositional insulating material 30. Furthermore, the junction of the conductive material 48 and the insulating material 30 (when present) can together act as a charge blocking region, and alternatively or additionally act as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0035] In one embodiment and as shown, the lowermost surface of the channel material 36 of the channel material string 53 never directly abuts against any of the conductor materials 17 of the conductor layer 16. In one embodiment and as shown, the conductive material 42 directly abuts against the sidewall 41 of the channel material string 53.

[0036] Intermediate material 57 is formed in trench 40 and is thus laterally positioned between laterally adjacent memory blocks 58 and longitudinally along said laterally adjacent memory blocks. Intermediate material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. Such material may comprise one or more of insulating, semiconductive, and conductive materials, and in any case, can prevent the conductive layers 22 in the finished circuit system structure from shorting to each other. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intermediate material 57 may include through-hole arrays (not shown).

[0037] refer to Figure 18-23 In one embodiment and as shown, the formation of the conductive material 48 occurs in the first region ( Figure 19 ), rather than relative to the second vertical stack 18*( in the second zone 70). Figure 23 Therefore, in one embodiment, the resulting second vertical stack 18* in the second region 70 includes an upper portion 18U comprising alternating first insulating layers 22* and second insulating layers 20*. The lower portion 18L of the second vertical stack 18* includes a lowermost insulating layer 20z directly above the conductor material 17 of the conductor layer 16 and an adjacent layer 22z directly above the lowermost insulating layer 20z. The adjacent layer 22z includes a conductive first material 78 and a conductive second material 79, the conductive second material being directly electrically coupled to the conductive first material 78. The conductive first material and the conductive second material have different reduction potentials differing from each other by at least 0.5V, and the second vertical stack has its conductive first material and conductive second material retained in its adjacent layer within the finished construction of the memory array.

[0038] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described above.

[0039] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of manufacturing methods. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate having, forming, and / or having any of the properties described relative to the device embodiments.

[0040] In one embodiment, the integrated circuit system includes a memory array (e.g., 49) comprising strings (e.g., 56) of memory cells (e.g., 56), the integrated circuit system including laterally spaced memory blocks (e.g., 58), each of the laterally spaced memory blocks comprising a first vertical stack (e.g., ...). Figure 19The first vertical stack includes alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Strings (e.g., 49) of memory cells (e.g., 56) including channels (e.g., 53) extend through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines (e.g., 29). The second vertical stack (e.g., 18*) Figure 23 The layer 18* is adjacent to the first vertical stack and includes an upper portion (e.g., 18U) and a lower portion (e.g., 18L). The upper portion includes alternating first insulating layers (e.g., 22*) and second insulating layers (e.g., 20*). The lower portion includes a bottommost insulating layer (e.g., 20z) directly above the conductor material (e.g., 17) of the conductor layer (e.g., 16). An adjacent layer (e.g., 22z) is directly above the bottommost insulating layer and includes a first conductive material (e.g., 78) and a second conductive material (e.g., 79), the second conductive material being directly electrically coupled to the first conductive material. The first conductive material and the second conductive material have different reduction potentials that differ from each other by at least 0.5V. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] In one embodiment, the integrated circuit system includes a memory array (e.g., 49) comprising strings (e.g., 56) of memory cells (e.g., 56), the integrated circuit system including laterally spaced memory blocks (e.g., 58), each of the laterally spaced memory blocks comprising a first vertical stack (e.g., ...). Figure 19 The first vertical stack includes alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Strings (e.g., 49) of memory cells (e.g., 56) including channels (e.g., 53) extend through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines (e.g., 29). The second vertical stack (e.g., 18*) Figure 23The first vertical stack (18*) includes an upper portion (e.g., 18U) and a lower portion (e.g., 18L). The upper portion includes alternating first insulating layers (e.g., 22*) and second insulating layers (e.g., 20*). The lower portion includes a bottommost insulating layer (e.g., 20z) directly above the conductor material (e.g., 17) of the conductor layer (e.g., 16). An adjacent layer (e.g., 22z) is directly above the bottommost insulating layer and includes a first conductive material (e.g., 78) and a second conductive material (e.g., 79), the second conductive material being directly above and abutting the first conductive material. A third conductive material (e.g., 80) is directly above and abutting the second conductive material. Two of the first, second, and third conductive materials have a composition that is identical to each other. The two materials have a reduction potential that is different from one of the remaining materials that is not one of the two materials and differs from the remaining material by at least 0.5V. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] The above-described processing or construction can be viewed as an array of components formed as a single stack or single group of such components, or within a single stack or single group, which is above or part of an underlying substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the finished product construction at any location, and in some embodiments may be under the array (e.g., under-array CMOS). In any case, one or more additional such stacks / groups may be disposed or fabricated above and / or below the stacks / groups shown in the figures or described above. Furthermore, the arrays of components in different stacks / groups may be identical or different relative to each other, and the different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be disposed between vertically adjacent stacks / groups. Moreover, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0043] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0044] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “below,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means along a general direction (i.e., within 10 degrees) relative to the substrate being processed during manufacturing, and vertical is a direction generally orthogonal to it. “Just horizontal” refers to along the surface of the main substrate (i.e., not forming degrees with said surface) relative to the substrate being processed during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction inclined at least 45° from just horizontal. Furthermore, relative to a field-effect transistor, “vertically extending,” “horizontally extending,” “horizontally extending,” etc., refer to the orientation of the transistor's channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0045] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) between the two stated areas / materials / components. Moreover, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0046] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any material overlying them. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of one or more such compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0047] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions having different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, “different compositions” requires only that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, a material, region, or structure is “directly contacting” another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the words "above," "on top," "near," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervening material, area, or structure prevents the stated material, area, or structure from physically touching each other.

[0048] In this text, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” to each other. Another electronic component may be electrically coupled between and to a zone-material-component. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediary electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0049] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for components that have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with respect to any series of areas, components, and / or features, and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0050] Compositions of any of the conductive / conductor / conductive materials described herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" refers to any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds, or a combination thereof.

[0051] In this document, any use of “selective” for etching, removal, deposition, and / or forming is an action of one stated material relative to another stated material at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective forming is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1 up to at least a first 75 angstroms.

[0052] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0053] in conclusion

[0054] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming a conductive layer comprising a conductive material on a substrate. A lower portion of a stack is formed, wherein the stack ultimately comprises vertically alternating first and second layers above the conductive layer. The stack comprises laterally spaced memory block regions. The material of the first layer has a different composition than the material of the second layer. The lowermost first layer of the first layer comprises a conductive first sacrificial material. A conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that differ from each other by at least 0.5V. The lowermost second layer of the second layer is insulating and lies below the lowermost first layer. Vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion. A string of channel material is formed extending through the first and second layers of the upper portion to the lowermost first layer of the lower portion. Horizontally elongated trenches are formed in the stack, the horizontally elongated trenches being individually located between laterally adjacent memory block regions in the memory block regions and extending to the conductive first sacrificial material and the conductive second material in the lowermost first layer. The conductive first sacrificial material is etched through the trench using current etching. After current etching, the bottom second layer is removed. After the bottom second layer is removed, a conductive material is formed in the bottom first layer, which directly electrically couples the channel material in the individual channel material strings and the conductor material of the conductor layer together.

[0055] In some embodiments, an integrated circuit system including a memory array includes a memory cell string comprising laterally spaced memory blocks, each of the laterally spaced memory blocks individually comprising a first vertical stack comprising alternating insulating and conductive layers. The memory cell string includes a string of channel material extending through the insulating and conductive layers. The conductive layers individually comprise horizontally elongated conductive lines. A second vertical stack is adjacent to the first vertical stack. The second vertical stack includes an upper portion and a lower portion. The upper portion includes alternating first and second insulating layers. The lower portion includes a lowermost insulating layer directly above the conductive material of the conductive layer and an adjacent layer directly above the lowermost insulating layer. The adjacent layer includes a conductive first material. A conductive second material is directly electrically coupled to the conductive first material. The conductive first material and the conductive second material have different reduction potentials that differ from each other by at least 0.5V.

[0056] In some embodiments, an integrated circuit system including a memory array includes a memory cell string comprising laterally spaced memory blocks, each of the laterally spaced memory blocks individually comprising a first vertical stack comprising alternating insulating and conductive layers. The memory cell string includes a string of channel material extending through the insulating and conductive layers. The conductive layers individually comprise horizontally elongated conductive lines. A second vertical stack is adjacent to the first vertical stack. The second vertical stack includes an upper portion and a lower portion. The upper portion includes alternating first and second insulating layers. The lower portion includes a lowermost insulating layer directly above the conductive material of the conductive layer and an adjacent layer directly above the lowermost insulating layer. The adjacent layer includes a first conductive material. A second conductive material is directly above and abuts the first conductive material. A third conductive material is directly above and abuts the second conductive material. Two of the first, second, and third conductive materials have a composition that is identical to each other. The two materials have a reduction potential that is different from one of the remaining materials among the first conductive material, the second conductive material, and the third conductive material, and differs from the remaining material by at least 0.5V.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: A conductor layer comprising a conductor material is formed on a substrate; A lower portion is formed above the conductor layer, comprising a stack of vertically alternating first and second layers, the stack including laterally spaced memory block regions, wherein the material of the first layer has a different composition than that of the second layer, and the lowermost first layer of the first layer comprises: Conductive first sacrificial material; A conductive second material, which is directly electrically coupled to the conductive first sacrificial material; and The first conductive sacrificial material and the second conductive material have different reduction potentials that differ from each other by at least 0.5 V; The bottom second layer of the second layer is insulating and is located below the bottom first layer; The stacked upper portion forms vertically alternating first and second layers above the lower portion, and forms a channel material string that extends through the first and second layers in the upper portion to the lowermost first layer in the lower portion; Horizontal elongation trenches are formed in the stack, the horizontal elongation trenches being individually located between laterally adjacent memory block regions in the memory block regions and extending to the conductive first sacrificial material and the conductive second material in the bottom first layer; The conductive first sacrificial material is etched electrically through the trench; The bottom second layer is removed after the current-current etching; and After removing the bottom second layer, a conductive material is formed in the bottom first layer, which directly electrically couples the channel material in the individual channel material strings and the conductor material of the conductor layer together.

2. The method of claim 1, wherein the different reduction potentials differ from each other by at least 1.0 V.

3. The method according to claim 1, wherein the different reduction potentials differ from each other by no more than 4.0 V.

4. The method of claim 1, further comprising isotropically and non-currently etching the conductive second material through the trench prior to forming the conductive material.

5. The method of claim 1, wherein the first conductive sacrificial material and the second conductive material have different thicknesses relative to each other.

6. The method of claim 5, wherein the conductive second material is directly above the conductive first sacrificial material and is thinner than the conductive first sacrificial material.

7. The method of claim 1, wherein the first conductive sacrificial material and the second conductive material are in direct contact with each other.

8. The method of claim 1, wherein one of the conductive first sacrificial material and the conductive second material comprises conductive doped silicon, and the other of the conductive first sacrificial material and the conductive second material comprises a metallic material.

9. The method of claim 1, wherein the conductive second sacrificial material is directly above the conductive first sacrificial material, and the method further includes a conductive third material directly above the conductive first sacrificial material and the conductive second material and directly electrically coupled to the conductive first sacrificial material and the conductive second material.

10. The method of claim 9, wherein the current etching also current-etches the conductive third material through the trench.

11. The method of claim 9, wherein the current etching also does not preferentially etch the conductive third material through the trench relative to the second material.

12. The method of claim 9, wherein the conductive first sacrificial material and the conductive third material have a composition that is identical to each other.

13. The method of claim 9, wherein the first conductive sacrificial material and the third conductive material have a greater thickness than the second conductive material.

14. The method of claim 13, wherein the conductive first sacrificial material and the conductive third material have the same thickness relative to each other.

15. The method according to claim 1, wherein, The stack includes a first vertical stack and further includes a second vertical stack adjacent to the first vertical stack, the second vertical stack including an upper portion and a lower portion, the upper portion including alternating first and second insulating layers, the lower portion including a lowermost insulating layer directly above the conductor material of the conductor layer and an adjacent layer directly above the lowermost insulating layer, the adjacent layer including: The first conductive material; A conductive second material, which is directly electrically coupled to the conductive first material; The first conductive material and the second conductive material have different reduction potentials that differ from each other by at least 0.5 V; and The second vertical stack has a first conductive material and a second conductive material retained in its adjacent layers in the finished structure of the memory array.

16. An integrated circuit system comprising a memory array including strings of memory cells, comprising: The memory blocks are spaced laterally apart, each including a first vertical stack, the first vertical stack including alternating insulating and conductive layers, the memory cell string including a string of channel material extending through the insulating and conductive layers, the conductive layer including horizontally elongated conductive lines; A second vertical stack is located next to the first vertical stack. The second vertical stack includes an upper portion and a lower portion. The upper portion includes alternating first and second insulating layers. as well as The lower portion includes a lowermost insulating layer directly above the conductor material of the conductor layer and an adjacent layer directly above the lowermost insulating layer, the adjacent layer comprising: The first conductive material; A second conductive material, which is directly electrically coupled to the first conductive material; and The first conductive material and the second conductive material have different reduction potentials that differ from each other by at least 0.5 V.

17. The integrated circuit system of claim 16, wherein the different reduction potentials differ from each other by at least 1.0V.

18. The integrated circuit system of claim 16, wherein the different reduction potentials differ from each other by no more than 4.0V.

19. The integrated circuit system of claim 16, wherein the first conductive material and the second conductive material have different thicknesses relative to each other.

20. The integrated circuit system of claim 19, wherein the conductive second material is directly above the conductive first material and is thinner than the conductive first material.

21. The integrated circuit system of claim 16, wherein the first conductive material and the second conductive material are in direct contact with each other.

22. The integrated circuit system of claim 16, wherein one of the conductive first material and the conductive second material comprises conductive doped silicon, and the other of the conductive first material and the conductive second material comprises a metallic material.

23. An integrated circuit system comprising a memory array including strings of memory cells, comprising: The memory blocks are spaced laterally apart, each including a first vertical stack, the first vertical stack including alternating insulating and conductive layers, the memory cell string including a string of channel material extending through the insulating and conductive layers, the conductive layer including horizontally elongated conductive lines; A second vertical stack is located next to the first vertical stack. The second vertical stack includes an upper portion and a lower portion. The upper portion includes alternating first and second insulating layers. as well as The lower portion includes a lowermost insulating layer directly above the conductor material of the conductor layer and an adjacent layer directly above the lowermost insulating layer, the adjacent layer comprising: The first conductive material; A second conductive material is located directly above and abutting the first conductive material. A conductive third material, which is directly above and abuts the conductive second material; and Two of the conductive first material, the conductive second material, and the conductive third material have a composition that is relatively identical to each other; the two materials have a reduction potential that is different from one of the remaining materials that is not one of the two materials and differs from the remaining material by at least 0.5V.

Images