Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly having a first tier. The first tier has first memory cell tiers alternating with first insulating tiers. A second tier is above the first tier. The second tier has second memory cell tiers alternating with second insulating tiers. A cell material pillar passes through the first tier and the second tier. A memory cell is along a region of the first memory cell tiers and the second memory cell tiers and includes the cell material pillar. An intermediate tier is between the first tier and the second tier. The intermediate tier includes a buffer region adjacent to the cell material pillar. The buffer region includes a composition different from a first insulating material and a second insulating material and different from a first conductive region and a second conductive region. Some embodiments include a method of forming an integrated assembly.

Description

[0001] Relevant patent data

[0002] This application claims priority and benefit to U.S. Patent Application No. 16 / 984,457, filed August 4, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] A method for forming an integrated assembly (e.g., an integrated memory device). Integrated assembly. Background Technology

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers may store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory in solid-state drives (SSDs) instead of conventional hard disk drives (HDDs). As yet another example, flash memory is prevalent in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized, and enables manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0005] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0006] Before specifically describing NAND, it may be helpful to describe more generally the relationships within an integrated arrangement of memory arrays. Figure 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transfer information to and from memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in memory cells 1003 need to be accessed. Sensing amplifier circuitry 1015 is used to determine the value of the information read from memory cells 1003. I / O circuitry 1017 transmits information values ​​between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 represent values ​​of information read from or to be written to memory cells 1003. Other devices can communicate with device 1000 via I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 controls memory operations to be performed on memory cells 1003 and utilizes signals on control line 1020. Device 1000 can receive power supply voltage signals Vcc and Vss on first power line 1030 and second power line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that represent information to be read from or programmed into memory cell 1003. Column decoder 1008 can selectively activate CSEL1 to CSELn signals based on address signals A0 to AX on address line 1009. Selection circuit 1040 can select signals on first data line 1006 and second data line 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple charge storage device strings. In a first direction (ZZ′), each charge storage device string may include, for example, thirty-two charge storage devices stacked one on top of the other, where each charge storage device corresponds to, for example, one of thirty-two layers (e.g., layers 0 to 31). The charge storage devices of the corresponding strings may share a common channel region, for example, a common channel region formed in a pillar of a corresponding semiconductor material (e.g., polysilicon), the charge storage device strings being formed around the corresponding semiconductor material pillar. In a second direction (XX′), for example, each of sixteen first groups of multiple strings may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., “global gate control (CG) lines,” also referred to as word lines WL). Each of the access lines may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same level) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. On a third direction (YY′), each of eight second groups of multiple strings may include sixteen strings coupled by corresponding ones of eight data lines. The size of a memory block may include 1,024 pages, totaling approximately 16 MB (e.g., 16 word lines × 32 levels × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, levels, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the XX′ direction, the memory block comprising fifteen charge storage device strings from one of sixteen first groups of strings described in Figure 2. The multiple strings of the multiple memory blocks 300 can be grouped into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile column 1, tile column j, and tile column K, where each subset (e.g., tile column) comprises a “partial block” (sub-block) of the memory block 300. A global drain-side selected gate (SGD) line 340 can be coupled to the SGDs of the multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding ones of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, and 336 can simultaneously couple or disconnect the SGD of the corresponding sub-block (e.g., a tile array) string, independent of the SGD of the strings of other sub-blocks. A global source-side select gate (SGS) line 360 ​​can be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​can be coupled to multiple sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers 322, 324, and 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a tile array). Each of the sub-SGS drivers 322, 324, and 326 can simultaneously couple or disconnect the SGS of the corresponding sub-block (e.g., a tile array) string, independent of the SGS of the strings of other sub-blocks. A global access line (e.g., a global CG line) 350 can couple to a charge storage device corresponding to a corresponding level of each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a counterpart among a plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers may simultaneously couple or disconnect the charge storage device corresponding to the respective sub-block and / or level, independently of other partial blocks and / or other levels of charge storage devices. Charge storage devices corresponding to the respective subset (e.g., partial block) and the respective level may include a “partial level” of charge storage devices (e.g., a single “patch”). A string corresponding to the respective subset (e.g., partial block) may be coupled to a counterpart among sub-sources 372, 374, and 376 (e.g., “patch source”), wherein each sub-source is coupled to a respective power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic diagram in FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. N Charge storage transistors can use floating gate materials (e.g., polysilicon) to store charge, or they can use charge trapping materials (e.g., silicon nitride, metal nanodots, etc.) to store charge.

[0012] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in source-to-drain series between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, while each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated by the boxes in FIG. 4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to a bit line (i.e., a digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to a word line 202. The charge storage transistor 208 is a column of those transistors within the NAND string 206 coupled to a given positioning line 228. The charge storage transistor 208 behaves in conjunction with those transistors coupled to a given word line 202.

[0016] It is desirable to develop improved methods for forming integrated memories (e.g., NAND memory). It is also desirable to develop improved memory devices. Attached Figure Description

[0017] Figure 1 shows a block diagram of a prior art memory device having a memory array containing memory cells.

[0018] Figure 2 shows a schematic diagram of the prior art memory device of Figure 1 in the form of a 3D NAND memory device.

[0019] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the XX′ direction.

[0020] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0021] Figure 5 and 5A This is a schematic cross-sectional side view of an instance integration assembly in the instance processing stage of an instance embodiment method for forming an instance memory device. Figure 5 ) and schematic top view ( Figure 5A ). Figure 5 The cross-sectional side view is along Figure 5A Line 5-5.

[0022] Figure 6 yes Figure 5 The instance integration assembly is in Figure 5 A schematic cross-sectional side view of the instance processing stage following the processing stage.

[0023] Figure 7 and 7A yes Figure 5 The instance integration assembly is in Figure 6 A schematic cross-sectional side view of the instance processing stage following the processing stage. Figure 7 ) and schematic top view ( Figure 7A ). Figure 7 The cross-sectional side view is along Figure 7A Line 7-7.

[0024] Figure 8 yes Figure 5 The instance integration assembly is in Figure 7 A schematic cross-sectional side view of the instance processing stage following the processing stage.

[0025] Figure 9 and 9A yes Figure 5 The instance integration assembly is in Figure 8 A schematic cross-sectional side view of the instance processing stage following the processing stage. Figure 9) and schematic top view ( Figure 9A ). Figure 9 The cross-sectional side view is along Figure 9A Line 9-9.

[0026] Figure 10-15 yes Figure 5 The instance integration assembly is in Figure 9 A schematic cross-sectional side view of the instances following the processing stage.

[0027] Figure 16 and 16A yes Figure 5 The instance integration assembly is in Figure 15 A schematic cross-sectional side view of the instance processing stage following the processing stage. Figure 16 ) and schematic top view ( Figure 16A ). Figure 16 The cross-sectional side view is along Figure 16A Line 16-16.

[0028] Figure 17-20 yes Figure 5 The instance integration assembly is in Figure 8 A schematic cross-sectional side view of the instances following the processing stage. Detailed Implementation

[0029] Some embodiments include a method of forming a memory having two or more layers stacked on top of each other, and some embodiments include a configuration having two or more layers stacked on top of each other. References Figure 5-20 Describe an example implementation.

[0030] See Figure 5 The integrated assembly 10 includes a conductive structure 12. The conductive structure 12 may be a source structure similar to the source structure described above in the background section. The conductive structure 12 may include any suitable conductive composition, and in some embodiments, may include a conductive doped semiconductor material (e.g., n-type silicon) on a metallic material (e.g., one or both of tungsten and tungsten silicide).

[0031] The source structure 12 may be supported by a semiconductor substrate (substrate). The semiconductor substrate is not shown in the figures of this disclosure for simplicity. The semiconductor substrate may include any suitable semiconductor composition; and in some embodiments may include single-crystal silicon.

[0032] An alternating stack 14 of first layers (levels, layers) 16 and second layers 18 is formed over the conductive structure 12. The stack 14 may include any suitable number of alternating layers 16 and 18. The first layer 16 ultimately becomes a conductive level for the memory arrangement. Any suitable number of layers 16 may exist to form the desired number of conductive levels. In some embodiments, the number of layers 16 may be 8, 16, 32, 64, etc.

[0033] The first layer 16 includes a first material 20. Such a first material may include any suitable composition, and in some embodiments may include silicon nitride, be composed primarily of silicon nitride, or be composed of silicon nitride.

[0034] The second layer 18 includes a second material 22. This material may be an insulating material and may include any suitable composition. In some embodiments, the second material 22 may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide.

[0035] In some embodiments, materials 20 and 22 may be referred to as a first material and an insulating second material, respectively.

[0036] Layers 16 and 18 may have any suitable thickness; and may have the same thickness as each other, or may have different thicknesses relative to each other. In some embodiments, layers 16 and 18 may have a vertical thickness in the range of about 10 nanometers (nm) to about 400 nm.

[0037] Stack 14 is spaced apart from conductive structure 12 by gaps. These gaps indicate that one or more additional components, structures, etc., may exist between the illustrated area of ​​stack 14 and conductive structure 12. Such additional structures may include, for example, a source-side selected gate (SGS) structure. An SGS structure (not shown) may be present... Figure 5 and 5A The processing stage that follows the processing stage is formed.

[0038] One of the first levels 16 is the uppermost one in the first level and is marked 16a to distinguish it from the other first levels. One of the first levels is the second to last first level and is marked 16b to distinguish it from the other first levels.

[0039] One of the second levels is the uppermost one in the second level, and is marked as 18a to distinguish it from the other second levels. The uppermost second level 18a is between the penultimate first level 16b and the uppermost first level 16a.

[0040] Stack 14 may be referred to as a first stack. First layer 24 may be considered to include at least a portion of the first stack 14. In some embodiments, first layer 24 may include the entirety of the first stack 14. In some embodiments, layers 16a, 16b, and 18a may be considered to correspond to the middle region 26. Lower portion 28 of the first stack 14 may be considered to correspond to the portion below the middle region 26.

[0041] The intermediate region 26 described herein includes both of the first level 16 and one of the second level 18. Generally, the intermediate region may include one or more of the first level and one or more of the second level.

[0042] The channel material pillars will eventually extend through stack 14, and gaps will be provided between the channel material pillars to divide the pillars within the memory block. Instance locations of channel material pillars are illustrated in area 30, and instance locations of gaps are illustrated in area 32.

[0043] Figure 5A exhibit Figure 5 The image shows a top view of assembly 10, illustrating an example arrangement of channel material pillar locations 30 and slot locations 32. Slot location 32 can be considered as defining the edges of memory block regions 34 and 36, and channel material pillar locations 30 can be considered as being within such memory block regions. In some embodiments, portions of stack 14 can be considered as being within memory block regions 34 and 36, and portions can be considered as being within slot regions between memory block regions.

[0044] See Figure 6 Trench 38 is formed to extend into intermediate region 26 (and in the illustrated embodiment, it is shown to extend through layers 16a, 16b, and 18a). Trench 38 extends substantially entirely across memory block regions 34 and 36.

[0045] Figure 6 The illustrated embodiment has a groove 38 extending through both of the first layers 16. Generally, the groove 38 will extend through one or more of the first layers and will fall on (or extend into) one of the second layers 18 (i.e., the bottom periphery of the groove will include the material 22 of the second layer 18).

[0046] The formation of trench 38 removes some of the intermediate region 36 to retain the remaining region (partial) 37 of the intermediate region 36 between the trenches 38. The remaining region 37 can be considered as a portion containing layers 16a, 16b and 18a.

[0047] See Figure 7A buffer material 40 is formed within the trench 38. In some embodiments, the buffer material 40 may be formed to fill (or overfill) the trench 38, and then planarization (e.g., chemical mechanical polishing, CMP) may be used to remove any excess material 40 and form the illustrated planarized surface 41 extending across the remaining area 37 of the uppermost first layer 16a and the buffer material 40.

[0048] The cushioning material 40 may include any suitable composition. The cushioning material may be a semiconductive composition (e.g., may include silicon, germanium, etc.), an insulating composition (e.g., may include hafnium dioxide, zirconium oxide, etc.), or a conductive composition (e.g., may include tungsten, titanium, tungsten silicide, etc.).

[0049] In some embodiments, the buffer material 40 may include one or more of silicon, carbon-doped silicon nitride, aluminum-doped magnesium oxide, hafnium dioxide, zirconium oxide, and manganese oxide, and may be primarily composed of one or more of these, or may be composed of one or more of these. The carbon-doped silicon nitride may include a carbon concentration ranging from about 5 atomic percent (atomic %) to about 15 atomic percent, and in some embodiments may include a carbon concentration ranging from about 8 atomic percent to about 9 atomic percent. The aluminum-doped magnesium oxide may include an aluminum concentration greater than 0 atomic percent, and in some embodiments may include an aluminum concentration ranging from greater than 0 atomic percent to about 15 atomic percent.

[0050] In some embodiments, the cushioning material 40 may include a metal, be primarily composed of a metal, or be composed of a metal. For example, the cushioning material 40 may include one or both of titanium and tungsten, be primarily composed of one or both of them, or be composed of one or both of them.

[0051] In some embodiments, the cushioning material 40 may include one or more of metal oxides, metal carbides, metal borides, metal nitrides, and metal silicides, and may be primarily composed of one or more of them. For example, the cushioning material 40 may include one or more of tungsten nitrides, titanium nitrides, tungsten silicides, and titanium silicides, and may be primarily composed of one or more of them.

[0052] Figure 7A exhibit Figure 7 The top view of assembly 10 shows that the cushioning material 40 extends substantially entirely across memory block regions (memory block locations) 34 and 36. In some embodiments, memory block regions 34 and 36 may be considered to correspond to memory blocks of the type described above with reference to Figures 1-4.

[0053] See Figure 8The opening 42 is formed to extend through the buffer material 40 and through the lower portion 28 of the stack 14. The opening 42 can be formed by any suitable processing. For example, a masking material (not shown) can be provided to define the location of the opening 42, and the opening 42 can be formed to extend through materials 20, 22, and 40 by one or more suitable etching processes, after which the masking material can be removed to retain... Figure 8 The configuration described herein. In some embodiments, opening 42 may be referred to as a first opening to distinguish it from other openings formed in subsequent processing stages. Opening 42 is formed in region 30 ( Figure 7 ) place.

[0054] See Figure 9 Sacrificial material 44 is formed within opening 42. Sacrificial material 44 may comprise any suitable composition that can be selectively removed relative to materials 20, 22, and 40. For example, in some embodiments, sacrificial material 44 may comprise a substance selected from the group consisting of carbon, silicon, metals (e.g., tungsten), etc.

[0055] The planarization surface 45 is formed to extend across the sacrificial material 44, the cushioning material 40, and the uppermost layer 16a. The planarization surface 45 can be formed by any suitable process, such as CMP. The sacrificial material 44 can be considered as being configured to extend through the plug 47 of the stack 14.

[0056] Figure 9A exhibit Figure 9 A top view of the configuration, showing plugs 47 arranged in a tightly packed configuration across memory block regions 34 and 36.

[0057] See Figure 10 A second stack 46, consisting of alternating third layers (levels, layers) 48 and fourth layers 50, is formed above the first stack 14. The stack 46 may include any suitable number of alternating layers 48 and 50. The third layer 48 ultimately becomes a conductive level for the memory arrangement. Any suitable number of layers 48 may exist to form the desired number of conductive levels. In some embodiments, the number of layers 48 may be 8, 16, 32, 64, etc.

[0058] The third layer 48 includes a third material 52. This third material may include any suitable composition, and in some embodiments may include silicon nitride, be primarily composed of silicon nitride, or be composed of silicon nitride. Thus, the third material 52 may include the same composition as the first material 20.

[0059] The fourth layer 50 includes a fourth material 54. This material may be an insulating material and may include any suitable composition. In some embodiments, the fourth material 54 may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide. In some embodiments, the insulating fourth material 54 may include the same composition as the insulating second material 22.

[0060] Layers 48 and 50 may have the same thickness as described above relative to layers 16 and 18.

[0061] The second stack 46 can be considered as being included by the second layer 56.

[0062] See Figure 11 The second opening 58 is formed to extend through the second stack 46. The second opening 58 extends into the sacrificial material 44.

[0063] exist Figure 11 In the illustrated embodiment, one of the second openings 58 is designated 58a and is not aligned with the underlying first opening 42. The other of the second openings 58 is designated 58b and is aligned with the underlying opening 42.

[0064] The buffer material 40 forms a hard termination layer (i.e., an etch termination layer) that prevents the misaligned area of ​​opening 58a from penetrating the intermediate area 26 into the underlying material of the first stack 14. This avoids problems associated with conventional processes (i.e., processes lacking material 40 in area 26). These problems may include areas where the misaligned portion of opening 58a causes scraping of material 20 and 22 within the upper area of ​​the second stack 14, resulting in the removal of such material. This scraping can adversely affect the configuration of structures subsequently formed within openings 58 / 42, potentially leading to impaired device performance or even device inoperability. Therefore, the treatment described herein advantageously mitigates or prevents problems associated with conventional manufacturing processes.

[0065] See Figure 12 Remove sacrificial material 44 ( Figure 11 Therefore, the second opening 58 can be considered as extending through the sacrificial material 44. In some embodiments, the removal of the sacrificial material can be considered as reopening the first opening 42. In some embodiments, the second opening 58 together with the reopened first opening 42 can be considered as forming a guide post opening 60 extending through the first stack 14 and the second stack 56. The guide post opening including the misaligned opening 58a is designated as 60a, and the other guide post opening is designated as 60b. The guide post openings 60a and 60b have different shapes relative to each other.

[0066] exist Figure 12 In the illustrated embodiment, material 40 forms a step 62 within the guide post opening 60a.

[0067] See Figure 13 A cell material pillar 64 is formed within the pillar opening 60. The cell material pillar includes a channel material 66, a gate dielectric material (insulating material, tunneling material) 68, a charge storage material 70, and a charge blocking material 72. The channel material 66 can be considered as configured as the channel material pillar 74. The channel material pillar 74 is electrically coupled to the conductive structure 12 and, in some embodiments, can directly contact the conductive structure 12. Materials 66, 68, 70, and 72 can have any suitable thickness. Materials 66, 68, 70, and 72 in… Figure 13 The diagram illustrates that they are shown to be of approximately the same thickness, but typically two or more of the materials will have different thicknesses relative to each other. The channel material column 74 is shown to be hollow and laterally surrounds the insulating material 76.

[0068] The channel material 66 may comprise any suitable semiconductor composition. In some embodiments, the channel material 66 may comprise one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., constitute primarily of one or more of them, or consist of one or more of them; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the channel material 66 may comprise silicon. Silicon may be in any suitable crystalline state (e.g., single crystal, polycrystalline, amorphous, etc.).

[0069] The gate dielectric material (tunneling material) 68 may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, silicon nitride, aluminum oxide, hafnium dioxide, zirconium oxide, etc. In some embodiments, material 68 may include a bandgap engineered laminate.

[0070] The charge storage material 70 may include any suitable composition, and in some embodiments may include a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.).

[0071] The charge blocking material 72 includes any suitable composition, and in some embodiments may include one or both of silicon dioxide and silicon oxynitride.

[0072] The insulating material 76 may include any suitable composition, and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide. In some embodiments, the insulating material 76 may be omitted, and the channel material post 74 may be a solid post instead of the hollow post illustrated.

[0073] In some embodiments, unit materials 68, 70 and 72 are formed within the opening 60 to line the opening, and then channel material 66 is formed within the lining opening.

[0074] In the illustrated embodiment, the unit material 72 (i.e., the charge-blocking material) is in direct contact with the buffer material 40. Furthermore, in Figure 13 In the illustrated embodiment, the area of ​​the unit material column 64 formed in the opening 60a is above the step 62 and directly abuts against such a step.

[0075] See Figure 14 The gap 78 is formed at gap position 32 ( Figure 7 and 7A )Inside.

[0076] See Figure 15 Remove the first material 20 and the third material 52 ( Figure 14 A void 80 is formed along layers 16 and 48. The first material 20 and the third material 52 can be removed using one or more etchants flowing into the void 78. In some embodiments, the first material 20 and the third material 52 comprise silicon nitride and are removed using phosphoric acid.

[0077] See Figure 16 80 (gap) Figure 15 The inner lining is a dielectric barrier material 82. The dielectric barrier material 82 may include any suitable composition; and may include, for example, one or more high-k compositions (e.g., alumina, hafnium dioxide, zirconium oxide, etc.). The term "high-k composition" means a composition with a dielectric constant greater than that associated with silicon dioxide (i.e., greater than about 3.9).

[0078] Conductive materials 84 and 86 are formed within the liner voids. Conductive materials 84 and 86 may comprise any suitable conductive composition; for example, one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, conductive material 86 may comprise a metal-containing core (e.g., a tungsten-containing core), and conductive material 84 may comprise a metal nitride (e.g., titanium nitride, tungsten nitride, etc.) along the periphery of the metal-containing core.

[0079] Figure 14-16 The process can be considered as combining the first material 20 and the third material 52 ( Figure 14 At least some of them are replaced with one or more conductive materials (e.g., conductive materials 84 and 86) to form Figure 16 The conductive layers are 16 and 48.

[0080] An insulating material 88 is formed within the gap 78. The insulating material 88 may comprise any suitable composition, and in some embodiments may comprise silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide. Although the gap 78 is shown as being filled with a single homogeneous material, in other embodiments, the gap may be filled with a laminate of two or more different materials. For example, in some embodiments, the gap may be filled with a suitable material to form three panels within each of the gaps. The three panels may comprise a central conductive panel (e.g., a panel comprising conductive doped silicon) sandwiched between a pair of insulating outer panels (e.g., panels comprising silicon dioxide).

[0081] The lower layer (first layer) 24 includes a stack 14 of alternating conductive layers 16 and insulating layers 18, and the upper layer (second layer) 56 includes a stack 46 of alternating conductive layers 48 and insulating layers 50. The conductive layers 16 of the first layer 24 may be referred to as the first conductive layer (or the first memory cell layer), and the conductive layers 48 of the second layer 56 may be referred to as the second conductive layer (the second memory cell layer).

[0082] The first memory cell level 16 can be considered as including a first conductive region 90 containing conductive materials 84 and 86, and the second memory cell level 48 can be considered as including a second conductive region 92 containing conductive materials 84 and 86. The first conductive region 90 and the second conductive region 92 can be identical to each other.

[0083] Cell material pillars 64 pass through the first layer 24 and the second layer 56. Memory cells 94 run along memory cell layers 16 and 48 and include areas of cell material pillars 64. Memory cells 94 can be considered as instances of NAND memory cells. The illustrated NAND memory cells 94 are arranged as vertically extending strings of memory cells.

[0084] In some embodiments, zone 26 may be considered as corresponding to an intermediate layer between the first layer 24 and the second layer 56. Such an intermediate layer includes a buffer 96 comprising a buffer material 40. The buffer 96 is adjacent to a unit material pillar 64. In some embodiments, the material 40 of the buffer comprises a composition different from the compositions of insulating materials 22 and 54 and different from the compositions of conductive materials 84 and 86.

[0085] Buffer 96 has a vertical thickness T equal to the combined vertical thickness of layers 16a, 16b, and 18a. In other words, buffer 96 has a vertical thickness equal to the combined vertical thickness of two of the memory cell layers (specifically, memory cell layers 16a and 16b) and one of the insulation layers (specifically, insulation layer 18a). In other embodiments, buffer 96 may have a vertical thickness equal to... Figure 16 The vertical thickness is described in the text as having different vertical thicknesses.

[0086] exist Figure 16 In the illustrated embodiment, one of the unit material pillars is designated 64a. A portion of this unit material pillar lies above step 62. Step 62 can be considered a segment of buffer zone 96. Therefore, the portion of the unit material pillar above step 62 can be considered to lie along and directly against the upper surface of buffer zone 96.

[0087] Figure 16A exhibit Figure 16 A top view of the upper layer 50, showing the cell material pillars 64 arranged in a tightly packed configuration within memory blocks 34 and 36.

[0088] Figure 16 and 16A The integrated assembly 10 can be considered as part of a memory device (e.g., a NAND memory device).

[0089] Figure 13 The processing stage is shown to be formed in a single step at the first opening 42 and the second opening 58. Figure 12 The channel material pillar 74 is located within the lower opening 42. In other embodiments, a portion of the channel material pillar may be formed within the lower opening 42, followed by the formation of an upper stack 46, and then an additional portion of the channel material pillar may be formed within the upper stack 46 and the additional portion may be joined to the lower portion of the channel material pillar. (See reference...) Figure 17-20 Examples of such embodiments are described.

[0090] See Figure 17 The integrated assembly 10 is shown as being in a followable position. Figure 8 The processing stage of the process. It can be done at opening 42 ( Figure 8 The lower portion of a unit material pillar 64 is formed within the unit material pillar 64, and then a sacrificial material 44 is formed above such a lower portion of the unit material pillar 64. The sacrificial material 44 is configured to extend into a plug 47 in the buffer 96. A planarized surface 45 is formed to extend across the upper surface of the assembly 10.

[0091] See Figure 18 A second stack 46 is formed on top of the first stack 14. Then, using a method similar to the one described above... Figure 11 The described process forms openings 58a and 58b extending through the second stack to the sacrificial material 44.

[0092] See Figure 19 Remove sacrificial material 44 ( Figure 18 This extends the opening 58 to the upper surface of the unit material column 64.

[0093] See Figure 20 The upper portion of the unit material column 64 is formed at the opening 58. Figure 19 Inside. The upper part of unit material column 64 is already in contact with... Figure 17 The lower part is joined together during the processing stage. Figure 20 Each of the unit material columns can be considered to be included in Figure 17 The lower part (area) 98 formed during the processing stage, and in Figure 20 The upper part (area) 100 formed during the processing stage. Figure 20 Assembly 10 can undergo a process similar to the above reference. Figure 14-16 Further processing described herein is performed to form memory cells along level 16 (e.g., Figure 16 Memory unit 94).

[0094] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0095] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0096] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be to provide linguistic variation within this disclosure to simplify the premises in the appended claims, rather than to indicate any significant chemical or electrical differences.

[0097] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the appended claims.

[0098] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0099] Unless otherwise specified, the accompanying cross-sectional drawings show only the features within the cross-sectional plane and not the material behind the cross-sectional plane in order to simplify the drawings.

[0100] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intermediate structure. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intermediate structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate upright alignment.

[0101] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally to the upper surface of the substrate, or it may extend non-substantially to the upper surface of the substrate.

[0102] Some embodiments include an integrated assembly having a first layer. The first layer has a first memory cell layer alternating with a first insulating layer. The first memory cell layer includes a first conductive region. The first insulating layer includes a first insulating material. A second layer is above the first layer. The second layer has a second memory cell layer alternating with a second insulating layer. The second memory cell layer includes a second conductive region. The second insulating layer includes a second insulating material. Cell material pillars pass through the first layer and the second layer. Memory cells are located along the first memory cell layer and the second memory cell layer and include regions of the cell material pillars. An intermediate layer is located between the first layer and the second layer. The intermediate layer includes a buffer adjacent to the cell material pillars. The buffer contains a composition different from the first insulating material and the second insulating material, and different from the first conductive region and the second conductive region. The buffer has a vertical thickness approximately equal to the combined vertical thickness of at least two of the first memory cell layers and one of the first insulating layers.

[0103] Some embodiments include a method of forming an integrated assembly. A first stack with alternating first and second layers is formed. The first and second layers each include a first material and an insulating second material. One of the first layers is the uppermost first layer. Another of the first layers is below the uppermost first layer and is the penultimate first layer. One of the second layers is the uppermost second layer and lies between the penultimate second first layer and the uppermost first layer. The lower portion of the first stack is below the penultimate second first layer. A trench is formed to extend through the uppermost first layer, the uppermost second layer, and the penultimate second first layer. A cushioning material is formed within the trench. A first opening is formed to extend through the cushioning material and through the lower portion of the first stack. A sacrificial material is formed within the first opening. A second stack with alternating third and fourth layers is formed above the first stack, the cushioning material, and the sacrificial material. The third and fourth layers each include a third material and an insulating fourth material. A second opening is formed to extend through the second stack to the sacrificial material. The second opening extends through the sacrificial material. A channel material pillar is formed within the first and second openings. Replace at least some of the first and third materials with one or more conductive materials.

[0104] Some embodiments include a method of forming an integrated assembly. A first stack with alternating first and second layers is formed. The first and second layers each include a first material and an insulating second material, respectively. A portion of the first stack is within a memory block location. A trench is formed extending through one or more of the first layers and having a bottom along one of the second layers. A lower portion of the first stack is below the trench. The trench extends substantially across the memory block location. A buffer material is formed within the trench. A first opening is formed extending through the buffer material and through the lower portion of the first stack. A sacrificial material is formed within the first opening. A second stack with alternating third and fourth layers is formed above the first stack, the buffer material, and the sacrificial material. The third and fourth layers each include a third material and an insulating fourth material, respectively. A second opening is formed extending through the second stack to the sacrificial material. The second opening extends through the sacrificial material. The extended second opening merges with the first opening to form a post opening extending through the first and second stacks. A cell material post is formed within the post opening. A slot is formed along the edge of the memory block location. The first and third materials are removed using one or more etchants flowing into the slot. The removal of the first and third materials creates voids within the first and third layers. One or more conductive materials are then formed within these voids.

[0105] As specified, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: The first layer has a first memory cell layer that alternates with the first insulating layer; The first memory cell level includes a first conductive region; The first insulation layer includes a first insulating material; A second layer is located above the first layer; the second layer has a second memory cell layer alternating with a second insulating layer; the second memory cell layer includes a second conductive region; the second insulating layer includes a second insulating material. A unit material column that passes through the first layer and the second layer; a memory cell along the first memory cell hierarchy and the second memory cell hierarchy and including the unit material column; and An intermediate layer, located between the first layer and the second layer; the intermediate layer includes a buffer adjacent to the cell material pillars; the buffer contains a composition different from the first insulating material and the second insulating material and different from the first conductive region and the second conductive region; the buffer has a vertical thickness approximately equal to the combined vertical thickness of at least two of the first memory cell layers and one of the first insulating layers.

2. The integrated assembly of claim 1, wherein the unit material pillar comprises a channel material and a charge trapping material.

3. The integrated assembly of claim 1, wherein the composition of the buffer is insulating.

4. The integrated assembly of claim 1, wherein the composition of the buffer is conductive.

5. The integrated assembly of claim 1, wherein the composition of the buffer is semi-conductive.

6. The integrated assembly of claim 1, wherein the composition of the buffer comprises one or more of silicon, carbon-doped silicon nitride, aluminum-doped magnesium oxide, hafnium dioxide, zirconium oxide, and manganese oxide.

7. The integrated assembly of claim 1, wherein the composition of the buffer comprises carbon-doped silicon nitride, wherein the concentration of carbon in the silicon nitride is in the range of about 5 atomic% to about 15 atomic%.

8. The integrated assembly according to claim 7, wherein the concentration of carbon present in silicon nitride is in the range of about 8 atomic% to about 9 atomic%.

9. The integrated assembly of claim 1, wherein the composition of the buffer comprises metal.

10. The integrated assembly of claim 1, wherein the composition of the buffer comprises one or more of a metal oxide, a metal carbide, a metal boride, and a metal silicide.

11. The integrated assembly of claim 1, wherein the unit material column comprises a portion along and directly abutting the upper surface of the buffer.

12. The integrated assembly of claim 1, wherein the unit material pillar is one of a plurality of unit material pillars within the memory block, and wherein the buffer extends substantially entirely across the memory block.

13. The integrated assembly of claim 1, wherein the first insulating material and the second insulating material are the same composition as each other.

14. The integrated assembly of claim 1, wherein the first insulating material and the second insulating material comprise silicon dioxide.

15. A method of forming an integrated assembly, comprising: A first stack is formed with alternating first and second layers; the first and second layers respectively include a first material and an insulating second material; one of the first layers is the uppermost first layer; one of the first layers is below the uppermost first layer and is the penultimate first layer; one of the second layers is the uppermost second layer and is between the penultimate second layer and the uppermost first layer; the lower portion of the first stack is below the penultimate second layer; The trench is formed to extend through the uppermost first layer, the uppermost second layer, and the penultimate first layer; A cushioning material is formed within the trench; The first opening is formed to extend through the cushioning material and through the lower portion of the first stack; Sacrificial material is formed within the first opening; A second stack with alternating third and fourth layers is formed above the first stack, the cushioning material, and the sacrificial material; the third and fourth layers each comprise a third material and an insulating fourth material, respectively. The second opening is formed to extend through the second stack into the sacrificial material; The second opening extends through the sacrificial material; Channel material columns are formed within the first opening and the second opening; as well as Replace at least some of the first material and the third material with one or more conductive materials.

16. The method of claim 15, wherein the cushioning material is insulating.

17. The method of claim 15, wherein the buffer material is conductive.

18. The method of claim 15, wherein the buffer material is semi-conductive.

19. The method of claim 15, wherein the buffer material comprises one or more of silicon, carbon-doped silicon nitride, aluminum-doped magnesium oxide, hafnium dioxide, zirconium oxide, and manganese oxide.

20. The method of claim 15, wherein the cushioning material comprises a metal.

21. The method of claim 15, wherein the buffer material comprises one or more of a metal oxide, a metal carbide, a metal boride, and a metal silicide.

22. The method of claim 15, wherein the cushioning material comprises one or more of tungsten, titanium, tungsten nitride, titanium nitride, tungsten silicide, and titanium silicide.

23. The method of claim 15, wherein the extended second opening engages with the first opening; and wherein the formation of the channel material column comprises forming channel material within both the first opening and the second opening in a single step.

24. The method of claim 15, further comprising forming a first region of the channel material column within a first opening, forming the sacrificial material above the first region of the channel material column, and forming a second region of the channel material column within the extended second opening.

25. The method of claim 15, wherein the remaining area of ​​the uppermost first layer is adjacent to the trench, and the method further comprises filling the trench with the cushioning material and forming a planarized surface extending across the cushioning material and across the remaining area of ​​the uppermost first layer prior to forming the first opening.

26. The method of claim 15, wherein the first material and the third material are the same composition as each other.

27. The method of claim 15, wherein the first material and the third material comprise silicon nitride.

28. The method of claim 15, wherein the second material and the fourth material are the same composition as each other.

29. The method of claim 15, wherein the second material and the fourth material comprise silicon dioxide.

30. A method of forming an integrated assembly, comprising: Forming an alternating first layer and second layer of the first stack; The first layer and the second layer each include a first material and an insulating second material; A portion of the first stack is located within a memory block location; The trench is formed to extend through one or more of the first layers and to have a bottom along one of the second layers, with the lower portion of the first stack below the trench; the trench extends substantially completely across the memory block location; A cushioning material is formed within the trench; The first opening is formed to extend through the cushioning material and through the lower portion of the first stack; Sacrificial material is formed within the first opening; A second stack with alternating third and fourth layers is formed above the first stack, the cushioning material, and the sacrificial material; the third and fourth layers each comprise a third material and an insulating fourth material, respectively. The second opening is formed to extend through the second stack into the sacrificial material; The second opening extends through the sacrificial material; The extended second opening merges with the first opening to form a guide post opening extending through the first stack and the second stack; A unit material column is formed within the opening of the guide post; A gap is formed along the edge of the memory block location; The first material and the third material are removed by one or more etchants flowing into the gap; the removal of the first material and the third material creates voids within the first layer and the third layer. as well as One or more conductive materials are formed within the void.

31. The method of claim 30, wherein the cushioning material is insulating.

32. The method of claim 30, wherein the buffer material is conductive.

33. The method of claim 30, wherein the buffer material is semi-conductive.

34. The method of claim 30, wherein the buffer material comprises one or more of silicon, carbon-doped silicon nitride, aluminum-doped magnesium oxide, hafnium dioxide, zirconium oxide, and manganese oxide.

35. The method of claim 30, wherein the cushioning material comprises one or more of a metal oxide, a metal carbide, a metal boride, and a metal silicide.

36. The method of claim 30, wherein the unit material column comprises a charge blocking material, a charge storage material, a tunneling material, and a channeling material.

37. The method of claim 36, wherein the charge storage material comprises silicon nitride.

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